A back-end, CMOS compatible ferroelectric Field Effect Transistor for synaptic weights
Mattia Halter, Laura Bégon-Lours, Valeria Bragaglia, Marilyne Sousa, Bert Jan Offrein, Stefan Abel, Mathieu Luisier, Jean Fompeyriney
AA back-end, CMOS compatible ferroelectricField Effect Transistor for synaptic weights
Mattia Halter, ∗ , † , ‡ Laura Bégon-Lours, † Valeria Bragaglia, † Marilyne Sousa, † BertJan Offrein, † Stefan Abel, † Mathieu Luisier, ‡ and Jean Fompeyrine † † IBM Research GmbH - Zurich Research Laboratory, CH-8803 RÃijschlikon, Switzerland ‡ Integrated Systems Laboratory, ETH Zurich, CH-8092 Zurich, Switzerland
E-mail: [email protected]
Abstract
Neuromorphic computing architectures enable the dense co-location of memory andprocessing elements within a single circuit. This co-location removes the communi-cation bottleneck of transferring data between separate memory and computing unitsas in standard von Neuman architectures for data-critical applications including ma-chine learning. The essential building blocks of neuromorphic systems are non-volatilesynaptic elements such as memristors. Key memristor properties include a suitablenon-volatile resistance range, continuous linear resistance modulation and symmetricswitching. In this work, we demonstrate voltage-controlled, symmetric and analog po-tentiation and depression of a ferroelectric Hf . Zr . O (HZO) field effect transistor(FeFET) with good linearity. Our FeFET operates with a low writing energy ( fJ ) andfast programming time (
40 ns ). Retention measurements have been done over 4-bitsdepth with low noise ( ) in the tungsten oxide (WO x ) read out channel. By ad-justing the channel thickness from 15nm to 8nm, the on/off ratio of the FeFET canbe engineered from to
200 % with an on-resistance ideally >
100 kΩ , depending onthe channel geometry. The device concept is using earth-abundant materials, and is a r X i v : . [ c s . ET ] J a n ompatible with a back end of line (BEOL) integration into complementary metal-oxide-semiconductor (CMOS) processes. It has therefore a great potential for the fabricationof high density, large-scale integrated arrays of artificial analog synapses. Keywords ferroelectric switching, hafnium zirconium oxide, tungsten oxide, BEOL, ferroelectricfield-effect transistor, memristor
The development of new computing architectures has seen a substantial push since thescaling of conventional CMOS technology has come to its limits and cannot keep up withthe always increasing demand for computational power. A large part of today’s computingresources is dedicated to processing large amounts of data, such as images, videos, or sensoroutputs. For all these workloads, conventional von Neuman architectures are limited by afundamental, time and power consuming task of transferring data between the processor andthe memory. Brain-inspired neuromorphic architectures with co-located computation andmemory units appear as promising candidates to overcome this issue. Such architecturesconsist of neurons that are interconnected by plastic synapses, which can be arranged in acrossbar topology to efficiently perform matrix-vector multiplications âĂŞ a key comput-ing task when executing neural networks. In recent years, much progress has been madein neuromorphic hardware, in particular in creating crossbar arrays of artificial synapsesconnected to CMOS neurons.
Multiple device concepts have been proposed in order torealize the required artificial synapse, such as phase change memory (PCM), filamen-tary and non-filamentary resistive switching memory (RRAM), electro-chemical memory(ECRAM), and ferroelectric (FE) based memory cells. Unlike classical memoryelements, such devices are characterized by the stronger need for multilevel or analog pro-2ramming capabilities to define the synaptic weight. While PCM and RRAM devices areessentially current controlled, the different states in ferroelectric memory elements are con-trolled by applying an electric field. The states are linked to the partial switching of theferroelectric polarization, which allows to fine tune the synaptic weights in analog computingapproaches, with fast and low-power writing. For circuits solving real world applications, the number of required synapses rapidly ex-plodes with the complexity of the task at hand. Solving even a simple task such as theMNIST database of handwritten digits requires ≈ synapses, while the training of adeep neural network (DNN) relies on up to millions of synapses. Such numbers of hardwaresynapses can only be obtained in densely integrated circuits such as fabricated using modernCMOS technology. Part of the functions in neural networks can also be implemented usingCMOS circuits (e.g. activation). Therefore, it is important that materials and processes areCMOS compatible. The recent discovery of ferroelectricity in hafnia composites, a mate-rial already present in CMOS lines, has revived research activity in the field of integratedferroelectrics. Artificial ferroelectric synapses have been realized based on two device con-cepts, namely two-terminal ferroelectric tunneling junctions (FTJ) and three-terminalferroelectric field-effect transistors (FeFET). Hafnia-based FTJs remain a challengeas the stabilization of the ferroelectric phase in sub- thick structures becomes difficultand polarization drops at film thicknesses relevant for tunneling.
Using a transistorinstead has the advantage of separating the write process (low power write through highimpedance gate ) and the read process (through source-drain resistance). It also permitsto tune synaptic resistance by changing the channel geometry. Hafnia-based FeFETs weredemonstrated mainly as non-volatile memory cells, steep-slope field-effect transistors, and artificial neurons. These concepts usually are implemented on the front end of line(FEOL) and use Si as a channel. Because of the constraints imposed by the FEOL on thethermal budget and on the device geometry, an integration in the back end of line (BEOL)can be advantageous. E.g., an integration in the BEOL enable a larger device area with3espect to the size of the ferroelectric domains, which can translate into a larger number ofstates. Recently, analog synaptic behavior has been shown in a hafnia-based FeFET withindium gallium zinc oxide (IGZO) and poly-Si channels fabricated in the BEOL.
Thecombination of a hafnia-based ferroelectric with an oxide channel is expected to alleviate theknown issues associated with Si-based FeFETs such as unintended low-k interfacial layersformed at the Si interface. On Si based channels, buffer layers have been used as a solution,but they have the disadvantage of reducing the effective field over the ferroelectric layer.
For neuromorphic applications the absolute resistance should be in the MΩ range and therelative change in resistance ideally within a window of 8 up to 20-50. Those values area compromise between being large enough for performing learning tasks, and low enoughto avoid one synaptic element to dominate the respone of a whole column/row of the over-all crossbar array.
Here, we report on a Hf . Zr . O (HZO) based FeFET utilizing atungsten oxide (WO x ) channel. We demonstrate the impact of the ferroelectric polariza-tion on the channel resistance, the influence of the channel thickness on the on/off ratio,ferroelectric HZO with a long endurance, the stabilization of multiple differentiable states,a good retention as well as a continuous potentiation and depression. By using a BEOLcompatible process and by using only abundant and CMOS friendly materials, the proposedHZO/WO x stack is very promising for large-scale integrated neuromorphic hardware basedon ferroelectrics. For our study, we designed FeFET devices similar to back gated PseudoMOS with anHZO (
10 nm )/TiN (
10 nm )/ n + Si gate stack and an thick WO x channel (Figure1a). The channel is formed by oxidizing . of W after the formation of the ferroelectricHZO. The source and drain contacts are deposited on the WO x channel through lift-off.The device is encapsulated by a Al O and a
100 nm
SiO passivation layer. Contact4ads are formed on top of the passivation layers and routed through openings to sourceand drain. The gate is accessible through the highly n + doped Si substrate and is sharedbetween all devices on our chip. As visible in the bright field scanning transmission electronmicroscopy (BF-STEM), our fabrication process results in sharp interfaces between the layersand crystalline WO x grains (Figure 1b). The energy-dispersive X-ray spectroscopy (EDS)line profile confirms the targeted elemental distributions and reveals regions of intermixingbetween the various layers. After the low temperature crystallization of HZO by a millisecondflash lamp technique described elsewhere, grazing incidence X-ray diffraction (GIXRD)analysis shows the characteristic peak at 30.6Âř of the orthorhombic/tetragonal phase inHZO (Figure 1c). The diffractogram is consistent with data from metal-ferroelectric-metal(MFM) structures with the same HZO published in Ref. (46). No monoclinic phase (peaks at28.2Âř and 31.8Âř) is present in our samples, which is a consequence of the low temperaturecrystallization technique. Following the oxidation and crystallization of W to WO x , GIXRDstill shows no monoclinic HZO phase, but displays two additional peaks at 28.8Âř and 33.6Âřthat can be attributed to the monoclinic P121/c1 phase of WO x (ICSD-647640). For the electrical characterization of HZO in our FeFET devices, additional metal-semiconductor-ferroelectric-metal (MSFM) capacitor structures have been processed on thesame sample. "Capacitance versus voltage" ( C − V ) measurements on a µ m × µ m ca-pacitor reveal a ferroelectric typical butterfly-shaped hysteresis curve typical of ferroelectrics,with a capacitance per unit area of C OX = 2 . µ F / cm (Figure 2a). The asymmetric be-havior originates from the asymmetric electrodes (WO x , TiN). "Polarization versus voltage"( P − V ) measurements were performed on the same capacitor (Figure 2b) and show typicalcharacteristics. In the pristine state, the P − V curve is anti-ferroelectric (AFE)-like withhysteresis, especially on the negative voltage side. We applied switching cycles withan amplitude of ± . at a frequency of
100 kHz , resulting in a pinched P − V curve witha positive (negative) remanent polarization + P r = 12 . µ C / cm ( − P r = 11 . µ C / cm ). Fur-thermore, a slight imprint with a positive coercive voltage of + V C = 0 .
91 V and a negative5 b) (a)(c) Figure 1: Structural data of the FeFET. (a)
Schematic illustration of a FeFET, indicatingsource (S), drain (D), gate (G), a WO x channel and a ferroelectric HZO gate dielectric. (b) Cross-sectional BF-STEM image with energy-dispersive X-ray spectroscopy (EDS) lineprofile of the SiO /Al O /WO x /HZO/TiN/ n + Si gate region. (c)
GIXRD for a diffractionangle (2 θ ) from 26Âř to 38Âř showing the presence of the orthorhombic/tetragonal crystallinephase in HZO after crystallization and after the W layer was oxidized to WO x .one of − V C = − .
27 V are observed due to the asymmetric electrodes. The cycling enduranceof our HZO is for an MFM structure and × in the case of the MSFM configurationpresent in our FeFET (Figure S1).Having confirmed the ferroelectric nature of our HZO gate dielectric, the electrical char-acterization of the WO x channel in a FeFET device was performed next, by investigatingthe influence of P r , channel thickness ( d WOx ), and the channel carrier concentration ( N D )on the channel resistance ( R DS ). For that, three samples with different d WOx and one with anon-ferroelectric HfO gate dielectric were realized. R DS was measured between source anddrain after each µ s long write pulse ( V write ) applied to the gate (measurement scheme canbe seen in Figure S4). For ease of comparison, R DS is normalized by R ON (Figure 2c, d, e, f).A clear hysteresis in R DS is observed for devices with a ferroelectric HZO gate dielectric. Toconfirm that the modulation of the channel resistance originates from P r and not from an-other effect, an identical device with a non-ferroelectric HfO gate dielectric was measured.Both have an thick WO x channel. R DS shows no hysteresis in the non-ferroelectric6fO sample (Figure 2c) and further proves that the hysteresis originates from the ferroelec-tricity in HZO. In addition to the polarization in the HZO, the type and concentration ofthe free charge carriers as well as d WOx influence the on/off ratio. For a maximum re-duction in the channel off-current, the polarization-field induced depletion width ( x d ) shouldbe larger than d WOx . Using PoissonâĂŹs equation, the relationship between x d and N D canbe expressed as follows: x d = (cid:15) (cid:15) WOx C HZO "(cid:18) C V GS qN D (cid:15) (cid:15) WOx (cid:19) / − , (1)where (cid:15) is the vacuum permittivity, (cid:15) WOx the permittivity of WO x ( (cid:15) WOx = 189 , see supple-mentary information), C HZO is the HZO capacitance per unit area ( C HZO = 3 . µ F / cm ,Figure S5b), and V GS is the polarization charge-induced potential across HZO. The carrierconcentration ( N D = 1 . × cm − ), the channel resistivity ( ρ H = 3 . × − Ω cm ) andits mobility ( µ H = 0 .
19 cm V − s ) were determined by Hall measurements carried out on asimilar sample. Using Eq. (1), a depletion width x d = 1 . , . , . and . for V GS =1 V , , and , respectively was calculated (Figure S6b). For a constantpolarization, the largest effect is obtained if d WOx < x d = 6 . or N D < × cm − .Three samples with different d WOx were realized to benchmark this estimation with experi-mental data. BF-STEM measurements reveal d WOx = , . and
15 nm , as reportedin Figures 1b and S2a,b, respectively. The polarization does not change between the threestructures (Figures 2a and S3a,b). By decreasing d WOx from
15 nm to . and theon/off ratio increases from ≈ to ≈ and ≈
90 % , respectively. Those results agree wellwith the x d calculated by Eq. (1).For neuromorphic applications multiple (analog) levels of the channel resistance, goodretention properties, low device-to-device and cycle-to-cycle variations, fast updates, and lowpower consumption are important characteristics of ideal devices. The exact require-ments vary depending on the details of operation and from one implementation to the other.As an example, inference workloads would use off-line trained weights transferred to the chip7 d)(a) (e)(b) (f)(c)
Figure 2: Capacitance and polar-ization behavior of a µ m × µ m W/WO x /HZO/TiN/n + Si MSFM struc-ture and WO x channel resistance hys-teresis: (a) Capacitance versus voltage( C − V ) measurements after the HZOwas woken up by 20 C − V cycles. (b) Polarization versus voltage ( P − V )characteristics in the pristine state andafter cycles. (c, f ) Comparison ofsimultaneously processed samples withHZO and HfO gate dielectric. The nonferroelectric HfO sample does not showany channel resistance hysteresis. (d,e, f ) Influence of the channel thickness( d WOx ) on the on/off ratio.to operate the network, and the precision of the weights ( ≥ bit) is more relaxed as in thecase of a chip designed to perform on-line learning. In our device structure, weights are de-fined through the intermediate states of the channel resistance, enabled via the multi-domainnature of the ferroelectric HZO layer.
By switching only a subset of the domains, astate between R ON and R OFF can be set. The fraction of the switched ferroelectric domains8 a) (b)
Figure 3: Analog multi-level behavior of a FeFET of µ m width and µ m length. (a) Thechannel resistance ( R DS ) after the application of µ s write pulses ( V write ) of varying ampli-tudes. The different curves correspond to different consecutive measurements with reducing V write range. (b) Retention measurement for . V read , D = 200 mV was uninterruptedlyapplied while R DS was measured every .depends on the amplitude, width, and number of the applied write pulses. Different puls-ing schemes on HZO have been investigated in the past. For on-line learning algorithmsrunning on crossbar arrays integrated on CMOS, potentiation and depression pulse schemeswith a constant pulse amplitude and width are preferred to those with varying amplitude.Nevertheless, for the proof of concept the multi-state nature of a µ m wide and µ m longFeFET was investigated by applying voltage pulses of varying amplitudes, while keeping afixed pulse duration of µ s (Figure 3a). This pulse scheme results in the best linearity inpotentiation and depression. By sweeping V write from − to , R DS shows a hystereticcycle from
80 kΩ to
125 kΩ with various intermediate states (on/off ≈ . ). By reducing therange of V write numerous R DS sub-loops can be accessed, as shown in Figure 3a. The asym-metry in the hysteresis loop is due to the imprint in the ferroelectric layer. Furthermore, theretention properties have been studied, as demonstrated in Figure 3b. First, an intermediatestate was written by a µ s pulse. Then, a source-to-drain voltage V DS = 200 mV was appliedfor , while R DS was measured every . Between each measured intermediate state theFeFET was reset to its low resistive state ( R ON ) by setting V write = − during . The9 b)(a) (c)(d) Figure 4: Potentiation and depression of a µ m wide and µ m long FeFET. (a) The toppanel shows multiple potentiation and depression cycles of the channel resistance ( R DS )with varying pulse amplitude ( V write ) and constant pulse width ( t write ). The bottom panelshows the corresponding write pulse sequence . After each pulse R DS was measured. (b) Absolute cycle-to-cycle variation of R DS showing the data, average and standard deviationerror bars. (c) Standard deviation of the R DS cycle-to-cycle variation in percent. (d) Multiple potentiation and depression cycles of R DS with increasing t write from
40 ns to
250 ns and constant V write .FeFET showed stable retention properties for 18 differentiable channel resistances (>4bit)for the full . The good retention measurement hints to an absence of depolarization orother screening mechanisms. The obtained multistate storage capability, the long retentionand rather fast programming speed makes this FeFET suited for inference applications.For on-chip learning, artificial synapses require a finer mesh of intermediate levels. Inaddition, symmetric and linear potentiation and depression are desirable. With respect tosymmetry the field-driven ferroelectric switching is advantageous to other technologies thatoften show abrupt or unidirectional switching. The requirement of low variability is re-laxed as the training occurs on a specific hardware and thus incorporates the variability inits solution. To investigate the linearity and symmetry of the potentiation and depression,10ultiple write pulses of increasing and decreasing amplitude were applied. For the poten-tiation V write was increased from to . and for the depression decreased from to − with
100 mV steps (Figure 4a). The duration of the write pulses was kept constant at µ s . When averaging over several cycles (Figure 4b), multiple states with small standarddeviation are observed. Normalizing the cycle-to-cycle standard deviation by R ON reveals aconstant value of about (Figure 4c). The number and overlap of states are defined bythe potentiation and depression step size. The latter could be reduced further to increasethe resolution. When fitting the potentiation range from to . and depression rangefrom − . to − . by linear regression (Figure 5a), an adjusted residual-square valueof 0.952 is obtained. The residuals normalized by the R DS window as a function of pulsenumber is depicted in Figure 5b. For a more detailed analysis of the symmetry, Gaussianprocess regression (GPR) was used to predict a noise free signal (Figure 5c). Plotting ∆ R (Figure 5e) and the signal to noise ratio (SNR, Figure 5d) as a function of pulse numberreveals diminishing ∆ R and noisier signals towards the extremes. The symmetry factor (SF)was then calculated using the following equation: SF = | ∆ R + − ∆ R − ∆ R + + ∆ R − | , (2)where ∆ R + is the potentiation and ∆ R − is the depression change in resistance at a certainresistance level. By this definition, SF can take values between 0 and 1 where 0 is the perfectsymmetry. The less linear the range of the data becomes, the larger is SF (Figure 5d). Theaverage across the full resistance range is SF = 0 . while the most linear part in the centerreaches a very good symmetry factor of SF = 0 . .Short programming pulses are advantageous as fast writing and low-power consumptionare important for neuromorphic applications. By varying the pulse width from
40 ns to
250 ns with a fixed amplitude (Figure 4d), already the shortest applied pulse of
40 ns (equipmentlimit) changes the resistance and demonstrates very fast writing capabilities of the FeFET.It is expected that even shorter pulses could successfully program the device. In our device,11 e)(c) (f)(d)(b)(a)
Figure 5: Extraction of linearity and symmetry metric. Linear regression and the GPRmethodology is applied to our FeFET data from multiple cycles with: 22 potentiationpulses (blue) with increasing amplitude ( to . ) and 22 depression pulses (black) withdecreasing negative amplitude ( − . to − ). (a) R DS as a function of pulse number andthe linear regression fit (red). (b) Absolute residuals r normalized by the channel resistancewindow. (c) Channel resistance ( R DS ) as a function of pulse number and the GPR predictednoise free signal (red). (d) Absolute SNR for each potentiation and depression pulse. (e)
Absolute change of R DS after each potentiation and depression pulse. (f ) Symmetry factor(SF) as a function of R DS .little energy is consumed while writing a state. When applying V write = 3 . a gate currentof I gate = 3 . × − A is measured. Applying a write pulse duration of t write = 200 ns results in E = V write · I gate · t write w · l = 2 . × − J µ m − , where l is the length and w the width ofthe gate. We propose a device concept based on the ferroelectric field effect into a thin WO x channelusing HZO gate dielectric, that can be used as a synaptic element in hardware-supportedneural networks. The fabrication process is compatible with the integration in the BackEnd Of Line of CMOS technology and is using earth-abundant materials, which is making12t attractive for large-scale integration. By comparing HZO and HfO based devices, andcarefully analyzing capacitor and transistor data, we unambiguously show that the channelresistance is directly coupled to the polarization of the HZO layer and can be programmedin a non-volatile manner. Multilevel states programmed over more than 4-bits depth with agood retention and an almost symmetric potentiation and depression is obtained, togetherwith a low programming energy. The property of the WO x layer and the geometry of thedevice can be arranged so that a well-suited resistance range is obtained, favorable to buildlarge scale arrays. The proposed device exhibit therefore promising metrics when consideredas a synaptic element for processing cores supporting artificial neural networks. Future workwill concentrate on controlling the channel thickness and the carrier concentration of WO x to increase the on/off ratio, so that the device can be operated strictly in the linear region,without ever fully switching all the domains to the same polarization. This is expected toimprove symmetry and to allow a constant pulse scheme for potentiation and depression,which is more friendly to learning algorithms. Sample preparation.
Our FeFET is a bottom/gate device with shared gate. Thegate contact is accessed through the Si n + substrate. First,
10 nm
TiN was depositedusing a tetrakis(dimethylamino)titanium (TDMAT) precursor and N /H plasma in anOxford Instruments plasma enhanced atomic layer deposition (PEALD) system. An ap-proximately
10 nm thick layer of HZO was grown in a process using alternating cycles oftetrakis(ethylmethylamino)hafnium (TEMAH), and ZrCMMM ((MeCp)2Zr(OMe)(Me)) at ◦ C . Rutherford Back Scattering (RBS) analysis of the film (not shown) indicated anactual film composition of Hf . Zr . O . The sample was then immediately transferred to asputter chamber for the deposition of W. For the crystallization of HZO a millisecondflash lamp anneal (ms-FLA) with a background temperature of ◦ C was performed.13fter crystallization the W was reduced to ≈ . by Ar sputtering. The W wasthen crystallized and oxidized to
10 nm WO in a rapid thermal annealer (RTA) at ◦ C for with
50 sccm O . Afterwards a reduction of the WO to WO x was performed in aRTA by H annealing at ◦ C and vacuum annealing at ◦ C . WO x was further thinnedby Ar sputtering to . Source and drain were deposited by sputtering and liftoff. Thepassivation consists of Al O by thermal ALD (precursor) and
100 nm
SiO by plasma-enhanced chemical vapor deposition (PECVD). Vias were etched using a reactive ion etcher(RIE) with a CHF /O plasma. Finally, the contacts were realized by depositing
100 nm
Wby sputtering and defined in an RIE with a SF /O plasma. Structural Characterization.
Grazing incidence X-ray diffraction (GIXRD) measure-ments were performed in a Bruker D8 Discover diffractometer equipped with a rotating anodegenerator. TEM lamellas have been prepared by Focused Ion Beam using a FEI FIB He-lios FEI Helios NanoLab 450S and investigated with a double spherical aberration-correctedJEOL JEM-ARM200F microscope. Bright field STEM (BF-STEM) images have been ac-quired at 200 kV and Energy Dispersive x-ray Spectroscopy (EDS) line profiles have beenperformed using a liquid-nitrogen-free silicon drift detector.
Electrical Characterization. R DS − V write and retention were measured using an Ag-ilent B1500. V write pulses were generated by a WGFMU and RSU module for the AgilentB1500 and applied to source and drain simultaneously while grounding the gate (Figure S4a). R DS was measured by applying an IV-sweep from −
200 mV to
200 mV to the drain whilehaving the source connected to ground (Figure S4b). R DS was then determined by averagingthe resistance at ±
200 mV . P − V loops on HZO were recorded using a TF Analyzer 2000from AixAct. The signal of was applied to the top W/WOx contact while the bottomTiN/ n + Si contact (substrate) was grounded. For the wake-up of HZO, cycles of ± . and
100 kHz were applied. 14 upporting Information Available
The following files are available free of charge.The Supporting Information is available free of charge on the ACS Publications websiteat DOI:• Additional data concerning the endurance of MFM and MSFM structures, BF-STEMand P − V measurements on additional samples, electrical measuring schemes, capac-itance measurements and permittivity and depletion width calculations. (PDF) Acknowledgement
We acknowledge helpful discussions with Nanbo Gong and Takashi Ando. This projecthas received funding from the European Commission under grant agreement H2020-ICT-2016-1-732642 (ULPEC).
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E-mail: [email protected] S1 a r X i v : . [ c s . ET ] J a n a) (b) Figure S1: Endurance measurements of
10 nm
HZO. The total remanent polarization( P = | P r − | + | P r+ | ) was determined by positive up negative down (PUND) measurementswith and ± . . The cycling frequency was set to up to cycles,
10 kHz upto cycles and
100 kHz for cycles above : (a) The TiN/HZO/TiN MFM configura-tion was cycled at ± . . (b) The W/WO x /HZO/TiN MSFM configuration was cycled at ± . with a − . offset. (a) (b) Figure S2: Cross-sectional BF-STEM images of the samples from the WO x thickness series: (a) d WOx = 11 . , (b) d WOx = 15 nm S2 a) (b) Figure S3: P-V measurements on the samples from the WO x thickness series. Polarizationversus voltage ( P − V ) characteristics measured on µ m × µ m W/WO x /HZO/TiN/n + SiMFM structures at in the pristine state and after cycles: (a) d WOx = 11 . , (b) d WOx = 15 nm . (b)(a) Figure S4: Write and read schematic showing a semiconductor parameter analizer (B1500)with the waveform generator/fast measurement unit (WGFMU) and its two remote-senseand switch units (RSU): A state is written by applying a pulse to source (S) and drain (D)while the gate (G) is grounded. The channel resistance is read by applying an IV-sweep from −
200 mV to
200 mV to D while having S connected to the common ground through SMU2.S3 a) (b)