A Comparative Study between HLS and HDL on SoC for Image Processing Applications
AA Comparative Study between HLS and HDL onSoC for Image Processing Applications
Un Estudio Comparativo entre HLS y HDL en SoC para Aplicaciones de Procesamiento de Imágenes
Roberto Millón ∗ , Emmanuel Frati ∗ and Enzo Rucci † ∗ Departamento de Ciencias Básicas y Tecnológicas, UNdeCChilecito (5360), La Rioja, Argentina [email protected] [email protected] † III-LIDI, Facultad de Informática, UNLP - CIC.50 y 120 s/n, La Plata (1900), Argentina [email protected] Abstract —The increasing complexity in today’s systemsand the limited market times demand new development toolsfor FPGA. Currently, in addition to traditional hardwaredescription languages (HDLs), there are high-level synthesis(HLS) tools that increase the abstraction level in systemdevelopment. Despite the greater simplicity of design andtesting, HLS has some drawbacks in describing hardware.This paper presents a comparative study between HLSand HDL for FPGA, using a Sobel filter as a case studyin the image processing field. The results show that theHDL implementation is slightly better than the HLS versionconsidering resource usage and response time. However,the programming effort required in the HDL solution issignificantly larger than in the HLS counterpart.Keywords: FPGA; SoC; Sobel; HDL; HLS.
Resumen—
La creciente complejidad de los sistemasactuales y los tiempos limitados del mercado exigen nuevasherramientas de desarrollo para las FPGAs. Hoy en día,además de los tradicionales lenguajes de descripción dehardware (HDL), existen herramientas de síntesis de alto nivel(HLS) que aumentan el nivel de abstracción en el desarrollode sistemas. A pesar de la mayor simplicidad de diseño ypruebas, HLS tiene algunos inconvenientes para describirhardware. Este documento presenta un estudio comparativoentre HLS y HDL para FPGA, utilizando un filtro Sobelcomo caso de estudio en el ámbito del procesamiento deimágenes. Los resultados muestran que la implementaciónHDL es levemente mejor que la versión HLS considerandouso de recursos y tiempo de respuesta. Sin embargo, elesfuerzo de programación en la implementación de HDL essignificativamente mayor.Palabras clave: FPGA; SoC; Sobel; HDL; HLS.
I. I
NTRODUCTION
FPGAs are in an intermediate position between ASICsand CPUs, given their ability to reconfigure their archi-tecture according to the application and their good energyefficiency [1]. In the last decade, multiple efforts havebeen made to reduce the energy consumption of largecomputing systems [2] and FPGAs are consolidating as aviable alternative to achieve this goal. That is why several
The final authenticated version is available online at https://doi.org/10.37537/rev.elektron.4.2.117.2020 companies and organizations have incorporated this kindof hardware devices to their systems, like Microsoft [3],Baidu [4], CERN [5] or Amazon [6].However, FPGAs have not been massively adopted as itwas originally expected by their vendors [7]. At the begin-ning and for more than one decade, FPGA applications wereexclusively developed using hardware description languages(HDLs). Unfortunately, HDLs have many drawbacks: theyare verbose and error-prone, require in-depth knowledge ofdigital electronics, and demand long development times [8].As a result, the FPGA community explored alternativetools to increase the abstraction level as a way to reduceprogramming costs and accelerate time to market [9].Since the early 2000s, several FPGA vendors started tooffer high-level synthesis (HLS) tools for systems devel-opment. In the HLS approach, programmers code FPGAapplications using high-level languages (HLLs), like C, C++,or SystemC. Then, the tool is responsible for generating thecorresponding HDL code [10]. Thus, engineers work at ahigher abstraction level and produce reusable hardware de-signs without requiring hardware expertise. This alternativeapproach allowed the industry to shorten time to marketsince productivity gets increased while development costgets reduced [11].Even though HLS tools present several advantages todevelop hardware descriptions, they also have a weak spot.As HLLs were designed for software applications, theypresent some shortcomings when describing hardware thatcan negatively impact the resources usage and response timeof the final hardware designs [12].In this context, it is important to know the advantages anddisadvantages of different languages and approaches to syn-thesize optimal hardware descriptions. This paper presentsa comparative study between two Sobel filter solutions for aSystem-on-Chip (SoC) platform using both HDL and HLSapproaches. Overall, the main contributions of the paper arethe following: • The creation of a public git repository containing opti-mized SoC solutions of Sobel filter for edge detection a r X i v : . [ c s . A R ] D ec sing both HDL and HLS approaches . As Sobel isa convolutional operator, these implementations canbe easily adapted to perform other image processingfilters. • A thorough comparison between both solutions interms of resource usage, execution time, and program-ming effort. In this way, we can identify the strengthsand weaknesses of each programming approach in theimage processing field.The rest of the paper is organized as follows. Section IIpresents the background and the state of the art of this work.The optimized implementations are described in Section III.In Section IV, experimental results are analyzed and finally,in Section V, conclusions and some ideas for future researchare summarized.II. B
ACKGROUND AND S TATE OF THE A RT A. FPGA Programming Languages
Verilog and VHDL are the two leading HDLs to describe,simulate, and synthesize hardware systems. Both were devel-oped in the 80’s and have been updated several times sincethen [13]. Using HDL to describe hardware requires digitaldesign expertise, which limits the use of FPGA to hardwareengineers. The results are low-level, complex designs, andslow development and debugging processes.The HDL drawbacks lead to the development of new toolsto describe hardware in the early 2000s, such as Vivado HLS(Xilinx), Catapult C (Mentor Graphics), and Intel OpenCLSDK (Intel). These HLL-based tools raise the abstractionlevel and increase FPGA opportunities to engineers thatspecialize in embedded software programming [14].Unfortunately, C-based languages have some shortcom-ings when describing hardware. First, either the designer orthe HLS tool must specify the concurrency model becauseof HLLs lack a definition of hardware timing. Second,HLLs lack of the definition of exact bit width for a signal,since they only provide limited data types such as bool,int, and/or long. Third, HLLs do not have abstractions ofhardware interfaces and, contrary to the distributed memorymodel of FPGAs, they assume a flat memory model thatcan be accessed through pointers. Therefore, HLS tools mustprovide extensions to the HLL through libraries and directivesets to overcome those deficiencies. In other cases, HLStools impose restrictions on HLLs, such as not supportingdynamic memory allocations [12].
B. Sobel Filter
The Sobel algorithm is a gradient-based edge detectionmethod to extract the edges of a grayscale image usingthe first derivative. By computing horizontal h and vertical v direction derivatives of a pixel against the surroundingpixels, the algorithm segments the image into areas orobjects. This process reduces the amount of data whilepreserving the image’s structural properties. The G h and G v derivatives represent the components of the gradientvector [15], [16], given by Equation 1. ∇ f = ( G h , G v ) (1) https://github.com/robertoamt/HDL-HLS-Sobel-filters- The gradient magnitude expresses the rate of change ofintensity in neighboring pixels and defines the edge strength.A sudden change in contiguous pixels increases the gradientmagnitude resulting in the border of an object, given byEquation 2: |∇ f | = (cid:113) G h + G v (2)Equation 2 can be approximated as Equation 3. This lastformula delivers a faster computation but still preservingrelative changes in intensity. |∇ f | ≈ | G h | + | G v | (3)Fig. 1 shows the two × convolution masks (namely, M h and M v ) used by the Sobel filter to calculate the componentsof the gradient vector. Fig. 1. Sobel convolution masks
From mathematical point of view, the image must bemultiplicated by the Sobel masks to get the components ofthe gradient vector. The image is scanned from left to rightand top to bottom, applying convolution to each individualpixel using the M h and M v masks [17]. Fig. 2 shows theconvolution process of the Sobel filter. Fig. 2. Sobel convolution process
C. State of the Art
In the literature, numerous works propose HLS or HDLsolutions to different problems. However, just a few im-plement the same algorithm with both HLS and HDL de-scriptions. Some studies conclude that both implementationshave similar performance results with a larger resource con-sumption on the HLS approach [8], [18]–[22]. Conversely,other studies observed better performances in one of thetwo implementations, either HLS [23]–[27] or HDL [28],[29]. From the programming effort perspective, comparativeworks between HLS and HDL designs for FPGA showsimilar trends (except for [30]). In general, HLS descriptionsrequire less development time due to their higher abstractionlevel and the programmer’s familiarity with those languages.However, there is no single conclusion about performanceand resource usage between the two approaches. In these as-pects, the results are affected by the problem characteristics,the tools used, and the design features.his research presents and compares two optimized Sobelfilter solutions for a SoC platform designed with both HLSand HDL approaches. Compared to previous works, thenovelty of this study lies in the hardware and softwaretechnologies used, the chance to reuse/modify the solutionsimplemented, and the careful comparative analysis carriedout. In this way, we can contribute to the identification of thestrengths and weaknesses of each programming approach inthe image processing field.III. I
MPLEMENTATION
To compare both HDL and HLS approaches, we haveimplemented a complete Sobel system to detect edges onRGB images (BMP format). Firstly, a DMA block accessesthe microSD memory for image reading and sends thepixel stream to the processing core. After Sobel operation,the processing block returns the pixel stream to the DMAblock for further storage in the microSD memory. TheARM processor is responsible for configuring and managingthe system. Finally, all modules were integrated using theVivado 2019.1 tool. Fig. 3 shows a block diagram of thewhole system.
ARM Processor
DDR memory controller AXI DMA
RGB2GRAYAXI-LITEAXI AXISTREAM SOBEL FILTERU8toU32FPGA
Fig. 3. Complete Sobel system
The processing core consists of 3 blocks that were synthe-sized and validated using both HDL and HLS approaches.The first block (RGB2GRAY) converts RGB images tograyscale using the method based on the arithmetic meanof the three components; the second block (SOBEL FIL-TER) detects the edges in the image; and the third block(U8toU32) combines four 8-bit integer variables to form a32-bit word.
A. HLS Version
To implement the Sobel filter on HLS, we use twomemory structures called line buffer and sliding window [31]. Each line buffer correspond to an entire row of theimage and we used them to keep the Sobel working set. Onits behalf, the sliding window contains the image pixels thatwill be convoluted.The filter requires three line buffers that are arranged oneabove the other. When a new pixel is received, the linebuffers perform a vertical rotation before storing the newpixel. When the two upper line buffers are full and threepixels are in the lowest line buffer, the convolution processis performed using the sliding window pixels and the Sobelmasks. Fig 4 illustrates the described process. p p p p p p p p p p New pixelinput and Convolution operationp p p p p p p p p p p p p Valid pixel New pixel Sliding WindowVerticalrotation inline buffersp p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p Input Image Output Image
Fig. 4. Sobel filter operation in the HLS implementation
Several compiler directives were used to optimize synthe-sis and reduce programming costs. To communicate the im-age and its parameters, the system uses AXI4 interfaces thatwere synthesized using the
HLS INTERFACE pragma. Thedesign also incorporates two compiler directives to achievebetter performance:
HLS ARRAY PARTITION pragma al-lows parallel memory accesses to line buffers, slidingwindow and masks; and the
HLS PIPELINE pragma toincrease throughput by enabling parallel execution of con-volution tasks.
B. HDL Version
As the HLS version, the HDL implementation also usesline buffers and sliding window data structures. However, itjust requires two line buffers and not three of them. PreviousHDL solutions [32]–[34] use shift registers to describe theline buffers, which results in a larger use of FPGA registers.To decrease the use of registers, our design uses two blocksof RAM RAMB18 (one physical RAMB36) as line buffers(namely line_buffer_1 and line_buffer_2 ). We synthesizedthe sliding window as three shift registers composed of threeflip-flops each (9 registers in all). Fig 5 represents the HDLimplementation of Sobel filter.
D (data_in)W_Addr W_en
LB_1
R_en R_Addr W_Addr W_en D (data_in) Q (data_out)R_en R_Addr Q (data_out)
NEW PIXEL SLIDINGWINDOW
LB_2
BRAMBRAM
Fig. 5. Synthesis of Sobel filter in HDL implementation
Sobel filter performs four tasks, each requiring one clockcycle. The first task is comprised of two actions: the recep-tion of a new pixel and the reading of the line buffers. Thesecond task is composed of two actions too: the filling of thesliding windows and the writing in the line buffers. In thenext clock cycle, the filter performs the convolution. Finally,the filter sends the processed data in the fourth cycle. Thisprocess is shown in Fig. 6.Unlike the HLS design, the HDL system must describe theAXI4 connection interfaces at a lower level (AXI-STREAM p p p p p p p p p Valid pixel New pixel New pixel input and line buffers readingp p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p Input Image Output Imagep p p p p p p Line Buffers Sliding Windowp p p p p p p p Line bufferswriting andsliding windowfillingp p p p p p p p p p p p p p p p p p p p p p p p p p p p Convolutionprocess
Fig. 6. Sobel filter process in HDL implementation and AXI-LITE). As it was mentioned before, the completeprocess was divided into four stages, incorporating registersbetween them. Although these additional registers increasethe latency, they allow this design to overlap the differenttasks in the same clock cycle. In this way, a pipeliningscheme is manually achieved (no compiler directives), whichincreases system throughput and shortens response time. Thepipelined tasks are shown in Fig. 7.
New pixel input and line buffers readingLine buffers writing and sliding window fillingConvolution processData sendingTask Clock cyclePixel 1 Pixel 2 Pixel 3Pixel 1 Pixel 2 Pixel 3Pixel 1 Pixel 2 Pixel 3Pixel 1 Pixel 20 1 2 3 4Pixel 4Pixel 4 Pixel 5
Fig. 7. Pipelined scheme in HDL implementation
IV. E
XPERIMENTAL R ESULTS
The SoC used for testing is a ZYBO platform (SoCZYNQ-7000), which consists of an ARM Cortex-A9 dual-core processor and an XC7Z010-1-CLG400C FPGA. Tosystem design, we have used the graphical environmentwithin the Vivado Design Suite software. We developeda test application using the XSDK tool and also selectedfour images from public repositories:
Mandrill of 512 × , Kodim23 of 768 × , Owl of 1920 × , and Lightbulbs of 1920 × . Each particular test was run ten times;performance was calculated by the average of ten executionsto avoid variability. All time measures were performed withthe xtime_l.h library. A. Edge Detection
Fig. 8 shows the testing images with their correspondingresulting image after applying the Sobel filter. The approxi-mated formula from Equation 3 was used to compute thegradient magnitude. Last, we have compared the result-ing images of both approaches (HDL & HLS) using an http://sipi.usc.edu/database/database.php https://pixabay.com/es/photos/lechuza-granero-ave-animales-1710659/ https://pixabay.com/es/illustrations/bombillas-de-luz-para-vidrio-5488573/ automated procedure based on the Hamming distance. Nodifference between images were found in all cases. (a)(b)(c)(d)Fig. 8. Test images. (a) Mandrill . (b)
Kodim23 . (c)
Owl . (d)
Lightbulbs . . Resource Usage and Performance Table I presents the resource usage for the two So-bel implementations. The values in the columns
S.LUTs , S.Registers , F7 Muxes , BRAM , and
DSPs refer to thepercentages of lookup tables, registers, multiplexers, RAMblocks, and DSP blocks used, respectively. In particular, theHLS version requires 5.5 × more LUTs and 4.6 × more reg-isters than the HDL counterpart. Still, it does not representa design restriction in either case. TABLE IR
ESOURCE USAGE
Version Resource usage (%)
S.LUTs S.Reg F7 Muxes BRAM DSPsHDL 0.8% 0.5% 0% 1.6% 0%HLS 4.4% 2.3% < Table II presents the runtime of each Sobel version. Foreach testing image, we present two times: (1) the opera-tion time of the processing blocks (RGB2GRAY, SOBELFILTER, and U8toU32) labeled as
Sobel , and (2) the I/Otime of the system labeled as
I/O . Also, the last columnshows the speedup ratio between the HLS runtime andthe HDL runtime . As it can be seen in the results, theHDL filter is faster than the HLS version in all cases. Thelargest performance difference is achieved when processingthe smallest image ( Mandrill ), reaching a speedup of 6.6 × .The difference decreases as the size of the image increases,but the HDL version still shows superior to the HLS coun-terpart obtaining a speedup of 1.4 × for the largest image( Lightbulbs ). TABLE IIP
ERFORMANCE
Image Task Runtime (ms)
HDL HLS Speedup
Mandrill Sobel × (512 × I/O
816 837 -
Kodim23 Sobel × (768 × I/O
Owl Sobel × (1920 × I/O
Lightbulbs Sobel
58 82.9 1.4 × (1920 × I/O
The HDL implementation outperformed the HLS versionfor both resource usage and performance. Both issues arerelated to the automated process that Vivado HLS followsto translate the HLL code to the corresponding hardwaredescription. The resulting RTL requires a larger number This value is only computed for the Sobel column of each image. TheI/O time is approximately the same for both versions since they share theI/O operation of finite state machines and signals to ensure its correctoperation, increasing resource consumption and responsetime.
C. Programming Cost
There are several proposals for measuring the program-ming cost of an application. Some of them propose countingthe number of lines of code (SLOC) or the number ofcharacters (including blank lines and comments). Despitetheir simplicity, the main drawback is that these parametersdo not reflect the complexity of the algorithms [35]. Otheralternatives measure the development time, even though it isdependent on the programmer experience. In this work, wehave decided to measure the programming cost through theSLOC indicator and the development time invested to reacha complete and functional implementation. These metricsare combined with a qualitative comparison of the requiredeffort in each solution. As both parts are complementary,they allow the reader a comprehensive understanding of theprogramming cost.Table III shows the number of files, SLOC , and de-velopment time (in hours) for each approach. The projectinvolved a single programmer having minimal knowledgeabout FPGA programming . The HLS version was de-veloped first, taking him 121 hours and 90 SLOC to geta correct implementation of the entire system. Next, theprogrammer continued with the HDL implementation. It isimportant to remark that, implementing the HLS versionfirst gave some advantage to the HDL implementation dueto the knowledge gained in that process. Despite that, thedevelopment time increased to 384 hours and 493 SLOC.This represents an increase of 5.5 × SLOC and 3.2 × hourscompared to the HLS version. TABLE IIIP
ROGRAMMING COST
Version Programming cost
The HDL implementation required more time and SLOCthan its HLS counterpart. This is due to the HLS approachallowed the programmer to focus on the system functionalitywithout requiring him to define hardware resources and/orother low-level mechanisms. For example, communicationports and pipelining scheme were implemented using com-piler directives in the HLS approach. In the opposite direc-tion, the programmer had to manually describe them at RTLlevel in the HDL approach.V. C
ONCLUSIONS AND F UTURE W ORK
In this work, we present a comparative study beweenHLS and HDL approaches for FPGA programming. Taking To measure the SLOC indicator, we have used the cloc tool https://github.com/AlDanial/cloc The programmer took two undergraduate semester courses in the field. he Sobel filter as a study case, we implemented optimizedSoC solutions for detecting edges in images and made themavailable through a public git repository. Next, we performeda thorough comparison between HDL and HLS in termsof resource usage, execution time, and programming effort.As Sobel is a convolutional operator like many others, wecan identify strengths and weaknesses of each programmingapproach in the image processing field.The results show that the HDL implementation is slightlybetter than the HLS version considering resource usage andresponse time. However, the programming effort requiredin the HDL solution is significantly larger than in the HLScounterpart. According to these results, the HDL approachwould only be convenient when the resource usage and/orthe response times are critical. Otherwise, the HLS approachcan lead to important reductions in both programming costand development time, at the cost of a small increase inresource usage and execution time.Future work focuses on extending the experimental workcarried out to other boards. This would allow us to enlargethe representativity of the analysis performed.A
CKNOWLEDGMENT
This work was partially supported by the “Software yaplicaciones en computación de altas prestaciones” project,RR Nº 883/18 (UNdeC).R
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