A Survey of Aging Monitors and Reconfiguration Techniques
Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes
11 A Survey of Aging Monitors and ReconfigurationTechniques
Leonardo R. Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm MoraesPUCRS Av. Ipiranga 6681, Porto Alegre, Brazil – [email protected]
Abstract
CMOS technology scaling makes aging effects an important concern for the design and fabrication of integratedcircuits. Aging deterioration reduces the useful life of a circuit, making it fail earlier. This deterioration can affect allportions of a circuit and impacts its performance and reliability. Contemporary literature shows solutions to monitorand mitigate aging using hardware and software monitoring mechanisms and reconfiguration techniques. The goalof this review of the state-of-the-art is to identify existing monitoring and reconfiguration solutions for aging. Thissurvey evaluates the aging research, focusing the years from 2012 to 2019, and proposes a classification for monitorsand reconfiguration techniques. Results show that the most common monitor type used for aging detection is tomonitor timing errors, and the most common reconfiguration technique used to deal with aging is voltage scaling.Furthermore, most of the literature contributions are in the digital field, using hardware solutions for monitoringaging in circuits. There are few literature contributions in the analog area, being the scope of this survey in thedigital domain. By scrutinizing these solutions, this survey points directions for further research and developmentof aging monitors and reconfiguration techniques.
Index Terms
Aging monitors, reconfiguration techniques, survey.
I. I
NTRODUCTION
With the scaling of CMOS technology circuit reliability issues become increasingly relevant for the design ofintegrated circuits. Among these issues, circuit aging is getting critical, as it inevitably affects all circuits. Theliterature shows an increase in the number of papers related to aging between 2000 to 2020 [1], [2], [3]. This trendis due to the development of ultra-deep submicron technologies, where reliability became crucial [4].Aging is the deterioration of circuit performance over time [5], which can reduce the useful life of a circuit. Thisdeterioration can increase circuit delay and affect all portions of a System-on-Chip (SoC), analog circuit, digitallogic, and memory. One important factor that accelerates aging is power. The increase of power in modern circuitsincreases the temperature and makes these circuits susceptible to effects like bias temperature instability (BTI) andhot carrier injection (HCI) [6].One solution to deal with aging effects is to add design safety margins to the circuit, such as clock margins. Thesemargins ensure correct operation even in the presence of aging effects once they are designed according to worst-caseconditions. However, these margins decrease performance, as they increase the clock period. The literature presentsother solutions to mitigate aging, allowing to extend the lifetime of chips. These solutions monitor parametersthat indicate aging effects. The monitored parameters include temperature, frequency variation, delay variation,among others. Decision methods, as threshold voltage analysis, evaluate whether the monitored parameters have anappropriate range of values. Activation mechanisms, such as voltage and frequency adaptations, bring the circuitback to the safe parameters if these do not meet predefined constraints.The goal of this review is to study existing solutions for monitoring aging effects in circuits and dealing withthem. This study seeks to answer two questions: (i) what solutions the literature presents for aging monitoring? and (ii) what solutions the literature presents for circuit reconfiguration? This work surveys the literature from 2012to 2019, while works [7], [8], [9] map aging monitors since 1998. Thus, this survey fills the gap related to agingsurveys, covering the most recent works.The literature review considered three main search terms: • Integrated Circuits : this category limits the search to the area of integrated circuits. The search string presentsthe terms used to reference this area, like VLSI, system, and architectures; a r X i v : . [ c s . A R ] J u l • Monitoring and Self-reconfigurable Circuits : this category includes the monitoring area and the problemsinduced by aging, as Negative-Bias Temperature Instability (NBTI); • Aging
ASIC D EFINITIONS
This section provides definitions required for the understanding of this survey.
Definition 1.
Critical path : is the purely combinational path with the most significant delay between any tworegisters or primary I/O ports in a design.
Definition 2.
Soft-errors : errors that can occur in a circuit when it is exposed to radiation, like cosmic rays andneutrons particles. Single-event upset (SEU) is an example of soft-error, when the exposition to radiation cangenerate a change in the memory elements values, generating erroneous outputs [10].Important effects are considered in the aging research: NBTI (Definition 3), PBTI (Definition 4), HCI (Definition5).
Definition 3.
NBTI – Negative Bias Temperature Instability: increase in the threshold voltage and consequentlydecrease drain current and transconductance of a transistor [11]. It occurs in PMOS transistors and is caused bycircuit aging.
Definition 4.
PBTI – Positive Bias Temperature Instability: similar to NBTI, but in NMOS transistors. Since theintroduction of the high-K gate dielectrics and metal gates transistors, the effect of PBTI becomes comparable tothe NBTI one.
Definition 5.
HCI – Hot-Carrier Injection: consists of a voltage drop that produces a large electric field in theregion near to the drain of a transistor in saturation mode. It can result in the change of transistor characteristicssuch as the threshold voltage [12]. According to Novak et al., from Intel, [13], tri-gate technologies as 14nm canhelp to mitigate HCI effects toghter with body bias adjust techniques.Classic test approaches are adopted for aging monitoring and reconfiguration techniques: DfT (Definition 6),BIST (Definition 7), ATPG (Definition 8).
Definition 6.
DfT – Design for Testability: a set of techniques used to improve circuit testability by increasingcontrollability and observability in the design [14].
Definition 7.
BIST – Built-in Self-Test: a mechanism that tests the circuit itself, verifying all or a portion of theinternal functionality of the design [14]. The hardware and/or the software is built into integrated circuits allowingthem to test their operation. The main advantage of BIST is the ability to test internal circuits having no directconnections to external pins or external testers. In addition, BIST allows testing in the field.
Definition 8.
ATPG –Automatic Test Pattern Generation: a method that finds an input sequence (called test vectors)that enables automatic test equipment (ATE) to distinguish between the correct circuit behavior and the faulty circuitbehavior caused by defects. III. P
REVIOUS A GING S URVEYS
Rahimipour et al. [7] review on-chip monitors for temperature, soft-errors (Definition 2), and critical paths (Defi-nition 1), covering the period 1998-2011 (21 works). Figure 1(a) presents their classification divided in: monitors for high temperature induced problems; monitors for soft-errors; monitors for critical paths; and collaborative monitors,which combines the previously mentioned class of monitors. Soft-errors detects change caused in memory elementsdue radiation. Thermal monitors identify problems induced by high temperatures. Critical path delay monitors detectchanges in the critical path, as delay increases. Collaborative monitors are a combination of more than one classof monitors. Figure 1(b) summarizes the monitor types and also informs cause, effect, and control action for eacheffect.
Juracy et al. : A Survey of Aging Monitors and Reconfiguration Techniques
ON CHIP MONITORSTHERMAL MONITORS SOFT ERRORS MONITORS CRITICAL PATH DELAY MONITORS COLABORATIVE MONITORS (a) Typical examples of monitors.
Magnitude Cause Adverse Effect Control Action
Temperature Localizedpowerconsumption Performance /Reliabilityloss DVFS /ClockthrottlingCritical Path Timinguncertainties Speed loss DVFSSoft Error ncreasing insystemoperatingfrequencies Reliabilityloss BackwardrecoveryAging ProlongedUsage Speedreduction/Malfunction DVFS (b) Monitor types and control actions.
FIGURE 1.
Monitors types and control actions. Adapted from [4]. (controlled resource wearout), or availability of expendableresources (spatial redundancy).
AGING ADAPTATION AND MITIGATION TECHNIQUESWORST-CASE DESIGN DESIGN TIME AGING-AWARE BALANCING DYNAMIC ADAPTATION TECHNIQUES ADAPTIVE RESOURCE MANAGEMENTVOLTAGE MARGINGATE SIZING FREQUENCY MARGIN PATHSGATES INSTRUCTION PIPELINE STAGES VOLTAGE AND FREQUENCY SCALE COMPUTATIONAL SPRITING CONTROLLED RESOURCE WEAROUTITL SCHEME SPATIALREDUNDANCY
FIGURE 2.
Taxonomy of aging mitigation techniques. Adapted from [5].
Kochte et al. [6] review the period 2007-2017 (14works). Their work analyses self-test, self-checking, andself-diagnosis online techniques for self-awareness. Onlinetechniques include aging monitors. Figure 3 shows the clas-sification for self-test and self-checking, which contains non-concurrent and concurrent approaches. Non-concurrent ap-proaches regard self-testing methods, including classic meth-ods, as BIST, and techniques like suspending the circuitoperation to execute the test. Concurrent approaches areself-checking methods executed during the circuit operation,which includes aging monitors.
IV. PROPOSED CLASSIFICATION OF AGING MONITORSAND RECONFIGURATION TECHNIQUES
Our proposed classification extends the taxonomy of pre-vious work [4]–[6], considering parameters included in thestate-of-the-art and features of the circuits monitored bythem. Thus, this work proposes the following set of parame-ters for aging monitors classification: • Temperature : a temperature monitor detects aging ef-fects by measuring the variation in the temperature ofthe circuit. Temperature variations cause aging effectsas NBTI and PBTI; • Critical path : critical path monitors can be used toidentify timing errors due to wrong transitions, SEU,
ONLINE
NON-CONCURRENTPOWER-ON ON-DEMAND PERIODICAL CONCURRENTBIST SELF-TEST USING STORED DETERMINISTIC PATTERNSSOFTWARE-BASED SELF TEST MEMORY BIST CONCURRENT BISTSELF CHECKING DESIGN / CONCURRENT ERROR DETECTIONLOCKSTEP EXECUTIONSYNTHESIZED ASSERTIONS WATCHDOG ALGORITHM-BASED FAULT TOLERANCENON-FUNCTIONAL MONITORS
SELF-TEST AND SELF-CHECK METHODSSELF-TESTING SELF-CHECKING
FIGURE 3.
Self-test and self-checking circuits classification. Adapted from [6]. or delay increase on circuit paths. These errors aredetectable by comparing a circuit path controlled by thesystem clock and the same path controlled by a delayedclock [11]; • Clock frequency : clock frequency monitors measure thefrequency variation of a clock circuit under aging. Thistype of monitor uses a reference frequency to identify achange in the circuit operating frequency; • Workload : workload monitors measure the workload ofa circuit to identify the stress level. Similar to the CPUload measure. • Circuit state : circuit state monitors consider the state ofthe entire system. For example, some techniques use theBIST circuit output to evaluate aging effects; • Voltage : Voltage monitors analyze the threshold voltageof the circuit. Aging effects as NBTI can change thethreshold voltage of transistors.Table 1 presents the aging monitors addressed in thissurvey and compares with those covered by previous works.Note that the Table does not include survey [5] because itdoes not consider aging monitors. Our work addresses eightmonitors types, including monitors not covered by previousworks.
TABLE 1.
Comparison among the reviewed surveys related to aging monitortypes, and this survey coverage. Legend: “A”: addressed, “NA”: not addressed. [4] [6] This SurveyTemperature
A A A
Critical Path: Timing Errors
NA A A
Critical Path: SEU
A A A
Critical Path: Delay
A NA A
Clock Frequency
NA NA A
Workload
NA A A
Circuit State
NA NA A
Voltage
NA NA A
This work adopts the following classification of reconfig-uration techniques: • Dynamic voltage scaling : Dynamic Voltage Scaling
VOLUME 4, 2016 Fig. 1. Monitors types and control actions. Adapted from [7].
Khoshavi et al. [8] review the period 2004-2015 (30 works). Their work analyzes aging monitors and alsoaging models and techniques for aging mitigation. Aging models are used to predict the degradation of the circuitdue to aging. Mitigation techniques are used to deal with aging effects and ensure correct behavior of the circuitunder these effects. Besides, their work proposes a taxonomy to classify the aging mitigation techniques, shownin Figure 2. Worst-case design techniques add safety margins to the circuit characteristics, like frequency andsupply voltage, at design-time. Design time aging-aware balancing focuses on balancing circuit delay to reduceaging effects. Dynamic adaptation techniques are online approaches to tune the design under aging during circuitoperation. Adaptive resource management techniques mitigate the aging effects either through the managementof idle time (Idle-Time Leveraging schemes, also called ITL schemes), power management and task scheduling(controlled resource wearout), or availability of expendable resources (spatial redundancy).Kochte et al. [9] review the period 2007-2017 (14 works). Their work analyses self-test, self-checking, and self-diagnosis online techniques for self-awareness. Online techniques include aging monitors. Figure 3 shows the classi-fication for self-test and self-checking, which contains non-concurrent and concurrent approaches. Non-concurrentapproaches regard self-testing methods, including classic methods, as BIST, and techniques like suspending thecircuit operation to execute the test. Concurrent approaches are self-checking methods executed during the circuitoperation, which includes aging monitors.IV. P
ROPOSED C LASSIFICATION OF A GING M ONITORS AND R ECONFIGURATION T ECHNIQUES
Our proposed classification extends the taxonomy of previous work [7], [8], [9], considering parameters includedin the state-of-the-art and features of the circuits monitored by them. Thus, this work proposes the following setof parameters for aging monitors classification:
AGING ADAPTATION AND MITIGATION TECHNIQUESWORST-CASE DESIGN DESIGN TIME AGING-AWARE BALANCING DYNAMIC ADAPTATION TECHNIQUES ADAPTIVE RESOURCE MANAGEMENTVOLTAGE MARGINGATE SIZING FREQUENCY MARGIN PATHSGATES INSTRUCTION PIPELINE STAGES VOLTAGE AND FREQUENCY SCALE COMPUTATIONAL SPRITING CONTROLLED RESOURCE WEAROUTITL SCHEME SPATIALREDUNDANCY
Fig. 2. Taxonomy of aging mitigation techniques. Adapted from [8].
ONLINE
NON-CONCURRENTPOWER-ON ON-DEMAND PERIODICAL CONCURRENTBIST SELF-TEST USING STORED DETERMINISTIC PATTERNSSOFTWARE-BASED SELF TEST MEMORY BIST CONCURRENT BISTSELF CHECKING DESIGN / CONCURRENT ERROR DETECTIONLOCKSTEP EXECUTIONSYNTHESIZED ASSERTIONS WATCHDOG ALGORITHM-BASED FAULT TOLERANCENON-FUNCTIONAL MONITORS
SELF-TEST AND SELF-CHECK METHODSSELF-TESTING SELF-CHECKING
Fig. 3. Self-test and self-checking circuits classification. Adapted from [9]. • Temperature : a temperature monitor detects aging effects by measuring the variation in the temperature of thecircuit. Temperature variations cause aging effects as NBTI and PBTI; • Critical path : critical path monitors can be used to identify timing errors due to wrong transitions, SEU, ordelay increase on circuit paths. These errors are detectable by comparing a circuit path controlled by the systemclock and the same path controlled by a delayed clock [15]; • Clock frequency : clock frequency monitors measure the frequency variation of a clock circuit under aging.This type of monitor uses a reference frequency to identify a change in the circuit operating frequency; • Workload : workload monitors measure the workload of a circuit to identify the stress level. Similar to the CPUload measure. • Circuit state : circuit state monitors consider the state of the entire system. For example, some techniques usethe BIST circuit output to evaluate aging effects; • Voltage : Voltage monitors analyze the threshold voltage of the circuit. Aging effects as NBTI can change thethreshold voltage of transistors.Table I presents the aging monitors addressed in this survey and compares with those covered by previous works.Note that the Table does not include survey [8] because it does not consider aging monitors. Our work addresseseight monitors types, including monitors not covered by previous works.This work adopts the following classification of reconfiguration techniques: • Dynamic voltage scaling : Dynamic Voltage Scaling (DVS) is a power management technique where the voltageused in a component increases or decreases, according to some criteria [16]. An example of an approach tomanage power dissipation is the adoption of a closed-loop control technique where the voltage is a knob to
TABLE IC
OMPARISON AMONG THE REVIEWED SURVEYS RELATED TO AGING MONITOR TYPES , AND THIS SURVEY COVERAGE . L
EGEND : “A”:
ADDRESSED , “NA”:
NOT ADDRESSED . [7] [9] This SurveyTemperature A A A
Critical Path: Timing Errors
NA A A
Critical Path: SEU
A A A
Critical Path: Delay
A NA A
Clock Frequency
NA NA A
Workload
NA A A
Circuit State
NA NA A
Voltage
NA NA A meet the power goal [17]. • Dynamic frequency scaling : Dynamic frequency scaling (DFS) is a technique similar to DVS, but applied tothe circuit frequency. Similarly, if the circuit needs a boost in performance, the frequency is increased. If thecircuit or application can tolerate lower performance, the frequency may be decreased to allow power savings; • Aging compensation : Aging compensation is a technique that enables the circuit to alleviate aging effects. Forexample, some circuits activate extra devices, in parallel to the main circuit, to increase the driving strengthof an output driver, compensating the degradation due to HCI and BTI effects [18]; • Body-bias adaptive : Body-bias adaptive (BBA) is a technique that allows tuning the transistor threshold voltage[19]. This technique helps to mitigate and compensate for the NBTI impact in the circuit; • Workload reduction : Workload reduction is a series of software approaches to reduce the workload system byintroducing, for instance, no operation (NOP) instructions during the system operation.Table II compares reconfiguration approaches covered by the previous works, and the ones addressed in thissurvey. The Table does not include survey [9] because it does not address reconfiguration techniques. Also, notethat this survey does not address three types of reconfiguration techniques (clock throttling, backward recoveringand computational sprinting) that were covered in the previous surveys because these techniques were not adoptedin the research papers from 2012 to 2019. Our work addresses five reconfiguration approaches, including two typesnot covered by previous works.
TABLE IIC
OMPARISON AMONG THE REVIEWED SURVEYS RELATED TO RECONFIGURATION TECHNIQUES TYPES , AND THIS SURVEY COVERAGE .L EGEND : “A”:
ADDRESSED , “NA”:
NOT ADDRESSED . [7] [8] This SurveyDynamic Voltage Scaling A A A
Dynamic Frequency Scaling
A A A
Aging Compensation
NA A A
Body Bias Adaptive
NA NA A
Workload Reduction
NA NA A
Clock Throttling
A NA NA
Backward Recovering
A NA NA
Computational Sprinting
NA A NA
V. D
ISCUSSION RELATED TO THE S TATE - OF - THE -A RT This Section brings a summary of the presented techniques, remarks, and insights about how to deal with aging.Also, this Section answers the research questions presented in the Introduction Section. The classified state-of-the-artworks are described in Section VI.
About industry, most applications rely on sensors built in SoCs that allow measuring variations in such parametersas the circuit ages. These sensors are commonly distributed across the die and accessible through DfT infrastructureor as peripherals to CPUs. The most common sensor consists of a set of ring oscillators that control asynchronouscounters. These counters provide an overview of how the overall speed of the circuit is being impacted by aging[20].
A. Summary and remarks of the literature review
Table III summarizes the reviewed works. The “Overall Monitoring” column means monitoring the entire circuit,not just the critical paths using, for example, the voltage or the current. The “Monitor Insertion Strategy” columncorresponds to approaches that use some strategy to insert the monitors, such as statistical methods, and not basedonly on critical paths. The “Structure Reuse” column shows designs that use structures available in the circuitfor monitoring aging effects. In these cases, only DfT structures are reused. The “Metastability Concern” columncontains works concerned with metastability issues.Circuits monitoring the overall system may present a low area overhead, once one mechanism can be applied forthe entire design. This approach may be better in terms of area overhead when compared to solutions focusing oninserting monitors in all critical paths. However, designs that use methods to select paths to insert monitor are alsopromising in terms of area overhead reduction. The reuse of DfT structures is a promising strategy to choose paths,once test insertion overhead is already present in the circuit. This allows reducing the impact of aging monitors onarea.A ” no ” in the first column (Overall Monitoring) means that only part of the system is monitored. This means thatspecialized mechanisms may be required for different parts of the system. Particularly, works with a ” no ” in thesecond and/or third columns in Table III (Monitor Insertion Strategy and Structure Reuse) can present a significantoverhead in the system. Nevertheless, these solutions may be useful for detecting aging and could be combinedwith path selection strategies to reduce the system overhead, making their use feasible.Metastability is a concern present in only two works. It is an important issue, once its effects may propagatethrough designs, reducing circuit reliability, making them fail even in the absence of aging effects. Metastability canalso be an issue to systems with more than one clock domain, due to the clock synchronization between domains.Thus, these two works have an advantage compared to other approaches since they use the same circuitry to dealwith both aging and metastability effects.A feature that can be observed is that voltage and frequency scaling are reconfiguration techniques associatedmostly with critical path monitors, once it is possible to control the circuit speed by these two parameters. Similarly,body bias adjustment is associated with voltage monitors, once this reconfiguration technique changes the thresholdvoltage for compensating aging effects. B. Remarks about aging monitors
Figure 4 and Table IV present the answer to the first research question of this survey, “What solutions the literaturepresents for aging monitoring?”. The Figure shows the monitor types covered by this survey. The most commonmonitor type used for aging detection are timing error monitors, which is present in 36.58% of the reviewed papers.The second most common monitor type used for aging detection is temperature monitor, which is present in 27%of the papers.
C. Remarks about reconfiguration techniques
This Section answers the second research question of this survey: “What solutions the literature presents forcircuit reconfiguration?”. Figure 5 and Table V present the reconfiguration techniques covered in this survey.According to the Table, voltage scaling is the most adopted reconfiguration technique, present in 50% of the papersabout reconfiguration techniques. The second most common reconfiguration technique used for aging detection isfrequency scaling, which is present in 28.57% of the papers.
TABLE IIIS
UMMARY OF THE LITERATURE REVIEW . Overall Monitor Insertion Structure MetastabilityMonitoring Strategy Reuse Concern[21] , 2015 yes no no no[22] , 2017 yes no no no[23] , 2017 yes no no no[24] , 2017 yes no no no[25] , 2015 yes no no no[26] , 2016 yes no no no[18] , 2014 yes no no no[27] , 2016 yes no no no[28] , 2019 yes no no no[29] , 2015 no no yes no[30] , 2017 no no no no[31] , 2018 no no no yes[32] , 2016 no no no no[33] , 2015 yes no no no[34] , 2017 no no no no[35] , 2014 no no no no[36] , 2017 no no no no[37] , 2014 no yes no no[38] , 2014 no yes no no[39] , 2018 no no no no[40] , 2017 no yes no no[41] , 2015 no yes no no[42] , 2019 yes no no no[43] , 2019 yes yes no no[44] , 2018 no no no no[45] , 2012 no yes no no[46] , 2014 no yes no no[47] , 2014 no yes no no[48] , 2015 yes no no no[49] , 2016 yes no no no[50] , 2014 no no no no[51] , 2014 no yes no no[52] , 2015 yes no no yes[53] , 2017 yes no no no[54] , 2015 yes no yes no[55] , 2015 yes no yes no[56] , 2019 yes no no no[57] , 2017 yes no yes no[58] , 2015 yes no no no[59] , 2015 yes no no no[60] , 2018 yes no no no
VI. L
ITERATURE R EVIEW
This Section describes the papers related to aging monitors and reconfiguration techniques covering the yearsfrom 2012 to 2019. The subsections are grouped by monitoring approaches, according to the classification proposedin Section IV for aging monitors. When a paper also presents a reconfiguration technique, it is described together,in the same paragraph.
TEMPERATURE CRITICAL PATHTIMING ERRORS SINGLEEVENTUPSET CLOCKFREQUENCY CIRCUITSTATE VOLTAGEWORKLOADDELAYMONITORS
Fig. 4. Monitor types covered by the survey. TABLE IVC
LASSIFICATION OF THE MONITORS ’ WORKS ACCORDING TO THE PROPOSED CLASSIFICATION . Types
WorksTemperature [21] [22] [23] [24] [25] [26][18] [27] [28] [46] [47]Critical path: timing errors [29] [30] [31] [32] [33] [34][35] [36] [37] [38] [39] [40][41] [42] [43]Critical path: single event upset [44]Critical path: delay [45] [48] [49] [50] [51]Clock frequency [52] [53]Circuit state [54] [55] [56] [57]Workload [58]Voltage [59] [60]
VOLTAGESCALING AGINGCOMPENSATION WORKLOAD REDUCITONBODYBIASADJUSTRECONFIGURETECHNIQUESFREQUENCYSCALING
Fig. 5. Reconfiguration techniques covered by the survey. TABLE VW
ORKS CLASSIFICATION REGARDING RECONFIGURATION TECHNIQUES . Techiniques
WorksVoltage scaling [21] [32] [39] [45] [48] [50] [56]Frequency scaling [21] [45] [52] [56]Aging compensation [18]Body bias adjust [59]Workload reduction [40]
A. Temperature Monitors
NBTI, PBTI, and HCI are aging effects accelerated by temperature increase in chips. System workload affectspower dissipation, which has a direct impact on the temperature. Thus, monitoring temperature helps to deal with these effects. Some sensors use ring-oscillators to capture the aging effects caused by temperature increase. Thiskind of sensor provides an indirect measurement of temperature, and can be considered a temperature monitor.Igarashi et al. [21] propose an aging monitor implemented with ring-oscillator (RO) to measures BTI and AChot-carrier-injection (AC-HCI). The monitor consists of a symmetric RO (SRO) and an asymmetric RO (ASRO).ASRO is an RO composed of standard cells of different drives, while SRO is implemented only by standard cellswith the same driving strength. With these two types of RO, it is possible to separate NBTI and PBTI effects foranalyses by observing them under DC stress conditions. Also, the speed degradation caused by AC-HCI can bedetected because unbalanced delay with a long/short transition in ASRO has high sensitivity against AC-HCI underAC stress. A dynamic voltage and frequency scaling (DVFS) technique controlled by software is used to changethe supply voltage and clock activity dynamically and reconfigure the circuit. A test chip, including both SRO andASRO using NAND2 standard cells, was implemented in a 16 nm Fin-FET bulk CMOS technology. Results showthat V th shift due to PBTI measured from frequency degradation is 2mV, which is still 1/10 of NBTI in Fin-FETtechnology, and that is possible to reduce the BTI guard bands in 45% at the nominal frequency operation.Majerus et al. [22] use ROs to measure changes in transistor and resistor parameters as a function of the stresscaused by aging. The result is a data-driven aging model that provides information that can be used to ensuresystem reliability.Sengupta and Sapatnekar [23] present two methods that use sensors implemented with ROs to detect the delayshifts in circuits as a result of BTI and HCI effects. The first method uses a pre-silicon analysis of the circuit tocompute calibration factors that can translate the delay shifts in the ROs with a delay estimate of 1% of the realvalues. The second method uses an analysis where sensor measurements are combined with infrequent online delaymeasurements to reduce the circuit guard bands and allows 8% lower delay guard banding overheads compared tothe conventional methods.Kim et al. [24] propose a new test structure of RO that helps to measure the stress duty cycle (SDC) of the HCI.SDC is the ratio between the stress caused by the aging effect and the circuit cycle time [61]. The structure iscomposed of a NAND gate that has the function of enabling the oscillator mode and inverters. VDD and GND biasof the HCI stress inverter are set up in a complementary way during the stress, making the device not sufferingfrom BTI aging. Also, a buffer is designed as a compensator for the signal falling by as much as V th . Resultsdemonstrated that HCI SDC increases with frequency, but the maximum duty cycle was much less than 2%.Shakya et al. [25] propose an NBTI sensor that uses two ROs, one without circuit influence used as a referenceand other to evaluate the degradation circuit under stress, and compare the output of both. This approach gives themanufacturer the exact control over the yield and accuracy of the sensors, which not occurs with ad hoc approachesthat determine parameters such as the decision threshold.Miyake et al. [26] propose an aging-tolerant monitor that analyzes frequencies of more than one RO. Thus, it ispossible to derive the values for temperature and voltage from the frequencies using multiple regression analysis.Besides, three techniques to select the RO types are proposed to improve the accuracy of the measurement. Themethod was validated with simulations in 180 nm, 90 nm, and 45 nm CMOS technologies. In the 180 nm technology,temperature accuracy is about 0.99 ◦ C, and voltage accuracy is about 4.17 mV. Also, the authors fabricated testchips with 180 nm CMOS technology to confirm its feasibility.Kumar [18] presents an aging compensation technique for a CMOS transistor output driver. It contains an agingcompensation cell which monitors the degradation in the ON current ( I ON ) of output driver due to the HCI andBTI effect. Based on this degradation, the aging compensation cell generates compensation codes for PMOS andNMOS transistors drivers. These aging compensation codes turn on devices in parallel to the main driver, increasingthe drive strength of output, which compensates the degradation in NMOS and PMOS driver due to HCI and BTIeffects. The design was implemented in 40 nm CMOS process by using 1.8V thick-oxide devices. Results showthat by using the proposed aging compensation technique, the impact of aging on output driver reduces by 70%after ten years of operation.Ali et al. [27] use IJTAG to manage temperature health monitors on the chip. The temperature health monitorsare based on a Wheatstone bridge, which is composed of four resistors, one operational amplifier, one filter, and oneanalog to digital converter. Results show that the proposed solution can be used to manage and control instrumentsto ensure the reliable operation of the chip over its lifetime. According to the authors, the proposed method canreduce the overall time spent on the test, once there is no off-chip interface, and the system clock can be usedinstead of the test clock. Rathore et al. [28] propose to use temperature and NBTI sensors to implement a task mapping strategy tomanycore systems, called LifeGuard. LifeGuard considers performance and aging as parameters to perform taskmapping, and is based on reinforcement learning. At each tile of the network-on-chip (NoC), an NBTI and athermal sensor are added and used to perform the task mapping. As a benefit, LifeGuard prevents the rapid agingof cores that map a more significant number of tasks. Also, it improves the aggregate safe operating frequency ofthe system. Experimental results using a 256-core system showed that LifeGuard improved the health of the coresfor 57% when compared to the HiMap strategy [62], and 74% when compared to the Hayat [63]. Also, LifeGuardshows a better system performance.
B. Critical Path Monitors
Contemporary literature presents monitors that capture timing errors on the critical paths of circuits (Definition1). This technique contains extra components that capture the memory register output of the critical paths and itsprocessed data. A comparison between these data is executed to identify if a timing error occurred.Savanur et al. [29] present a BIST (Definition 7) approach to detect aging effects on the circuit during test mode.The BIST circuitry uses two identical buffer chains and a logic block to compare the output of these chains. Ifthere is a difference between the outputs of the chains, an error caused by aging is detected. The approach needsextra components, which are a D flip-flop, a NAND gate, an AND gate, and two buffers. HSPICE simulations on45 nm and 65 nm were performed to extract results. This paper focuses only on the NBTI aging factor, and resultsshow that the solution can detect minimal stress levels in the presence of process variations and that the agingdetection depends on the time that a path of the circuit keeps at logic level zero.Sai et al. [30] present a Parity Check Circuit (PPC) for monitoring delay-faults and compare it with the Canary flip-flop approach [64]. Unlike the Canary flip-flop approach, PPC can monitor more than one logic path simultaneously,which allows reducing the number of sensors. PPC is implemented using a multiple-input XOR gate, a delay element(DE), a matched delay element (MD), a flip-flop, a shadow flip-flop, and a 2-input XOR gate. The multiple-inputXOR gate is responsible for computing the data parity, and the MD is responsible for adding a delay to the clocksignal to compensate delay produced by the multiple-input XOR gate. The PPC was validated in a 32 bit MIPSprocessor using a 65 nm technology. Results indicate that the use of the circuit reduces area overhead by 66% andpower by 33% when compared to the Canary flip-flop approach.Sai et al. [31] propose a metastability-free aging sensor called Differential Multiple Error Detection Sensor(DMEDS). The sensor monitors multiple paths concurrently. It is composed of a Multiple Detection Unit (MDU)and a stability checker, which allows monitoring two or more critical paths simultaneously. Any transition in thedata active the MDU output signal that is captured by the stability checker, signaling a delay fault. The stabilitychecker checks the stability of the delayed signal while the clock is high. DMEDS was designed at transistor levelusing a 32 nm technology and applied to a 32-bit MIPS processor to monitor ten paths concurrently. Results showthat using DMEDS for monitoring ten paths can save 197.1% and 97.1% in area overhead when compared to Razor[15] and Canary [64], respectively.Copetti et al. [32] propose a hardware-based technique able to increase ICs lifetime. The technique is based ona sensor able to monitor IC aging and to adjust its power supply voltage to minimize NBTI effects, increasing thecircuit lifetime. The approach is composed of: (i) an aging sensor, which contains a delay element and the stabilitychecker; (ii) an actuator, which contains a counter and a decoder block; and (iii) a flip-flop inserted at the criticalpath output. The flip-flop output of the critical path passes through the delay element and the stability checker whilethe clock signal is high, analyzing data transitions. If a transition while the clock is high occurs, it means that thedelay of the circuit increased, changing the output of the stability checker and indicating a timing violation. Also,the actuator receives the signal from the stability checker and increases its counter, allowing the decoder to adjustthe power supply. Experimental results obtained by simulations demonstrate that the technique increases the circuitlifetime by 150%.Sadeghi-Kohan et al. [33] propose a self-adjusting age monitoring method to pipeline circuits, which allowsdetecting progressive changes in the timing of a circuit. The output of the critical paths are captured using anage monitoring clock (that occurs before the system clock), and this captured data is compared with the sameoutput but captured at the rising edge of the system clock. The circuit used to adjust the age monitoring clock hasan age indicator counter that counts RO pulses to adjust the clock phase and is initialized with the core process characteristic. As the core ages, the age indicator counter is incremented, causing a more extended clock phaseshift, and shorter slack time. The monitors are designed targeting low hardware overhead and accuracy in reportedtiming changes.In another work, Sadeghi-Kohan et al. [34] use a similar strategy to monitor paths of a circuit and to detect itscontinuous age growth. This approach can provide the aging rate and the aging state of the circuit. The proposedstrategy uses a clock generator to feed the register responsible for capturing the data before the system clock.Results show an area overhead of 2.13%, a power overhead of 0.69%, and a low-performance overhead. Yi et al.[35] present a scan-based on-line monitoring that monitors aging during system operation and gives an alarm if thesystem detects aging effects. This work inserts an extra scan chain that captures early the functional data (at theopposite edge of the system clock) within a given guard-band interval during system operation. After that, the extrascan chain output is compared to the original scan chain output, which allows detecting violations. The scan-chainscheme contains two scan-chains, one with conventional scan cells (SC scan-chain) and the other one with the earlycapture scan cells (ECSC scan-chain). The SC flip-flops capture the data at the clock rising edge, while the ECSCflip-flops capture the data at the clock falling edge. The modified scan chain uses an XOR gate to compare thecaptured data.Jung [36] presents an aging level estimating flip-flop that exploits the frequency guard band of a device toestimate the aging level with a small power overhead, called performance estimation flip-flop (PEFF). The PEFFhas five elements: i) a scan flip-flop; ii) a shadow latch; iii) a sampling time indicator; iv) a logic block to controlsthe input of the performance result cell (PERC); v) the PERC. The shadow-latch is used to sample the data earlierthan the functional flip-flop. Results show a reduction in monitoring time, and the power consumption is reducedby 50% when compared to the Yi et al. [35].Vazquez-Hernandez [37] proposes a solution for error prediction using an aging sensor based on the Error-Detection Sequential (EDS) circuit [65]. The EDS has a decoder module to monitors the critical paths. When oneof the paths is activated, the decoder active the EDS to allow detect errors. The methodology for path selectionuses statistical static timing analysis. Results show that the EDS can reduce power overhead form 102% to 6%and area overhead from 69% to 22% when compared to [5] and [35], considering the circuit characteristics as thenumber of gates and buffers.Chandra [38] proposes the SlackProbe monitor. This approach inserts timing monitors at endpoints and interme-diate nodes of the circuit paths. If a monitor is inserted at an intermediate node, an AND gate is used as delaymatching, and a transition detector is connected to the intermediate node with a minimum size inverter. If a signaltransition at the intermediate node occurs, it arrives at the transition detector through the delay chain, and the signalis compared with the incoming clock edge. If the transition is close to its required arrival time, a correspondingsignal transition arrives at the transition detector input after the clock edge. This transition triggers the transitiondetector and flags a signal indicating a delay failure. The monitor inserted at the intermediate node is capable ofmonitoring the delay of all critical paths passing through it, and its output can be used for mitigating failures dueto aging (based on hardware or software). The results show that SlackProbe can achieve up to 16x reduction in thetotal number of monitors.Masuda and Hashimoto [39] propose an error prediction adaptive voltage scaling (EP-AVS) and a mean timeto failure aware (MTTF-aware) design methodology for EP-AVS circuits. The EP-AVS has a main circuit plus atiming error predictive flip-flop (TEP-FF) and a voltage control unit. The TEP-FF has a flip-flop, delay buffers, anda comparator implemented with an XOR gate. Also, TEP-FF works with the main flip-flop. When the timing marginis gradually decreasing, a timing error occurs at the TEP-FF before the main flip-flop captures a wrong value dueto the delay buffer. This wrong value produces an error prediction signal, which allows the voltage control logicto provide a higher supply voltage and reduce the circuit delay. Evaluation results show that the proposed EP-AVSdesign methodology achieves a 20.8% voltage reduction while satisfying the target MTTF.Vijayan et al. [40] propose an aging monitor based on hardware and software. The system is composed ofrepresentative flip-flops (RFF) that are selected in an offline phase and connected to the monitoring hardware. Theaging effect consists of two phases: i) stress phase, where the transistor is under the aging effect; ii) recoveryphase, where the transistor is recovering from the stress phase. A switching event in the RFF corresponds to therecovery phase of the corresponding flip-flop group, which is captured to report the recovery event to the software.The representative flip-flops are observed by a switching-event detector to perform the capture operation, whichis composed of an XOR gate and a shadow flip-flop that generates a pulse at its output when a logic transition occurs in the corresponding flip-flop. The output of the switching-event detector is encoded using a priority encoder.In a determined clock cycle, the output of the priority encoder indicates the index of the flip-flop that switchesits state in that particular clock cycle. If two representative flip-flops change their states at the same time, thepriority encoder ensures a valid output. The critical-flag register (CFF) keeps the criticality word to represent therecovery/aging state of the corresponding representative flip-flop. This paper uses a software subroutine to mitigateaging by inserting NOPs instructions, which allows a relaxation on BTI stress, reducing the workload. Results showthat area and power overheads imposed by the monitoring hardware are less than 0.25% for a Leon3 processor andFabscalar processor.Saliva et al. [41] propose monitors based on delay elements called pre-error flip-flops. The approaches arecomposed of a shadow flip-flop that stores delayed data, and is works in parallel to the regular flip-flop. Theapproach compares the two flip-flop outputs, and a pre-error signal is generated to predict the occurrence of timingerrors. Each monitor uses different delay approaches. The first approach is the buffer delay, where buffers producethe delay. The second is the passive delay, where a resistor generates the delay. The last is the master delay, wheremaster-slave latches replace the regular flip-flop, and the slave latch outputs feed the shadow flip-flop to generatethe delay. Results show that the detection window of the in-situ monitors with passive delay is less deviant than thebuffer and master delay ones with V dd decrease. However, using a passive element in a digital circuit is not common.The in-situ monitor with buffer delay is a better choice because it uses standard cells in its implementation.Di Natale et al. [42] propose a hidden-delay-fault sensor that can be used to detect small delay faults. The sensorallows the circuit to operate at the nominal frequency, and it is inserted in a critical path. The monitor workssampling a signal in both clock edges. After that, the monitor compares the two samples using an XOR gate andstores the result on the next falling edge of the clock suing a shadow flip-flop. Result extraction is performed usinga classic scan chain. The authors propose that the sensor can be used during the lifetime of the circuit to identifytiming violations in short paths caused by aging. Also, the authors mention that it is possible to use the sensorcombined with reconfiguration techniques such as DVFS. The paper does not present results.Wang et al. [43] uses a timing margin detector (TMD) to monitor aging and capture delay behavior. Also, theoutput detector is used in a machine learning engine based on a support vector machine (SVM) to predict aging.The TMD is used to capture late transitions. It is composed of two D flip-flops, and by an OR gate at the flip-flops output. Results show that it is possible to obtain a 97.40% of accuracy in aging prediction, with 4.14% areaoverhead on average.Rohbani and Miremadi [44] propose an aging sensor combined with the flip-flops of the design that monitors thecritical path output before the rising edge of the clock signal. This signal follows the system clock by an adjusteddelay of about 10% to 20% of the clock period. When the clock is at logic level one, the sensor is activated. Anychange in the input signal during the period where the sensor clock is at logic level one and the system clock isat level logic level zero represents a delay extension of the critical path due to aging effects. Results show that theprecision of the proposed sensor is about 2.7 higher, with almost 33% less area overhead compared with state-of-the-art aging sensors. Furthermore, the presented sensor can detect and correct 50% of the Single Event Upsets(SEUs), which lead to a bit-flip in the flip-flops. Besides, the SEU detection circuitry can reduce Bias TemperatureInstability (BTI) by balancing the duty cycle of the flip-flop with negligible extra overhead.Pachito et al. [45] propose an aging-aware power supply or frequency reconfiguration approach that uses globaland local sensors. Global sensors perform periodic or on-demand delay monitoring, while local sensors predicterrors locally. Both allow adjusting frequency or power supply voltage. Results show that performance and powercan be improved by, respectively, increasing the frequency and reducing the voltage while still preventing errors.In other work, Semio et al. [46], [47] propose improvements in the global and local sensors cited previously. Theglobal sensor was improved to detect Negative-bias temperature instability (NBTI) and Positive-bias temperatureinstability (PBTI), while the local sensor was improved to tolerate delay-faults.Cho et al. [48] examine the effectiveness of the aging-aware Adaptive Voltage Scaling (AVS) for logic circuitblocks using a Tunable Replica Circuit (TRC) aging monitors. The TRC is calibrated off-line, based on the criticalpaths and on-line monitoring of the operational conditions of the circuit, as temperature variations. The PowerManagement Unit (PMU) communicates with the TRC periodically. The PMU tunes the Voltage Regulator Module(VRM) when the TRC detects an aging delay degradation until the TRC detects the correct behavior based on theclock. Simulation results in a 22 nm High-K/Metal-Gate Tri-Gate CMOS process show a 7% power reduction withthe removal of the guard-bands of a conventional fixed V cc . Ding et al. [49] propose a delay amplified digital (DAD) aging sensor circuit composed of a delay sensor anda signal amplification circuit. It uses a reference delay circuit designed according to the monitored combinationallogic circuit. The delay sensor is used to detect aging effects, while a timing multiplier circuit eliminates the effectson the environment, improving the aging sensor data accuracy. A digital sample module uses nine T flip-flops tocount the number of falling-edge during the amplified enable pulse. Using the parameters of TSMC 65 nm CMOStechnology, the DAD sensor circuit is designed and simulated using SPECTRE.Li and Seok [50] propose a technique to pipeline circuits that enables accurate of aging monitoring evenunder environmental variations. The technique scales the supply voltage for a temperature-insensitive delay andreconfigures the target paths into ring oscillators. The oscillation periods are measured and compared to pre-agingmeasurements to estimate the delay degradation caused by aging. Also, the technique presents a new registerimplementation, that has an area overhead of 12 transistors when compared to a standard flip-flop, and a relativelylow delay overhead, once it adds a small amount of load between the path from input to output. The techniqueadds a feedback network between the input and output registers of target paths, which can present a small portionof the total oscillation period, making little impact on monitoring accuracy. The area overhead of feedback networkcan be minimized by sharing feedback paths among multiple target paths, as like the counter. The counter is usedto measure the periods of the ring oscillator operation. Results show that the technique achieves highly-accuratemonitoring with an error of 15.5% across the temperature variations in self-test phases from 0 ◦ C to 80 ◦ C, exhibitingmore than 30 times improvement in accuracy as compared to the conventional technique operating at the nominalsupply voltage.Jang et al. [51] propose a aging sensor that detects failures caused by BTI and HCI. This aging sensor is basedon timing warning windows to detect a guardband violation of sequential circuits and generates a warning rightbefore circuit failures occur. It monitors the moment when the critical path delays of the logic exceed a standardvalue, which guarantees a correct circuit operation. The aging sensor is composed by: i) a guardband generator; ii)a path delay monitor; iii) a hold circuit; iv) a signal that controls the aging sensor. The circuit was implemented in110 nm, and results show that the aging sensor achieves a good aging failure prediction with low overhead.Table VI summarizes the reviewed path delay monitors. Most of the monitors use delay elements and comparisonmechanism to detect timing errors. Also, most of the approaches monitor just the critical paths without monitoringother system elements.
C. Clock Frequency Monitors
Aging can affect clock frequency and decreases system performance. Thus, clock frequency monitoring is a wayto detect aging in a design.Wang et al. [52] present a sensor for reliability analysis of digital circuits using standard-cells called Radic. TheAuthors also propose a low-cost built-in aging adaption system based on the Radic sensor to perform in-field agingadaption. Radic allows frequency, aging, and metastability measurements. Also, the sensor is designed to obtainthe frequency difference between the waveform under test and a reference frequency by measuring how muchclock cycles the wave under test is faster or slower than the reference frequency. A stable external source suchas automatic test equipment, or a waveform generator, or an internal source such as a phase-locked loop (PLL)can generate the reference frequency. An m-bit timer stores the length of the measurement window by countingthe number of clock cycles of the reference frequency. The Radic-based aging monitor system is inserted into aFreescale IP and an ITC’99 b19 benchmark. Results show that the system reduces the fixed aging guardband by80%. A comparison between the original design and the design with the proposed adaption system shows an areareduction of about 1.02% to 3.16% in most cases. Power is also reduced, as the design can be synthesized usingsmaller drive strength.Kfloglu et al. [53] propose an aging sensor based on RO that uses two identical aging paths. Both paths can beeither equally sensitive to BTI or modulated to be more sensitive to aging effects. Using DC biased with oppositepolarity inputs, both paths have the PBTI and NBTI effects stressed alternatively at every other stage. Unlike aconventional RO based aging sensor, a control loop logic links all stressed devices into one measuring RO loopwhich its output is the frequency degraded due to the aging. Also, the control loop logic links all non-stresseddevices are linked into a second RO loop, wich the output is the reference frequency. The frequency delta betweenaging frequency and reference frequency is used to monitors aging. TABLE VIC
OMPARISON AMONG CRITICAL - PATH MONITORS PAPERS . L
EGEND : “A”:
ADDRESSED , “NA”:
NOT ADDRESSED . System Extra Delay Comparisonmonitoring clock element mechanism[29] , 2015 NA NA A A [30] , 2017 NA NA A A [31] , 2018 NA NA A A [32] , 2016 NA NA A A [33] , 2015 NA A NA A [34] , 2017 NA A NA A [35] , 2014 NA NA NA A [36] , 2017 NA A NA A [37] , 2014 NA NA NA A [38] , 2014 NA NA A A [39] , 2018 NA NA A A [40] , 2017 NA NA NA A [41] , 2015 NA NA A A [42] , 2019 NA NA NA A [43] , 2019 NA NA NA A [44] , 2018 NA NA A NA [45] , 2012 A NA A A [48] , 2015 NA NA NA NA [49] , 2016 NA NA NA A [50] , 2014 NA NA NA NA [51] , 2014 NA NA A A
D. Circuit State and Workload Monitors
It is possible to detect aging by monitoring the whole system instead of just critical paths. The circuit state andits workload are metrics that can be monitored and provide insightful information. For example, they can indicatestress levels that will increase the aging effects impact.Koneru et al. [54] reuse the design for testability (DfT – Definition 6) infrastructure to perform a fine-grainworkload-induced stress monitoring for accurate aging prediction. A multiple-input signature register (MISR) isused to capture the workload effect on the circuit. An aging prediction software, based on support vector machine(SVM) learning technique, performs aging mitigation. The DfT controller, implemented as a finite-state machine(FSM), periodically switches the circuit into scan mode to capture the circuit state. After capturing the state, thecontents of the scan chains are then shifted out to the MISR. The scan-chains are modified to keep its value duringthe aging monitoring phase, which overwrites the state of the flip-flops and not allow the circuit to return to normaloperation until completing the shift to MISR. The Authors conducted experiments on two open-source processorbenchmarks, namely OpenRISC 1200 and Leon3, and on four ISCAS’89 benchmarks, to evaluate the accuracyof the proposed technique. Simulation results show that the proposed approach can accurately predict workload-induced aging trends. In a similar work, Firouzi et al. [55] reuse the BIST structure to predict the fine-grainedcircuit-delay degradation with minimal area and performance overhead and high accuracy.Khan and Kundu [56] propose a system-level reliability management scheme (SRM) that dynamically adjuststhe operating frequency and supply voltage according to the system aging. The proposal allows continuous run-time adjustments based on parameters such as actual room temperature and power supply tolerance. The SRMcommunicates with the voltage and frequency control registers to enable frequency and voltage reconfiguration. Itis implemented in software and assumes a Virtual Machine Monitor (VMM) running underneath the OS softwarestack, which is primarily used to enter and exit the SRM. The SRM software enables carefully crafted functionalstress tests or built-in self-test control to identify degradation at a component granularity and provides adjustmentsfor sustained performance levels at the target reliability. The software allows the system to adapt to the aging effectsand invokes aging device management at determined periods. The results show that the device can operate near peak frequency throughout product life. Also, the approach ensures protection against failure due to insufficientlifetime guardband and no system downtime or change.Sadi et al. [57] presents a framework for designing lifetime-reliable system-on-chip (SoC) with reconfigurationcapability to deal with aging effects. The proposed flow uses a BIST (Definition 7), and a machine learning linearregression predictor software to activate aging countermeasures. The aging status of the chip is monitored at regularintervals by the BIST hardware. Based on the observations, proactive adaptation methods are taken to counteract thereliability degradation effect. The framework allows testing patterns from SoC’s existing BIST hardware, collect theresponse, and tune the linear regression software. A gate-overlap and path-delay-aware algorithm selects a minimumset of patterns, which activate the target paths used as features of the linear regression predictor. The seeds of theselected patterns are stored in on-chip memory and applied at the BIST hardware at multiple test clock frequencieswhen required. The corresponding responses of these patterns are collected in a separate response storage flip-flop chain. The software-implemented machine learning classifier is trained with the collected multiple-frequencyresponses, and the trained predictor accurately predicts the state of aging degradation at runtime. The paths to bemonitored by the BIST hardware are selected at the design time based on timing analysis. The adaptive methodsused in this approach are frequency scaling, voltage scaling, and adaptive body biasing. Simulation results showthat the proposed technique allows accurate and fine-grained in-field aging prediction, with a precision that canreach 94%.Baranowski et al. [58] present a method for aging rate prediction, which is based on workload monitoringand linear regression machine learning technique. The monitoring technique enables the on-line prediction of thedegradation rate caused by the currently running application. The degradation rate monitoring system is composedof a workload monitor and a temperature sensor. The linear regression machine learning technique is used to findthe representative critical gates that are monitored. Results show that this method delivers sufficient accuracy at anarea overhead of 4.2%, which decreases with the size of the monitored circuit. E. Voltage Monitors
Circuit voltage can also be use to monitor aging effects. Similar to what happens in clock frequency variations,as the circuit ages, negative effects will be observed, such as timing errors and path delay extension.Narang and Srivastava [59] propose an approach that uses an inverter chain and counter-based technique todetect the variation in the threshold voltage. A voltage sensing methodology is used to monitor the circuit’s voltagevariation. This variation can be fed to an Adaptive Body Bias (ABB) circuit to mitigate the effects of NBTI. Theapproach uses a counter to determine the total path delay. The path delay feeds an inverter connected to an amplifier.The amplifier output pass trough a voltage to current converter, which feeds a logarithmic amplifier. The output ofthis logarithmic amplifier feds an exponential function generator that passes through a subtractor circuit that is usedto detect a change in the threshold voltage due to the NBTI effect. The circuit was validated in a set of circuitssuch as 32-bit OR gate, 64-input OR gate, and 32-bit comparator in 32 nm technology. The simulation results showthat this methodology is efficient as it reduces the delay to a large extent with minimal increase in power.Xiaojin et al. [60] propose a digital on-chip detector that uses the circuit output voltage phase to detect aging. Theapproach consists of duplicating the circuit, generating two circuits: a reference circuit and an aging stressed circuit.The output of both is compared using an XNOR gate. If a pulse occurs in the XNOR output, aging is detected.Also, the XNOR output pass trough time to digital converter to facilitate the circuit state analyses and verification.The authors claim that the aging detecting circuit can be applied in adaptive systems to mitigate the aging, but donot present a solution in this work. The validation was made by a chip implementation and by simulation. Thechip demonstrates results close to the simulated regarding aging time.VII. C
ONCLUSION
This Section concludes the aging monitors and reconfiguration techniques survey, providing insights for futureresearch and development. Table VII presents the implementation methods.Most of the literature contributions are in the digital area, specifically using hardware solutions for monitoringaging in circuits. Few works use software approaches for aging monitoring. Most software applications act onreconfiguring the circuit after aging detection. We observed works using learning methods (software) for takingproactive actions, detecting events related to aging before they occur. These learning-based methods can point out TABLE VIIC
LASSIFICATION ACCORDING TO THE IMPLEMENTATION METHOD . Classification Works
Digital, Hardware, Synchronous [23] [24] [25] [26] [18] [28] [29][30] [31] [32] [33] [34] [35] [36][37] [38] [39] [42] [43] [44] [45][46] [47] [48] [49] [50] [51] [52][53] [55] [60]Digital, Hardware & Software, Synchronous [21] [40] [54] [56] [57] [58]Analog & Digital, Hardware, Synchronous [22] [27] [41] [59] a promising way to detect the effects of aging, as long as they are associated with a rich set of hardware monitors,such as temperature monitors. Also, few contributions combine analog and digital techniques to perform agingmonitoring.As mentioned, the most common monitor used for aging detection is the timing error monitor. However, thistechnique is a function of the paths chosen to be monitored during design time. If this choice is executed incorrectlyand the set of critical paths does not represent the critical paths, the aging counter-effects solutions are inefficient.With the CMOS scaling, the number of critical paths increases, which increases the number of components tomonitor the aging effects. Thus, it is likely that the use of solutions focused on timing errors and path monitoringwill decrease in the future or be limited to older technologies nodes.We believe that solutions based on system-wide monitoring parameters such as temperature, voltage, and fre-quency will be more prevalent once they do not depend on a specific parameter.Summarizing, current techniques heavily rely on timing error monitors for detecting aging and use voltage scalingto compensate the effects in integrated circuits. We believe that new solutions are required due to the fact that astechnology nodes advance, it becomes harder to identify critical paths of a circuit. This limitation not only makesthe task of defining where to place timing error monitors more challenging, but can also require an increase inthe number of monitors, inducing larger area and power overheads. Furthermore, with the availability of differentsensors, such as frequency and temperature, in industrial SoCs, we believe there is a gap to be filled in agingdetection algorithms. Especially with emerging artificial intelligence capabilities, algorithms can analyze the dataof the available sensors and configure the SoC to counter aging effects.R
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Author Fernando Gehm Moraes is supported by FAPERGS (17/2551-0001196-1) and CNPq (302531/2016-5),Brazilian funding agencies. Leonardo Rezende Juracy was financed in part by the Coordenao de Aperfeioamentode Pessoal de Nivel Superior - Brasil (CAPES) - Finance Code 001.B
IOGRAPHY
Leonardo Rezende Juracy received a bachelor degree from the Pontifical Catholic University of Rio Grande doSul (PUCRS), Brazil, in Computer Engineering in 2015, an M.Sc. degree from the PUCRS, Brazil, in ComputerScience in 2018, and is currently an Ph.D. student at PUCRS. His research interests include design for testability, fault-tolerant designs, asynchronous designs, resilient designs, networks-on-chip and multi-processor systems-on-chip. Matheus Trevisan Moreira received a B.S.E degree in Computer Engineering from Pontifcia Universidade Catlicado Rio Grande do Sul (PUCRS) in 2011. He also received a M.Sc. degree in Computer Science from the graduateprogram in Computer Science (PPGCC) at PUCRS in 2012. He has over 50 published articles, in conferencesand journals. Also, his Thesis received an award from the Brazilian Society of Microelectronics (SBMICRO) andCEITEC S.A. as the best Ph.D. Thesis in Design, EDA and Test of Integrated Circuits in 2016. He is currentlythe Director of Technology at Chronos Tech, in San Diego, CA, USA. He has experience in different fields ofmicroelectronics with emphasis on non-synchronous circuits design.
Alexandre de Morais Amory received bachelor and master degrees in computer science from the PUCRSUniversity, in 2001 and 2003, respectively. In 2007 he received the Ph.D. in computer science from UFRGSUniversity, Porto Alegre, Brazil. His thesis received an Honorable Mention in the CAPES Thesis Award, in 2008.His professional experience include an internship at Philips Research Laboratories, The Netherlands, in 2005; asa lead verification engineer at CEITEC design house from 2007 to 2009; and as a postdoctoral fellow at PUCRS,from 2009 to 2012. Alexandre is currently a professor at PUCRS University. His research interest include design,test, fault-tolerance, and verification of digital systems, particularly MPSoCs and NoCs.