A System for Generating Non-Uniform Random Variates using Graphene Field-Effect Transistors
Nathaniel Joseph Tye, James Timothy Meech, Bilgesu Arif Bilgin, Phillip Stanley-Marbell
AA System for Generating Non-Uniform RandomVariates using Graphene Field-Effect Transistors
Nathaniel J. Tye
Department of Engineering,Cambridge Graphene CentreUniversity of Cambridge [email protected]
James T. Meech
Department of EngineeringUniversity of Cambridge [email protected]
Bilgesu A. Bilgin
Department of EngineeringUniversity of Cambridge [email protected]
Phillip Stanley-Marbell
Department of EngineeringUniversity of Cambridge [email protected]
Abstract —We introduce a new method for hardware non-uniform random number generation based on the transfercharacteristics of graphene field-effect transistors (GFETs) whichrequires as few as two transistors and a resistor (or tran-simpedance amplifier). The method could be integrated into acustom computing system to provide samples from arbitraryunivariate distributions. We also demonstrate the use of waveletdecomposition of the target distribution to determine GFET biasvoltages in a multi-GFET array.We implement the method by fabricating multiple GFETsand experimentally validating that their transfer characteristicsexhibit the nonlinearity on which our method depends. We use thecharacterization data in simulations of a proposed architecturefor generating samples from dynamically-selectable non-uniformprobability distributions.Using a combination of experimental measurements ofGFETs under a range of biasing conditions and simulation of theGFET-based non-uniform random variate generator architecture,we demonstrate a speedup of Monte Carlo integration by afactor of up to 2 × . This speedup assumes the analog-to-digitalconverters reading the outputs from the circuit can producesamples in the same amount of time that it takes to performmemory accesses. Index Terms —Monte Carlo Accelerator, Non-Uniform RandomVariates, Graphene, Graphene Transistors
I. I
NTRODUCTION
Hardware uniform random number generators exist inboth research and commercial computer architectures, withgeneration rates of up to 6.4 Gb/s [12]. Uniform randomnumbers are widely used in applications such as cryptography,where the objective is to generate bit vectors (e.g., 256-bitvectors) that are uniformly distributed over some range andare therefore difficult to guess. In contrast, this article focuseson non-uniform random number generators . A. Applications of non-uniform random variates
Many important applications in science and engineeringdepend not on uniform random samples, but instead require non-uniform random variates (random samples chosen froma non-uniform probability distribution), from a wide range ofdistributions. Examples of these applications of non-uniformrandom variates range from Monte Carlo simulations [27],to quantitative finance [34] to particle filter localization fordriverless cars [36]. Non-uniform random variates are alsoimportant in Bayesian machine learning applications [17], which involve the computation of a marginal probability whichgoes into the denominator of the expression of Bayesâ ˘A ´Zsrule. Computing these marginal probabilities in turn requiresevaluating an integral of a probability distribution. Because thedistributions in question are typically high-dimensional andhave no known analytic equational form, their integration oftenrequires the use of Monte Carlo integration methods whereone samples repeatedly from the corresponding distribution.
B. Challenges
Because generating samples from distributions whose inversecumulative distribution function (CDF) does not have a closedform requires the use of time-consuming rejection sampling [6],generating random samples from non-uniform distributions istypically an order of magnitude slower and less energy-efficientthan generating uniformly distributed random samples [35].One promising direction for efficiently generating non-uniformrandom variates is to sample from a physical process whoseevolution in time [42] or noise characteristics [25] follow someknown and (ideally) controllable probability distribution.
C. Contributions
This article presents the first demonstration of generat-ing non-uniform random variates by exploiting propertiesof GFETs previously considered to be undesirable: theirambipolar transfer characteristics and their lack of a band-gap. We provide a tutorial overview of the properties ofGFETs (Section II) and introduce a circuit topology forusing a chain of GFETs together with a uniform randomvariate generator to generate dynamically-controllable non-uniform distributions (Section III). We present the methodologywe used for fabricating an array of GFETs and empiricallycharacterizing their transfer characteristics (Section IV) and weuse those empirically-measured GFET transfer characteristicsto demonstrate the proposed method in a simulated combinedcircuit topology (Section V). We then use the generated non-uniform random variates in an end-to-end system example,where we evaluate their benefit to speeding up Monte Carlointegration, as well as their benefit to reducing the error inthe Monte Carlo integration process (Section VI). We proposethis system as a component/unit in a more general computingsystem. a r X i v : . [ c s . ET ] A p r omentum E n e r g y Conduction BandValence Band E F Fermi Energy Level,
Fig. 1. Energy band structure of graphene, showing the Dirac point,where the conduction and valence bands touch. E F is the Fermi level. Inundoped/unbiased graphene, it is located at the Dirac point. There is no bandgap: GFETs have low on- to off-current ratios making them a poor choice fortraditional digital logic applications. II. P
ROPERTIES OF G RAPHENE F IELD -E FFECT T RANSISTORS
GFETs have a channel made of single- or multi-layergraphene, rather than a semiconducting material such as siliconor germanium [32]. Unlike traditional semiconducting materials,graphene is a semi-metal: it lacks a band gap and its conductionand valence bands donâ ˘A ´Zt overlap. Instead, the conductionand valence bands meet at a single point, known as the
Diracpoint (Figure 1).Electrons at the Dirac point are effectively massless andso have unusually high electron mobilities. As a result, thephonon-limited carrier mobility (the highest possible mobilitylimited by interactions between carriers and vibrations of thechannel’s crystal lattice) of graphene on SiO is predicted tobe as high as 200,000 cm V − s − [4]. Although high electronmobilities result in more efficent flow of charge, the lack ofa band gap means GFETs have low on- to off-current ratiosand can never completely turn off, making them unsuitable fordigital logic applications [15].The poor on- to off-current ratios of GFETs in digital logicapplications does not preclude their use in other areas ofcomputing. Because it is possible to tune the Fermi levelin graphene (which typically lies at the Dirac point) by biasingthe channel, it is possible to control device characteristics, e.g.,using multi-gate structures, in a manner not equally possiblein typical metal-oxide-semiconductor field-effect transistors(MOSFETs). GFETs also have unique transfer characteristics:as the gate voltage is swept, the drain current exhibits a v-shaped characteristic curve, with the conductance increasinguntil it reaches a minimum value before increasing again.III. A GFET N ON -U NIFORM R ANDOM V ARIATE G ENERATOR
If the signal at the gate of a GFET is a uniform randomvoltage distribution, then the distribution of the drain currentwill be modified by the GFET’s transfer characteristics. Theexact shape of the transfer characteristics varies with thesource-drain voltage V DS . Thus, for a uniform random voltagedistribution at the gate, varying V DS for a GFET changesthe distribution of drain currents. If these drain currents areconverted to a voltage and passed through additional GFETs, itis possible to combine the transfer characteristics and biasingof multiple GFETs to achieve a range of drain current (andhence voltage) distributions. Uniform Random Voltage Distribution V out V ds GFET V ds GFET GFET 1 GFET 2 gate drainsource gate drainsource R R Fig. 2. Example schematic of a possible circuit used to transform a randomuniform noise distribution (V1) into an arbitrary distribution by cascadingseveral individually-biased GFETs.
Figure 2 shows a possible circuit to implement generationof a controllable non-uniform voltage distribution using GFETproperties. Each GFET in Figure 2 has a bias voltage, V DS ,that controls its transfer characteristics. The first GFET hasa uniformly-distributed random voltage across its gate and acorresponding distribution of drain currents, with the valuesof the drain currents for each input voltage determined by thetransfer characteristics of the GFET at its bias voltage V GFET DS .The circuit in Figure 2 converts the drain current of the firstGFET into a voltage input to the gate of the second GFET, usinga resistor, R . In practice, using a transimpedance amplifier(TIA) to perform this current-to-voltage conversion would resultin less Johnson-Nyquist noise in the generated voltages, thoughthe presence of such noise may not be detrimental given ourgoal of generating random variates. The analyses that followin Section V therefore use a resistor for converting the draincurrents to voltages to control the second stage in the circuit.The second GFET in Figure 2, operating at a bias voltageof V GFET DS , further shapes the distribution of the output signal.By selectively connecting multiple GFETs in the manner ofFigure 2 (and possibly using multi-gate GFETs), this methodin principle permits generation of a final output V out with arange of selectable distributions, controlled by the combinationof R , V GFET DS , and V GFET DS . A. Integration with an Existing Computer Architecture
For integration into a larger system, we propose the use ofa programmable analog switching matrix, e.g. a MAX11300[24], such as that illustrated in (Figure 3). This is used as aninterface between an external microcontroller or processor andthe GFET die and allows for dynamic reconfiguration of theGFET circuit. We present a hardware prototype of this analogswtiching matrix in Section IV.The GFET random number generator could be integratedinto a package with an existing CPU and ADC using bondwires to connect the two separate dies. Figure 4 shows a blockdiagram of the arrangement. The maximum frequency, f , andenergy cost, E , for a signal traveling across the bond wiresare . × b/s and . × J/b respectively usingthe values in Table I. The maximum frequency at which abit on the bond wire could change state is calculated usingthe capacitance between the bond wires, C , and the resistance igital ControlAnalogI/O With GFET Circuit Interface w/ Microcontroller D i g i t a l I n p u t s MISOMOSISCLK/CSProgrammable Analog Matrix12 ...
ADCDACSwitchGPIODigital Control
Fig. 3. Schematic of integration hardware used with the GFET circuits, basedon the schematic of the Maxim MAX11300 [24]. The analog I/O connectsto each terminal of each GFET. The zoomed view shows circuitry withinthe programmable analog matrix for control of each terminal. The switchdetermines whether the channel is enabled, the ADC converts an analog signalinto a digital signal read by the CPU, the DAC converts a signal from theCPU to the GFETs and the GPIO ports function as inputs/outputs with acontrollable logic level, e.g. for setting a bias level. All of these are run intoa MUX which is digitally controlled by the microcontroller.
Die 1 ADC
GFETRNGV
Out
CacheCPU
Fig. 4. Connection of CPU and RNG die using bond wires with resistance R across them and capacitance C between them. across a bond wire, R . Hughes et al. [11] show that f is givenby: f = 15 RC . (1)The energy cost of changing the value of a bit on the bondwire is calculated using the logic high voltage V . E is thengiven by [11]: E = CV . (2)The capacitance C used in Equations 1 and 2 is calculatedusing (cid:15) as the permittivity of free space, L as the length ofthe bond wire, a , as the radius of the bond wire, and d as thedistance between them. Grigsby [8] shows that C is given by: C = π(cid:15) L ln d − aa . (3)The resistance R used in Equation 1 is calculated using ρ as the resistivity of a bond wire and A as the cross-sectionalarea of a bond wire. Grigsby [8] shows that R is given by: R = ρLA . (4) TABLE IV
ALUES USED TO CALCULATE LIMITS ON PERFORMANCE .Parameter Value Units Source ρ Ω nm [23] L mm [38] (cid:15) mm s A / g [11] d mm [38] a m [38] These constraints are negligible, the overall speed is limitedby the ADC sample rate and the overall power consumption isdetermined by the ADC and GFET random number generator.
B. Wavelet Decomposition and Reconstruction of Distributions
In signal processing, the Fourier transform decomposes atime-varying signal into its constituent frequency componentsand the Fourier series allows for the construction of an arbitrarysignal from a sum of sines and cosines. This is a special case ofwavelet analysis, which allows for any function to be describedby a set of orthonormal basis functions.In wavelet analysis, an analysing wavelet is used with ascaling function to generate a set of basis functions. Thesebasis functions are simply scaled and shifted versions of theanalysing wavelet [7] and the inner product of the scaling andwavelet functions, which are neccessarily orthogonal, gives amatrix of wavelet coefficients.The discrete wavelet transform (DWT) uses known scalingand wavelet functions to generate a known set of basis functions.When applied to a discrete signal, those basis functions givean approximation of the signal and the signal is characterisedby it’s wavelet coefficients [5]. The inverse transform is simplythe linear combination (i.e. the sum) of these basis functions,and thus allows for reconstruction of the original signal witha desired level of accuracy dependent on the number ofcoefficients used.In the DWT, the set of coefficients can be considered as atransformation matrix or filter which is applied to a data vector.The coefficients are ordered using two patterns: the first actsas a smoothing filter and the second brings out details in thedata. A pyramidal algorithm is used to apply the matrix, withcoefficients arranged such that odd rows containg coefficientsacting as a smoothing filter and even rows contain those actingas those which bring out the data’s detail. Each pair of rowscan be thought of as a level of analysis; as the number of levelsincreases, the total number of inner products is divided by two[7]. Thus, each step smooths the data and so information islost.We demonstrate wavelet decomposition and reconstructionof a distribution in the following example. We show thedistributions reconstructed from inverse DWTs with differentnumbers of coefficients, corresponding to a given level ofaccuracy for the lognormal distribution in Figure 5. We used asecond-order Coiflet wavelet for both the DWT and the inverse-DWT. We chose this wavelet arbitrarily as a proof-of-conceptfor the proposed method, but it appeared to give reasonableresults. We calculated the Kullback-Leibler (KL) divergence16], a measure of the closeness of two distributions, bycalculating the peak positions of the generated distribution andthe reconstructed distributions and comparing them. Figure 5(b)uses the most coefficients and was thus the most accuractereconstruction, with a calculated KL divergence of 0, anidentical reconstruction. Figure 5(c) used less than half thecoefficients of (b) and had a KL divergence of 1.19. Figure 5(d),which used less than a quarter of the coefficients of (b) wasactually closer than (c), with a KL divergence of 0.45. R e l a t i v e F r equen cy (a) R e l a t i v e F r equen cy (b) R e l a t i v e F r equen cy (c) R e l a t i v e F r equen cy (d) Fig. 5. (a)
A software-generated lognormal distribution; (b) reconstructeddistribution using 55 coefficients; (c) reconstruction using 22 coefficients; (d) reconstruction using 12 coefficients. In each case, the x-axis is simply anumber.
Several approaches to implementing wavelet transforms havebeen developed: Stephane Mallat proposed a Fast WaveletTransform algorithm [21] and DWT algorithms have beenimplemented using FPGAs [2]. The output of such an approachwould form part of the digital input in Figure 3. Figure 6 is ablock diagram of a proposed complete system. Section IV andFigure 7 (c) present an early prototype of this system.We have shown that a distribution can be reconstructed froma set of wavelet coefficients determined by a wavelet transform.If we consider these coefficients to be bias voltages for GFETs,which have a tuneable characteristic transfer function with acertain distribution, then the characteristic of a GFET can beconsidered as a mother wavelet, with the bias voltages beingthe scaling parameters. Summing the output of each GFET(or combination of GFETs), with each representing a basisfunction, in principle, allows for the reconstruction of anyarbitrary function, with the accuracy dependent on the numberof GFETs used.IV. GFET F
ABRICATION AND E LECTRICAL C HARACTERIZATION
GFETs in the results presented here consist of an Si substrateonto which we patterned a gold back gate. We grow a 60 nm
Measured DataUniform Random Distribution CPU/MicrocontrollerSwitching Matrix GFET Circuit
Control /DataSignals ... MISO MOSI CLK /CS
Fig. 6. Proposed system to sample from non-uniform distributions. A CPUprocesses some data and takes the DWT, then converting the DWTs scalingparameters into control signals, e.g., bias voltages and configurations of GFETs.The architecture inputs a uniform random variate to the GFET circuit, whichtransforms it into an approximation of the target distribution. The CPU thenreads the approximated distribution from the circuit output. (a) (b)(c) (d)
Fig. 7. (a)
Three GFET array dice, each comprising four GFETS each havingsource, drain, top gate and back-gate contacts; (b) complete GFET die used inthis investigation; (c) the custom PCB for dynamic reconfiguration of GFETcircuits; (d) microscope image of the GFET investigated in this paper. alumina (Al O ) layer by atomic layer deposition (ALD), ontowhich we transfer a monolayer of graphene using a wet transferprocess. This graphene monolayer was grown by chemicalvapor deposition (CVD) and purchased from Graphenea. Afterpatterning the graphene, we deposit the gold source and draincontacts onto the graphene to create a µ m × µ m GFETchannel that lies exactly above the back gate. The channel isinsulated by another layer of alumina, onto which we patterngold top gates aligned with the GFET channels. We electricallypassivate the whole device by a final ALD deposition ofalumina. Finally, to facilitate electrical access to the GFETs,we etch away the alumina on top of the contacts that areelectrically linked to the source, drain, back, and top gates ofthe GFETs.We fabricate four identical GFETs on each silicon die(Figure 7(a)) and we electrically connect the GFETs via wire-bonding the die from its gold contacts (Figure 7(b)) to a customprinted circuit board (PCB) (Figure 7(c)). The PCB comprisesan array of DACs, ADCs, and analog switches, all of whichallow for dynamic and in-situ (re)configuration of a given
10 -5 0 5 10 V GS (V) I D S ( A ) -4 Vds = 1 VVds = 0.8 VVds = 0.6 VVds = 0.4 VVds = 0.2 V (a) V DS (V) I D S ( A ) -3 Vgs = 0.2 VVgs = 0.4 VVgs = 0.6 VVgs = 0.8 VVgs = 1 V (b)
Fig. 8. (a)
Plot of the drain current, I d against the top gate voltage, V GS fordifferent bias voltages of V DS ; (b) plot of the drain current, I d against thesource-drain voltage, V DS for a stepped gate-source voltage V GS . circuit. Because graphene is sensitive to atmospheric effects ,and also to protect the wire-bonding, we place a glass protectivecover over each die once bonded to the PCB, sealed with hotglue. The hardware prototype in Figure 7(c) implements theGFETs required to realise the circuit in Figure 2, as well as theanalog switching matrix described in Figure 3 and Figure 3.We performed electrical characterization of the GFETs usingtwo Keithley 2450 source-measure units (SMUs) synchronizedusing TSP-link. Figure 8(a) shows the transfer characteristiccharacterization results of a fabricated GFETs, with dataobtained by conducting a linear sweep of the (top) gate-source ( V GS ) voltage between − + I DS ). Each curve shows the transfer characteristic fora constant source-drain bias voltage ( V DS ), which we updatedfor each measurement.The Dirac points in Figure 8(a) lie to the left of 0.0 V,which suggests an n-type doping of the graphene channel.The deepening of the valley with increasing bias voltage V DS is a commonly-observed characteristic in GFETs [14],as is the hysteresis in the transfer characteristics, which themeasurements of Figure 8 (a) show for all applied bias voltages.This hysteresis is a result of multiple phenomena: chargetrapping between the graphene channel and the insulating layersare a major cause [19], however, additional factors includecapacitive gating causing a negative shift and charge transfercausing a positive shift [40] in the conductance with respectto gate voltage.We also measured the I DS versus V DS characteristics of theGFETs while varying the gate voltage V GS between 0.2 V and1.0 V, for source-drain voltages V DS over the range 0.0 V to10.0 V. Traditional MOSFETs exhibit saturation of their I DS versus V DS characteristics, with the characteristics separatedinto two main operating regions: linear and nonlinear. In GFETshowever, this saturation does not appear, due to a combination In principle, atmospheric effects can lead to doping of the channel. Theseeffects should however not occur even in the absence of the sealed glassprotective cover, as we fabricated the devices in a cleanroom environment andencased the graphene in alumina as described above. We however cannot ruleout inadvertent doping as a result of the fabrication process.
Measurement -10-50510 V G S ( V ) (a) -10 -5 0 5 10 V GS (V) F r equen cy (b) Fig. 9. (a)
Example of a generated uniform pseudorandom voltage distributionused the simulation; (b) histogram of the voltage distribution. of graphene’s lack of a bandgap and Klein tunneling [26].Figure 8(b) shows the measured characteristic curves for theGFET and Figure 8(a) shows the transfer characteristics.The characterization data in Figure 8(b) indicate that thedevices switch from a relatively linear region of conductanceto a nonlinear region at a bias voltage of around 3.5 V. Thisis in line with previous results which show that GFETs, incomparison to MOSFETs, often have a second linear region;there is a point of inflection [32] which appears to be the casein the plots here, at a V DS of approximately 3.5 V.As we show in Section V, the nonlinearity of the GFETtransfer characteristics, combined with the tunability of thecharacteristic shape by controlling V DS allows us to use oneor more GFETs to trans form uniform distrivutions of V GS into non-uniform distributions of I DS .V. S IMULATIONS OF
GFET C
IRCUITS
We use the GFET characterization data from Section IV tosimulate possible topologies for the GFET-based non-uniformrandom variate generator of Figure 2, using a custom-builtsimulation model of the circuit, implemented in Mathematica.We use an interpolating function to model the measured devicecharacteristics of each GFET and stimulate the gate of thefirst GFET in the circuit using a uniform random distributionbetween − +
8, effectively a V GS voltage in the range − + Ω forthe first resistor and of 1k Ω for the output resistance. Figure10 (a) shows the distribution of currents from the first GFET,and Figure 10 (b) shows the distribution for the second GFET. .8 1 1.2 1.4 I d,GFET1 (A) -4 F r equen cy (a) I DS,GFET2 (A) -5 F r equen cy (b) Fig. 10. Histograms of the GFET current distributions : (a) (b) I DS (A) R e l a t i v e F r equen cy Distribution Generatedby our MethodReference Distribution (a) I DS (A) R e l a t i v e F r equen cy Distribution Generatedby our MethodReference Distribution (b)
Fig. 11. Histograms of simulated transformations of uniform to non-uniformdistributions. (a)
GFET-only based transormation with a reference BurrType-XII; (b)
Combined GFET and computational transform with referencelognormal.
Figure 11 (a) shows final output distribution (i.e., the outputof the first GFET passed through the second GFET).We investigated the possibility of combining the GFET-baseddistribution with additional subsequent software transformationby running a second simulation of the circuit in Figure 2 usingthe experimentally-measured GFET data, with the characteristicfor a 1 V biased GFET as the first GFET and the characteristicfor a 0.8 V biased GFET as the second GFET. We chose aresistance of 1.2k Ω for the first resistor and 1k Ω for theoutput resistance. The initial output distribution was skewedto the right, and so the complementary cumulative distributionfunction, ¯ F ( x ) , given by: ¯ F ( x ) = 1 − F ( x ) , (5)where F(x) is the output distribution of the circuit. To comparethe similarity of the generated distribution to a genuinelognormal, we calculated the mean ( µ ) and standard deviation( σ ) of the logarithm of the simulation output and used these asparameters to generate a lognormal distribution over the sameinput space. Figure 11 (b) shows histograms of the simulationoutput and the reference distribution.VI. E ND - TO -E ND E XAMPLE : M
ONTE C ARLO I NTEGRATION
In Monte Carlo simulations it is common to need to integratevarious un-normalized non-uniform density functions to convertthem to valid probability density functions [34]. Monte Carlo integration is a convenient way of doing this. The normalizationcould require the integration of a lognormal distribution f ( x ) where A is an unknown normalizing constant, µ = 0 is themean and σ = 0 . is the standard deviation: f ( x ) = Axσ √ π e − (ln( x ) − µ )22 σ . (6)Let E be the error of a Monte Carlo integration and t be thetime taken by the integration. Let N be the number of randomsamples used in the integration and D be the distribution thatwe sample from. Let A be the area of each rectangle usedin the integration and b and h be the corresponding rectanglebase and height. Algorithm 1 shows the integration schemethat we used.We repeated the integration with D as: 1) a hardwaregenerated lognormal distribution and 2) a lognormal distributiongenerated with the C++ standard library’s utility for generatinglognormal variates, with the same µ and σ as f . We alsoperformed the integration with D as a uniform distributiongenerated with the C++ standard library’s random numbergenerator, with various ranges. We assume that samples fromthe hardware lognormal generator can be generated in the timerequired for one memory access. We ran all simulations on an2.8 GHz Intel Core i7 CPU using OpenMP parallelization toutilize all eight processor threads. Algorithm 1:
Monte Carlo integration.
Result:
Error E and time t Timer startGenerate N random samples from distribution D Sort N random samples for All pairs of samples do b = Samples[ i ] − Samples[ i − ] h = (f(Samples[ i ]) + f(Samples[ i − ]))/2 A + = b ∗ h end E = abs( − A )Timer stopt = stop − startRETURN E, t
A. Results
Figure 12(a) shows that it is on average . × faster to use aC++ lognormal random number generator than a C++ uniformrandom number generator. Running the program assuming thatthe lognormal samples are generated by the hardware randomnumber generator in the same amount of time required fora memory access is up to . × faster and always at least . × faster than using the C++ lognormal random numbergenerator. Figure 12(b) shows that the error reduction forthe Monte Carlo integration using the [0, 3] C++ uniformrandom number generator plateaus at around samples butfor the hardware lognormal the error continues to decrease. Thelognormal and [0, 3] C++ uniform lines intersect at between and samples and the intersection point shifts to the Number of samples T i m e ( s ) C++ uniformC++ lognormalHardware lognormal (a) Number of samples -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 E rr o r C++ uniform [0,3]C++ uniform [0,10]C++ uniform [0,100]C++ uniform [0,1000]C++ uniform [0,10000]C++ uniform [0,100000]C++ uniform [0,1000000]C++/hardware lognormal (b)
Fig. 12. (a)
Time taken to perform a Monte Carlo simulation for N samplesusing the C++ uniform and lognormal random number generators and theproposed hardware random number generator.; (b) Error in the numericalintegration produced by a Monte Carlo simulation for N samples using theC++ uniform and lognormal random number generators. The error bars showa 90 % confidence interval on the mean of 1000 samples for each point. right as we increase the range of the C++ uniform randomnumber generator. B. Insights from Monte Carlo Integration
Figure 12(b) shows that increasing the range of the C++uniform random number generator decreases the minimumerror that the integration plateaus at. Unfortunately increasingthe range of the C++ uniform random number generator alsoincreases the number of samples required for the estimate ofthe area to approach the true value. The proportion of theuniform probability density function overlapping the lognormalprobability density function decreases as the range of theuniform distribution is increased. For a given function wecannot know beforehand which range of uniform randomnumbers will produce a sufficiently small bound on the errorof integration. We can avoid this problem by sampling fromthe exact lognormal density that we want to integrate. Whenperforming the Monte Carlo integration of any non-uniformdistribution we should sample from the probability densityfunction of that distribution with the same parameters tominimize the error and number of samples required to geta reasonable estimation. This is not possible when samplingfrom a bounded uniform distribution.VII. R
ELATED R ESEARCH
A hardware random number generator, integrated in a CPUcapable of producing samples from arbitrary distributionsdoes not currently exist. Table II shows the state-of-the-artof hardware non-uniform random number generators. The priorwork on non-uniform random number generation in Table IIis fundamentally different to prior work on uniform randomnumber generation. The publications in Table II characterizethe non-uniform distribution of the physical process usedto obtain the random samples. The prior work on uniformrandom number generators does not produce or refer to anon-uniform distribution of random numbers [18], [30], [33],[39]. No comparison can be made between the GFET and
TABLE IIS
TATE - OF - THE - ART IN UNIFORM AND NON - UNIFORM RANDOM NUMBERGENERATION ARCHITECTURES . I
N CONTRAST TO THE METHODS BELOW , THE METHOD WE PRESENT IN THIS PAPER GENERATES ARBITRARYDISTRIBUTIONS AND IS ONLY LIMITED BY THE SPEED OF AVAILABLEANALOG - TO - DIGITAL CONVERTERS (ADC S ). Architecture Speed Distribution(s) Year Paper
Memristor 6.00 kb/s Unnamed 2017 [13]Photon Detection 1.77 Gb/s Exponential 2017 [22]FRET 2.89 Gb/s Exponential 2018 [42]Photo Diode 17.4 Gb/s Husumi 2018 [1]Photon Detection 66.0 Mb/s Arbitrary 2018 [28]Photon Detection 200 Mb/s Normal 2018 [31]Photon Detection 320 Mb/s Exponential 2018 [37]Electronic Noise 6.40 Gb/s Normal 2019 [10]Photon Detection 6.80 Mb/s Exponential 2019 [29]Photon Detection 63.5 Mb/s Exponential 2019 [20]Photon Detection 8.25 Mb/s Normal 2019 [9]Photon Detection 1.00 Mb/s Exponential 2019 [41]Electronic Noise 13.8 kb/s Normal 2020 [25] uniform random number generators. The uniform randomnumber generation efforts excluded from Table II producesingle bit samples where the result is either 0 or 1. The non-uniform random number generation efforts included in Table IIproduce multiple (usually 6 or greater) bit samples with agiven non-uniform distribution. Prior work that is capable ofproducing samples from arbitrary non-uniform distributionsexists [28]. Their method is not well suited for integrationwith current CPU architectures as it requires large opticalcomponents, it is therefore unclear how it could be miniaturizedand integrated into a CPU [28]. In contrast Section III describeshow the GFET random number generator would interface withan existing CPU.Currently no architecture exists with a Gb/s generationrate for arbitrary non-uniform distributions. As the methodwe present is analog, it should be possible to use existingtechnology to drive and sample from it. This will allow us toproduce samples from arbitrary distributions at Gb/s samplerates. Popular statistical tests such as Dieharder are designed forsamples from a [0, 1] uniform distribution and are therefore notcompatible with the non-uniformly distributed random numbersproduced in this work [3].VIII. S
UMMARY AND I NSIGHTS
This article demonstrates a novel circuit-level approach togenerating samples from non-uniform probability distributions,exploiting the transfer characteristics and ambipolarity ofgraphene field-effect transistors (GFETs).We describe the fabrication of arrays of GFETs on a siliconsubstrate and wire bonding of the fabricated devices to acustom PCB. We experimentally characterize the GFET transferand output characteristics at a range of GFET V DS biasvoltage configurations. Using the obtained characterizationdata, we simulate possible circuit designs for non-uniformrandom number generators comprising circuits requiring justtwo transistors and a resistor (or transimpedance amplifier).The results demonstrate that a circuit comprising a chain oftwo GFETs transforms a uniformly-distributed random inputvoltage into a non-uniformly distributed output. In the firstemonstration, biasing the first GFET at 0.8 V, outputtingcurrent through a 2.2k Ω resistor and inputting the resultantvoltage to the gate of the second GFET, biased at 1 V,produces an output voltage distribution through a 1k Ω outputresistor resembling a Burr-type XII distribution. Varying theGFET bias voltages and the resistances permits the circuit togenerate other dynamically-chosen distributions. We generatedan approximation of a lognormal distribution by biasing the firstGFET in the simulation to 1 V and the second to 0.8 V, settingthe first resistor to 1.2k Ω and keeping a 1k Ω output resistance,and then taking the complementary cumulative distributionfunction.We evaluate the end-to-end use of the GFET-circuit-generateddistributions in an application performing Monte Carlo integra-tion. The results show that, using the GFET-circuit-generatednon-uniform distributions instead of uniform random samplesfor sampling locations in the lognormal distribution improvesthe speed of Monte Carlo integration by a factor of up to 2 × .This speedup is based on the assumption that the analog-to-digital converters that will be necessary to read outputs fromGFET-based random number generation circuit can producesamples in the same amount of time that it takes to performmemory accesses. A CKNOWLEDGEMENTS
This research is supported by an Alan Turing Instituteaward TU/B/000096 under EPSRC grant EP/N510129/1,by EPSRC grant EP/R022534/1, and by EPSRC grantEP/V004654/1. N.J. Tye acknowledges funding from EPSRCgrant EP/L016087/1. J.T. Meech acknowledges funding fromEPSRC grant EP/L015889/1.R
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