A Unified Model for Gate Level Propagation Analysis
Jeremy Blackstone, Wei Hu, Alric Althoff, Armaiti Ardeshiricham, Lu Zhang, Ryan Kastner
AA Unified Model for Gate Level Propagation Analysis
Jeremy Blackstone
University of California, San Diego,[email protected]
Wei Hu
Northwestern PolytechnicalUniversity, [email protected]
Armaiti Ardeshiricham
University of California, San Diego,[email protected]
Lu Zhang
Northwestern PolytechnicalUniversity, [email protected]
Alric Althoff
University of California, San Diego,[email protected]
Ryan Kastner
University of California, San Diego,[email protected]
ABSTRACT
Classic hardware verification techniques (e.g., X-propagation andfault-propagation) and more recent hardware security verificationtechniques based on information flow tracking (IFT) aim to un-derstand how information passes, affects, and otherwise modifiesa circuit. These techniques all have separate usage scenarios, butwhen dissected into their core functionality, they relate in a fun-damental manner. In this paper, we develop a common frameworkfor gate level propagation analysis. We use our model to generatesynthesizable propagation logic to use in standard EDA tools. Tojustify our model, we prove that Precise Hardware IFT is equivalentto gate level X-propagation and imprecise fault propagation. Wealso show that the difference between Precise Hardware IFT andfault propagation is not significant for 74X-series and β85 ISCASbenchmarks with more than 313 gates and the difference betweenimprecise hardware IFT and Precise Hardware IFT is almost alwayssignificant regardless of size.
A variety of disciplines track the movement of data through hard-ware designs in order to make important design decisions. Forexample, information flow tracking (IFT) monitors the propagationof security critical information to determine compliance to securityproperties [2β4, 8, 14]; X-propagation aims to understand how non-deterministic values originating from uninitialized registers influ-ence reliability and where they could possibly flow to [1, 5, 6, 10, 13];and fault propagation models the effect of faulty values on sys-tem reliability [7, 11, 16] and susceptibility to implementation at-tacks [9, 15].Although these techniques seek to provide designers with verydifferent types of insight about a design, the steps taken to discoversuch information and their uninterpreted results are very similarand in some cases identical. By taking advantage of these simi-larities, it is possible to cast these problems into a unified formalmodel for gate level propagation analysis. In this work, we developthis unified propagation model, describe how techniques from faultpropagation, IFT, and X-propagation fit into this model, and ana-lytically and quantitatively describe the differences between thesetechniques.Our model takes the original circuit as input and formalizesseparate analysis logic called propagation logic that tracks the prop-agation of values in hardware designs as shown in Figure 1. Thislogic processes labels alongside the original circuit inputs to mark
UnifiedPropagation ModelGate Level CircuitFormal Simulation EmulationRuntime MonitoringHardware Verification Tools (Design Time)
Propagation Logic
Figure 1: Our unified propagation model takes a gate levelcircuit as input and generates a separate synthesizeablepropagation logic. This propagation logic can be analyzedduring design time using existing hardware verificationtools to perform formal, simulation, and emulation. Ifit passes verification, the propagation logic is no longerneeded; it is discarded and the original circuit goes throughthe traditional synthesis process. Additionally, because thepropagation logic is itself synthesizeable, it can be fabri-cated as a runtime monitor checking for propagation vio-lations in the original circuit. some data that we wish to track. The main benefit of our propaga-tion logic is that it is synthesizable. This allows us to analyze thelogic using existing hardware design tools for verification of differ-ent propagation properties such as security violations, initializationerrors, and faulty data. For example, we could use formal verifica-tion tools to prove that two modules are isolated from each other.Using existing hardware simulation tools we could run testbenchesto see if a particular input affects a particular output. Furthermore,we could use existing hardware emulation tools to perform verifi-cation for larger hardware designs. All three of these techniquescan be done at design time so the propagation logic does not needto be implemented providing a zero overhead verification tech-nique for propagation analysis of hardware designs. Additionally,the propagation logic can be realized into its own hardware cir-cuit performing analysis alongside the original circuit for whichinformation is being tracked.The major contributions of this paper are: β’ Developing a general framework for performing symbolicexecution that provides synthesizable analysis logic for mul-tiple data propagation-related problems; β’ Developing propagation logic to track transient faults; a r X i v : . [ c s . A R ] D ec Quantifying the precision differences between imprecisehardware IFT, Precise Hardware IFT, and fault propagation.The remainder of this paper is organized as follows. In Section 2we show how using our unified propagation model allows design-ers to encode different types of propagation analysis techniquesusing propagation logic and labels. Section 3 provides an analyticalcomparison of the techniques to show similarities and differencesand Section 4 makes a quantitative comparison of the techniques tohighlight how much the techniques differ and how different circuitsaffect the amount of data propagation. Section 5 discusses relatedwork and Section 6 concludes the paper.
This section formalizes our unified propagation model. We describehow to use attributes to build different types propagation logic, e.g.related to information flow tracking, faults, and x-propagation. Andwe describe the problem of precision in the propagation modelsincluding the benefits of safe but imprecise propagation logic.
In digital hardware design, the most frequently used circuit modelsare Boolean functions and Boolean gates. Equation (1) is a gen-eral representation of a Boolean circuit, where πΌ , πΌ , . . . , πΌ π are theinputs while π is the output. π = π ( πΌ , πΌ , Β· Β· Β· , πΌ π ) (1)In this work, we focus our analysis on gate level netlists and thusemploy Boolean gates as our circuit model. The Boolean circuitsare composed of Boolean operators or primitive gates, e.g., AND,OR, XOR and Invertor. The key idea for our propagation model is the addition of attributesor labels to the Boolean values that indicate something related tothe propagation, e.g., taint, X-state, and fault. By observing theattribute labels, we can reason about important design propertiesrelated to security, resilience, and fault tolerance. Table 1 showshow attributes are encoded under different application scenarios.
Table 1: Attribute encoding for different applications.
Application 1-Label 0-LabelIFT Tainted UntaintedXPA Non-deterministic DeterministicFPA Faulty Correct
Definition 1 - Taint:
In hardware IFT, we associate data with asecurity label called taint . We define a data object to be tainted if thedata object contains secret information in confidentiality analysisor if it carries untrusted information in integrity analysis [8]. Taintpropagation decides whether or not it is possible for tainted inputsto affect an output. If there is any scenario where a tainted valuecan cause a change in the output, then the output is marked astainted. Otherwise, the output is untainted and there is no taintedinformation flow.
Definition 2 - Non-deterministic:
If there is any scenariowhere the X-state can cause a change in the output, then the outputis non-deterministic . If it is not possible for the X-state to cause achange in the output, then the output is deterministic . We define anoutput data bit to be non-deterministic if toggling the logical valueof a particular unknown input changes the output [8].
Definition 3 - Faulty:
If there is any scenario where a misinter-preted logic value can cause a change in the output, then the outputis faulty. If it is not possible for a misinterpreted logic value to causea change in the output, then the output is correct. We define anoutput data bit to be faulty if simultaneously flipping the logicalvalue of all faulty inputs changes the output [8].
Depending on the attribute label, it is possible to have differentrules for deriving the propagation logic [3]. This creates differentpropagation logic with potentially varying precision and complex-ity. The precision of propagation logic is defined as the degree towhich propagation logic models real circuit behavior. A precisepropagation logic updates the attribute label of the output if andonly if at least one input with the same attribute label has an effecton the output. By comparison, an imprecise propagation logic maycontain false positives or false negatives. A false positive happenswhen the precise propagation logic sets the output attribute labelto logic β0β while the imprecise propagation logic sets the label tologic β1β. A false negative is a case when the precise propagationlogic sets the output attribute label to logic β1β while the imprecisepropagation logic sets the label to logic β0β. A false positive indi-cates non-existent circuit behavior, which makes the propagationlogic conservative when modeling circuit behavior. A false negativefails to capture a circuit behavior that does exist, which makes thepropagation logic erroneous. It is totally safe (although not ideal)for propagation logic to have false positives while false negativesshould be never allowed.A safe, imprecise propagation logic can ignore the effect thatcertain inputs have on the output when calculating the attributelabel for the output to reduce the computational cost. However,this process introduces false positives. More formally, an imprecisepropagation logic is derived from Equation (3) by reducing someinputs while still keeping their security labels. A frequently usedversion of imprecise propagation logic can be described as Equation(2), which completely ignores the effect of inputs on attribute labelpropagation. πΏ ( π ) = π πΏππππ ( πΏ ( πΌ ) , πΏ ( πΌ ) , Β· Β· Β· , πΏ ( πΌ π )) (2)One way to define precise propagation logic is enumeratingpropagation logic truth tables. These truth tables are capable ofanalyzing all possible combinations of input values and attributelabels to determine the output label for all scenarios. While thisis feasible for small primitive gates, such adjective enumerationis usually impractical for larger logic functions. For large circuits,it is far more efficient to constructively generate the propagationlogic for the circuit from smaller propagation logic functions forprimitive gates in a manner similar to technology mapping [4]. .4 Propagation Logic Propagation logic determines how labeled inputs propagate to theoutput labels. That is, it creates logical rules for the output attributelabels based on the input values, their attribute labels, and themethod of propagation. The function is defined as a map from thecircuit inputs and their attribute labels to the attribute label of theoutput as shown in Equation (3). πΏ ( πΌ ) , πΏ ( πΌ ) , Β· Β· Β· , πΏ ( πΌ π ) and πΏ ( π ) are the attribute labels of inputs πΌ , πΌ , Β· Β· Β· , πΌ π and π respectively. πΏ ( π ) = π πΏππππ ( πΌ , πΌ , Β· Β· Β· , πΌ π , πΏ ( πΌ ) , πΏ ( πΌ ) , Β· Β· Β· , πΏ ( πΌ π )) (3)Table 2 shows a partial truth table for label propagation of thetwo-input AND, OR and XOR gates, where the π and π columnsrepresent input values for π and π ; the π π‘ and π π‘ columns are theirlabel values and the remaining columns are the output taint values. Table 2: Partial Truth Table for label Propagation of two-input AND, OR and XOR gates.
Line a b π π π π π΄π π· _ π π ππ _ π π πππ _ π π Line 1 of Table 2shows that when both inputs have a label the output will be alwayshave a label while line 2 indicates that when both inputs are do nothave a label, the output will not have a label.When input π is β0β without a label, the output will not have alabel regardless of the value or label of π . This is because the outputwill be dominated by π to be β0β; the value of π does not have aneffect on the output. Line 3 shows such a case.
Line 4 shows thatwhen one input has a label, the output will be labeled if the otherinput is logic β1β.When considering the full truth table, we can derive the propa-gation logic for all of the gates as shown below.Propagation logic for a two-input AND gate: π π = π Β· π π + π Β· π π + π π Β· π π (4)Propagation logic for a two-input OR gate: π π = Β― π Β· π π + Β― π Β· π π + π π Β· π π (5)Propagation logic for a two-input XOR gate: π π = π π + π π (6)Propagation logic for a NOT gate: π π = π π (7)The propagation logic for NAND, NOR and XNOR can be derivedfrom a combination of the propagation logic for NOT followed bythat for AND, OR and XOR respectively. According to Equations (4)to (7), the propagation logic for NAND, NOR, XNOR are identicalto those for AND, OR and XOR respectively. Figure 2: Imprecise hardware IFT propagation logic for ANDgateFigure 3: Precise hardware IFT propagation logic for ANDgateFigure 4: Precise FPA propagation logic for AND gate.
Figure 2 shows the propagation logic using imprecise hardwareIFT and Figure 3 is constructed from the propagation logic in Equa-tion (4). While the logic in Figure 2 propagates the label regardlessof the inputs, the logic in Figure 3 does more precise analysis tovalidate that it is not possible for input π to have any effect on theoutput under the given input vector. We take into account the effectof logic values in label propagation. As a result, intricacies of thelogic gates actually prevent some tainted information flows.Further, our propagation logic may still contain a certain amountof false positives if the propagation logic is created constructivelyfrom those smaller primitive gates. This is due to variable cor-relation resulting from reconvergent fanouts. However, generat-ing totally precise propagation logic has been proven to be anNP-complete problem [4]. Furthermore, the false positives are notnearly as significant as the taint explosion from imprecise Hard-ware IFT as we demonstrate in section 4.2. The propagation logicderived in this paper provides a good balance between precisionand analysis complexity. able 3: Partial Truth Table for Fault Propagation of 2 inputAND gate, OR gate and XOR gate. Line a b π π π π π΄π π· _ π ππ _ π πππ _ π
04 0 1 0 0 0 1 1 In a general sense, a fault is any disruption in the normal executionof a device that leads to unexpected results. However, we focus ontracking transient faults due to their similarities to the taint and non-deterministic labels. A transient fault occurs during execution whenthe silicon becomes ionized and creates a current that causes thesignal value to be incorrectly interpreted by the circuit. This resultsin a logic value of β0β being interpreted as a β1β or logic value of β1βbeing interpreted as a β0β. Fault propagation seeks to understandthe impact that erroneous behavior will have on a design. It can beused to determine how vulnerable hardware designs are to faultattacks [15] and determine where to apply redundancy to correctthe faults and increase the reliability of the device [11].While some transient faults may affect the output causing thesystem to malfunction, others do not affect output and allow thesystem to function normally. In order to determine which situa-tions produce correct results and which produce faulty results, weconstruct truth tables and utilize them to derive shadow logic forprimitive gates. We refer to this technique as Fault PropagationAnalysis (FPA).Table 3 summarizes when outputs will or will not be faultyfor the primitive gates by comparing gates with correct inputsto gates with one of more faulty inputs. The
π΄π π· _ π , ππ _ π and πππ _ π columns indicate the outputs of AND, OR and XOR gatesrespectively.The following propagation logic can be used to express the in-formation in the AND gate column of Table 3 π π = ( π Β· π π + π Β· π π + π π Β· π π ) Β· Β― ( π β π ) (8)The following propagation logic can be used to express the in-formation in the OR gate column of Table 3 π π = ( Β― π Β· π π + Β― π Β· π π + π π Β· π π ) Β· Β― ( π β π ) (9)The following propagation logic can be used to express the in-formation in the XOR gate column of Table 3 π π = π π β π π (10)The following propagation logic can be used to express a NOTgate π π = π π (11)The propagation logic for NAND, NOR and XNOR can be derivedfrom a combination of the propagation logic for NOT followed by Table 4: Unified Propagation Model Precision Levels
Technique PrecisionImprecise Hardware IFT 0Precise Hardware IFT 1X-propagation 1Imprecise FPA 1Precise FPA 2that for AND, OR and XOR respectively. According to Equations (8)to (11), the propagation logic for NAND, NOR, XNOR are identicalto those for AND, OR and XOR respectively.Although most cases are identical to Precise Hardware IFT andGLX, there are two slight differences. If AND gates and OR gateshave inputs with complementary logic values that are both faulty,they produce the correct output (Line 6). Additionally, XOR gateswill produce the correct output regardless of the input logic valuesif both inputs are faulty(Lines 3, 6, and 9). We refer to these specialcases as fault masking. Furthermore, we refer to FPA that includesfault masking as precise FPA and FPA that does not include faultmasking as imprecise FPA.
Precise Hardware IFT, GLX and FPA can share the same propagationlogic library from primitive gates based on their levels of precisionas shown in Table 4. Here, imprecise hardware IFT is assigneda precision level of zero because it has the most false positivesamong different techniques. These false positives exist becauseneither the functionality of Boolean gates nor the effect of value onlabel propagation is accounted for. Precise Hardware IFT, GLX andimprecise FPA are assigned a precision level of one because theyhave identical propagation logic and eliminate the false positivesintroduced from not considering the effect of individual gates onlabel propagation. While level one is sufficient for Precise HardwareIFT and GLX, imprecise FPA still has false positives due to faultmasking. Precise FPA is assigned a precision level of two because iteliminates false positives from not accounting for fault masking.
In order to illustrate the difference in the levels of precision indifferent techniques, we perform analysis on various gate-levelnetlists and measure the impact of individual signals on the entiredesign. We implement Python scripts to parse circuit netlists intographs where each node denotes a gate and the edges represent itsinput and output signals. After this, we design Python functions toperform the propagation logic for imprecise hardware IFT, PreciseHardware IFT and FPA. For each benchmark, we assign randomtest vectors to the input, mark different percentages of signals witha tainted or faulty label and use our propagation logic to determinewhether or not these tainted or faulty signals would affect theoutputs. igure 5: The difference between imprecise hardware IFT and Precise Hardware IFT is almost always significant regardless ofsize.Figure 6: The difference between Precise Hardware IFT and FPA is not significant for benchmarks with more than 300 gates. .2 Percentage Difference Analysis This section shows experimental results that quantify the differ-ence between imprecise hardware IFT, Precise Hardware IFT andFPA propagation logic functions. First, we performed 1,000 ran-dom tests per benchmark and calculated the percentage of the testswhere the tainted or faulty signals affected the output. Next, weperformed t-tests and calculated bootstrap confidence intervals.T-tests were used to determine if the differences between imprecisehardware IFT and Precise Hardware IFT were statistically signifi-cant for each benchmark and bootstrap confidence intervals wereused to accurately quantify the overall percentage of differencebetween imprecise hardware IFT and Precise Hardware IFT foreach benchmark at a 95% confidence interval. Results are shown inFigure 5.We see that for all benchmarks except c499, c5315 and c7552imprecise hardware IFT is always different from Precise HardwareIFT. Furthermore c499 is the only benchmark where the differenceis not statistically significant. This benchmarkβs Precise HardwareIFT results are very similar to imprecise hardware IFT because it isconstructed in such a way that tainting a decent number of signalsalmost always results in the output being tainted. Although thecomplexity of the propagation logic increases substantially, it willalmost always provide considerable benefit by eliminating falsepositives.T-tests and bootstrap confidence intervals were also used tospecify the percentage difference between Precise Hardware IFTand FPA and the results are shown in Figure 6. We see that mostbenchmarks with fewer than 313 gates (c17, 74182, 74L85, 74181,and c432) show a significant difference between Precise HardwareIFT and FPA ranging from 32.3% to 92.2 %. Alternatively, we seethat all benchmarks with more than 313 gates do not show a sig-nificant difference between Precise Hardware IFT and FPA, onlybeing between 0.8 % and 29.5 % different. This is because the onlycase where GLIFT differs from FPA is fault masking. Significantdifferences were typical for larger circuits because faulty signalswere more sparse and fault masking occurred less. However, forsmaller benchmarks, differences between GLIFT and FPA are quitepronounced. Given these results, in many cases it is more practicalto use precision level 1 rather than level 2 for FPA because com-plexity will be reduced, there will be no false negatives and therewill not be a significant amount of false positives.
Fault propagation, X-propagation, and IFT each have ad hoc toolswhich optimize the analysis of a particular technique. Fault propa-gation uses OneSpin Fault Injection App (FIA). X-propagation usesSynopsys VCS Xprop, Cadence IFV, and Cadence Jaspergold andReal Intent Ascent XV. IFT uses GLIFT.FIA allows the user to define and inject fault scenarios [12].Fault scenarios analyze the effect on the design when particularsignals are faulty and are capable of analyzing different fault types.In addition to this, FIA can associate these fault scenarios withassertions and measure the coverage of the assertions to determinewhich functional areas have verification gaps.Synopsys VCS Xprop is capable of evaluating X-values by com-paring the path where the signal is set to β1β to the path where the signal is set to β0β for X-propagation [1]. Cadence IFV, CadenceJasperGold and Real Intent Ascent XV have this capability as wellalong while providing their own additional features. Cadence IFVcan automatically add X-propagation specific assertions, CadenceJasperGold can provide a failure trace path of a detected X-valuefrom source to destination and Real Intent Ascent XV can interactwith logic simulators to eliminate false positives at runtime.For IFT, GLIFT is able to track all logical information flow onBoolean gates and provide synthesizable analysis logic for creatingsecure architectures [14]. In addition to this, it is possible to isolateparticular areas of a design.Although each of these tools provide unique advantages, not allof them are synthesizable and thus cannot be used in standard EDAsimulation, verification, and emulation platforms. In particular, theX state is not synthesizable and is usually taken as donβt care duringsynthesis which can be optimized to 0 or 1. Thus, it is not possibleto use FPGA prototyping and emulation to accelerate X-simulation.On the other hand, our unified model provides allows designers touse FPGA prototyping and emulation platforms to accelerate thesepropagation problems.
Hardware information flow tracking, fault propagation, and X-propagation, address different problem domains. Yet, at their corethey share many similarities. This paper define a unified frame-work to address information flow tracking, X-propagation and faultpropagation using attribute labels and propagation logic at multiplelevels of precision. This framework is able to take the advantage ofexisting hardware design tools for verification, simulation, emula-tion and runtime monitoring. We observe that for circuits consistingof more than 313 gates, the difference between Precise HardwareIFT and FPA is not statistically significant for ISCAS 74X-seriesand β85 benchmarks while the difference between imprecise hard-ware IFT and Precise Hardware IFT is almost always statisticallysignificant regardless of the size of the design.
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