A Wideband Sliding Correlator based Channel Sounder in 65 nm CMOS: An Evaluation Board Design
aa r X i v : . [ ee ss . SP ] S e p Dipankar Shakya, Ting Wu, and Theodore S. Rappaport “A Wideband Sliding Correlator based Channel Sounder in 65 nmCMOS: An Evaluation Board Design”, in GLOBECOM 2020 - 2020 IEEE Global Communications Conference,
Taipei,Taiwan, Dec. 2020, pp. 1–6
A Wideband Sliding Correlator based ChannelSounder in 65 nm CMOS: An Evaluation BoardDesign
Dipankar Shakya
NYU WIRELESSNew York University
New York City, [email protected]
Ting Wu
Center for Neural ScienceNew York University
New York City, [email protected]
Theodore S. Rappaport
NYU WIRELESSNew York University
New York City, [email protected]
Abstract —Wide swaths of bandwidth at millimeter-wave (mm-Wave) and Terahertz (THz) frequencies stimulate diverse ap-plications in wireless sensing, imaging, position location, cloudcomputing, and much more. These emerging applications moti-vate wireless communications hardware to operate with multi-Gigahertz (GHz) bandwidth, at nominal costs, minimal size, andpower consumption. Channel sounding system implementationscurrently used to study and measure wireless channels utilizenumerous commercially available components from multiplemanufacturers that result in a complex and large assemblywith many costly and fragile cable interconnections betweenthe constituents and commonly achieve a system bandwidthunder one GHz. This paper presents an evaluation board (EVB)design that features a sliding correlator based channel sounderwith 2 GHz null-to-null RF bandwidth in a single monolithicintegrated circuit (IC) fabricated in 65 nm CMOS technology.The EVB landscape provides necessary peripherals for signalinterfacing, amplification, buffering, and enables integration intoboth the transmitter and receiver of a channel sounding system,thereby reducing complexity, size, and cost through integrateddesign. The channel sounder IC on the EVB is the world’s firstto report gigabit-per-second baseband operation using low-costCMOS technology, allowing the global research community tonow have an inexpensive and compact channel sounder systemwith nanosecond time resolution capability for the detection ofmultipath signals in a wireless channel.
Index Terms —Sliding correlator channel sounder, on-chipbaseband, pseudo-random noise sequence, RF grounding, mi-crostrip impedance, printed circuit board
I. I
NTRODUCTION
Wireless communication technologies utilize mm-Wavefrequencies in fifth-generation (5G) cellular wireless [1]–[3],while future sixth-generation (6G) cellular wireless systemsand beyond envision operation at even higher frequenciesinto the Terahertz (THz) range [4]. The higher frequenciesprovide wide swaths of GHz range bandwidth that can beleveraged for diverse applications involving thousands ofinterconnected devices communicating at multi Gigabits-per-second (Gbps) data rates with sub-millisecond latency [5].Especially in the study of wireless channels, GHz widebandwidths allow systems to detect multipath signals at nanosecond time differences which facilitates development ofaccurate channel models for indoor and outdoor environments,and applications such as centimeter level accurate positionlocation, environmental sensing, and imaging [4], [6]–[8].The onward march into higher frequency ranges neces-sitates the improvement of existing RF hardware in termsof operating frequency, bandwidth, noise figure (degrada-tion factor of signal-to-noise ratio by a device), sensitivity(minimum signal level detectable at the receiver), and mono-lithic integration of high performance components [9]. As anexample, present foundry technologies are able to typicallyfabricate transceivers that operate up to 200 GHz with sub-GHz RF bandwidth, noise figures at 9 dB and power ampli-fiers that can provide 180 mW power [9], [10]. Evidently,the operational bandwidth of most commercial-off-the-shelf(COTS) wireless devices remains under one GHz and mono-lithic designs are pursuant of achieving higher bandwidth.Currently, most channel measurement setups also operateunder one GHz bandwidth and involve the integration ofmultiple discrete COTS components including clock sources,amplifiers, mixers, signal generators, and transceivers [11]–[15]. Alongside cost implications, complexity and interfac-ing requirements among multiple components from differentmanufacturers, COTS systems are limited by the maximumchip rate of the baseband electronics, time resolution inthe power delay profile (PDP) of the signals received, anddifficulty in implementing multiple transmitting and receivingchannels in parallel for the study of multiple antenna wirelesscommunications [11], [13], [14], [16].This paper presents an evaluation board (EVB) design thatfeatures an ultra-wideband, programmable, synchronizationcapable channel sounder integrated circuit (IC) implementedin 65 nm complementary metal oxide silicon (CMOS) tech-nology as the principal component. The EVB introduces pe-ripherals necessary to interface the IC into a channel soundingsystem including clock buffers, single ended and differentialsignal converters, amplifiers, programming switches and apower supply. The rest of the paper is organized as follows:Section II describes fundamental concepts involved in design- ig. 1. (a) A transmitter system block diagram that generates pseudo-random noise sequence at chip rate α . (b) A receiver system block diagram with asliding correlator implementation for generating time dilated power delay profiles. (c) Block diagram of the baseband at tansmitter and receiver merged ona single channel sounder chip ing the baseband monolithic IC, Section III highlights theboard design process, and Section IV presents the final boardfabrication with initial test results.II. D ESIGN AND SPECIFICATIONS OF THE ON - BOARDSLIDING CORRELATOR BASED CHANNEL SOUNDER CHIP
A. Sliding correlator based channel sounding
Introduced by Don Cox in [17], sliding correlation is a timetested method for the measurement of ultra-wideband wire-less channels using direct sequence spread spectrum signals.The method involves transmission of a predetermined signalknown both to the transmitter (TX) and receiver (RX) be-forehand, with signal statistics that resemble Gaussian whitenoise, known as the pseudo-random noise (PN) sequence [18].The RF signal received at RX is then correlated with the PNsequence replica which results in a power delay profile of thereceived signal.Fig. 1(a) and (b) are block representations of TX andRX setup in a sliding correlator based channel sounder [16].In reference to Fig. 1(a), initially a PN sequence generator(PNSG) generates a PN sequence, s ( t ) , at a chip rate equalto the fast clock input, α . The PNSG is implemented usingmaximal linear feedback shift registers with programmablefeedback taps. At the subsequent mixer, s ( t ) modulates anintermediate frequency (IF) signal generated by the first localoscillator. The modulated signal at IF is upconverted to theRF carrier frequency, f c , resulting in the RF output signalat f c ± α that is transmitted over the wireless channel. Thewideband signal thus transmitted is subject to reflection,diffraction, scattering, and transmission through blockages inthe channels before arriving at the receiver. The effects of thechannel cause multiple replicas of the transmitted signal toarrive at the receiver over multiple paths at different delays.As illustrated in Fig. 1(b), the received multipath signals aredown-converted and demodulated before sliding correlationis performed with a replica of the transmitted PN sequence operating at a slightly slower clock rate of β , referred to as r ( t ) . The result of the sliding correlation process is a timedilated PDP that represents the time domain response of thechannel, given by: R s ( τ ) = Z T r ( t ) s ( t − t − τ ) dt, (1)The dilation in the time scale of the received PDP corre-sponds to the sliding factor γ , obtained as in Eq. (2). γ = αα − β , (2) B. Design of the on-board channel sounder IC
The dashed blue boxes in Fig. 1(a) and (b) represent thebaseband components of the TX and RX which is combinedby the channel sounder chip design on a monolithic IC designthat is capable of operating at either end of the channelsounder system. As shown in Fig. 1(c), the ‘Mode Control’pin on the IC is used to switch between TX mode for the pinset to ‘Low’ and RX mode for pin set to ‘High’.The output of PNSG 1 directly generates PN sequenceat chip rate of α in TX mode. In RX mode, the output ofPNSG 1, s ( t ) , is mixed with the output of PNSG 2, r ( t ) at chip rate β , to generate the synchronization signal whichis a zero delay absolute timing reference for the multipathcomponents arriving at the receiver. The signal r ( t ) is alsofed into two mixers in order to perform the sliding correlationfunction with the in-phase and quadrature components of thedemodulated received signal. The output of the two mixersconstitute the result of the sliding correlation function, R s ( τ ) .III. D ESIGN AND T ESTING OF THE
EVB
COMPONENTS
A. Channel Sounder IC Specifications based on Measure-ments
Fabricated in a 65 nm CMOS process, the channel sounderchip is a monolithic design of 1 mm × × Fig. 2. The 1 mm × × Initial tests with the chip directly wire bonded to a printedcircuit board (PCB), and a 1.1 V supply voltage verified thesequence accuracy, chip rate, and bandwidth for differentlengths of PN codes. Upon feeding with a 1 GHz clocksignal as α and programming a sequence length of 2047( N − , N = 11 ), the chip sequence was observed in timedomain as the black trace in Fig. 3(a). Peak-transitions in theanalog waveform higher than 0.5 V were recorded as ‘1’,else ‘0’ to obtain the blue trace and verify valid strings ofsame consecutive bits (runs) in the sequence. The spectrummeasurement for the 1 Gbps PN sequence was as shown inFig. 3(b) with the power profile showing a distinct energypeak of -18.4 dBm at 1 GHz, indicating 2 GHz null-to-nullRF bandwidth. Specifications of the chip following the initialtesting are tabulated in Table I [16]. Fig. 3. (a)Time domain measurement of the generated PN sequence; analogwaveform (black), bit sequence (blue). (b) Measured spectrum for the PNsequence operating at 1 Gbps for sequence length N=11
B. Layout of the EVB
The EVB design focuses on interfacing the widebandchannel sounder IC to the 142 GHz channel sounding setupat NYU WIRELESS [15]. The board provides essential pe-ripherals for the IC operation, which perform amplificationand filtering of RF signals, inter-conversion between sig-nal communication methods –differential and single-endedsignaling, buffering and amplification of clock signals, andprovide stable power supply at different voltages. Electroniccomponents on the board are grouped into sub-units based on
TABLE IM
EASURED SPECIFICATIONS FOR THE FABRICATED WIDEBAND CHANNELSOUNDER BASEBAND DESIGN
Item SpecificationTechnology
65 nm CMOS
Maximum Chip Rate
Multipath Delay Resolution
Null-to-Null RF Bandwidth
PN Code Length N − ( N = { , , .., } ,programmable) Power Consumption
IC Packaging
QFN48 6 × Synchronization
SupportedFig. 4. Functional block diagram of the EVB sub-units with relative boardpositioning. Gray highlighted blocks represent DC operating frequency. function and distributed over the board area according to thelayout displayed in Fig. 4.The board is laid out with sub-units operating at DC placedin a separate region from sub-units operating at frequencies upto 1 GHz. The separation of regions helps prevent interferenceon RF signal traces from the DC common-mode, and managereturn paths within separated DC/RF ground planes. It helpspreserve the integrity of signals near RX sensitivity (typicallybelow -100 dBm) common at mm-Wave and THz frequencies.
C. Design considerations for the EVB
Grounding:
All signals flowing in a circuit seek the lowestimpedance path to return to the signal power source tocomplete the circuit. As many signals are operating in atypical circuit, a single wire or trace of limited width andcross-section providing the return connection may have tocarry hundreds of amperes current per cm of cross-sectionarea [21]. Thus, a ground plane is a standard method ofproviding a broad cross-section for returning signal currentswhile minimizing the return path resistance. However, it isnot a panacea for providing return paths to all signals ashe behavior of returning currents varies by frequency. A DCsignal returns over the shortest path on the ground plane,while RF signals seek out the path of minimum impedance[22]. For a two-layer PCB layout with signals routed on thetop and ground on the bottom layer, RF signals above 1 MHztravel directly beneath the top layer signal trace. Furthermore,as DC signal return currents take the shortest path to ground,loops are formed on the ground plane, which may couplenoise and interfere with RF signals.RF signal traces routed on multi-layer PCBs require acontinuous ground plane underneath without any slits andbreakages along the entire return path. The presence ofdisruptions in the ground plane changes the path length forRF signals, as returning signals loop around the breakage[23]. For example, at a millimeter wavelength, the changein path length by a half-mm may put differential signalsin-phase and change the path impedance to cause completesignal reflections. Impedance of RF signal traces:
Reflection of RF signalsis avoided, and maximum power flow is maintained duringthe propagation of an RF signal over traces across the circuitboard when the impedance is uniform throughout the signalpath. Sub-miniature version-A (SMA) connectors with char-acteristic impedance of 50 Ω are commonly used to transportRF signals over the wire in RF systems. Thus, RF signaltraces with a continuous ground underneath, called micro-striptraces, are designed to have 50 Ω characteristic impedance forRF-PCBs, as obtained from Eq. (3) [24]. Z = 87 √ ǫ r + 1 . ln (cid:18) . h . w + t (cid:19) , (3) where,Z = micro-strip impedance ǫ r = dielectric constant of insulating material h = separation between trace and ground in mils(1 mil= 0.001 inches) w = width of the trace in mils t = thickness of the trace in milsThe trace width ( w ) in Eq.(3) may be varied to achievethe 50 Ω impedance. An extension to Eq. (3), shown in Eq.(4), is required to calculate the characteristic impedance fordifferential signal pairs as signals in a differential pair arereferenced to each other and not to ground [24]. Finally, thetrace length determines the input impedance offered by thetrace and the connected load. Z d = 174 √ ǫ r + 1 . ln (cid:18) . h . w + t (cid:19) (cid:16) − . e ( − . dh ) (cid:17) , (4) where, d is the separation of differential pair traces in mils D. Sub-units of the EVB and Test Results
Before implementation on the final EVB, the sub-units weredesigned and tested on individual test PCBs. The test boards were fabricated in-house at NYU-MakerSpace on double-sided bare PCB with 18 µ m copper layers each side separatedby 0.79 mm flame retardant-4 (FR-4) insulation material witha dielectric constant of ∼ Fig. 5. In-house fabricated test boards on double sided PCB. RF connectionsterminated with SMA connectors, DC connections with wire terminal blocks.
Single-ended signal converter and amplifier:
To elimi-nate noise from the power supply, and thermal noise fromexternal components that single-ended signals are subject to,the mixers and amplifiers in the chip baseband are designedfor differential operation [16], [25]. However, the RF signalscarried on coaxial cables interconnecting components of the142 GHz channel sounder, setup at NYU WIRELESS aresingle-ended. Based on Fig. 1(b), to interface the chip inputwith the preceding IF mixer at the RX, each single-endedinput signal from the IF mixers are split into two signalsof equal magnitude but opposite polarity using a 50 Ω Differential signal converter and amplifier:
A slidingcorrelation on two PN sequences results in a low-frequencytime dilated PDP component with distortion components ata frequency above α − β . This waveform is output by thechip in two components, each as a differential signal pair asin Fig. 1(b). The differential signal converter-and-amplifiermerges the output signal pair into a single-ended signal, thenlow-pass filters and amplifies the single-ended signal, usingthe schematic shown in Fig. 6.The merging and filtering stage outputs a single-endedsignal with an amplitude equal to the difference betweenthe two input signal amplitudes. The resistor (R3) and ig. 6. Two stages of the differential to single ended signal converter andamplifier: the merging and filtering stage followed by the amplification stage;implemented with the AD8515 operational amplifier from Analog Devices. capacitor (C5) placed in parallel on the feedback linein Fig. 6 implement a first-order low-pass filter with a3 dB bandwidth of 150 kHz to suppress the distortioncomponent of the waveform. The amplification stage thenamplifies the single-ended signal by gain equal to the ratio ofresistances on the feedback line (R7) to the input line (R8)in Fig. 6, thus implementing a gain of 10 dB. The final boarddesign implements a switch-selectable gain of 3, 10, or 20 dB. Clock Buffer:
Clock signals are crucial to the imple-mentation of a sliding correlator based channel sounder asthey determine the rate of the PN sequence, bandwidth ofthe transmitted signal, and time dilation factor correspondingto γ . Direct distribution of the clock from a clock-sourceinto different board components may degrade the waveformof the clock signal due to the added loading, noise fromthe on-board electronics, and cabling losses. For instance,a 10 pF additional stray capacitance can add a 200 mVp-p ringing distortion on a 500 mVp-p square wave [22].Thus, the addition of a buffer between the clock sourceand clock dependent components can alleviate the waveformdegradation and amplify the clock source prior supplying thecomponents.A 7.5 GHz state-toggling capacity clock buffer is imple-mented as a test board based on Fig. 7, for both the fast andslow clocks α and β in Fig. 1(c). Testing showed a consistent600 mVp-p square wave output at the input clock frequencyfor input down to 60 mVp-p. Power Supply:
The components of the EVB require DCsupply voltage at different levels; the clock buffer operates at3.3 V, the differential signal converter and amplifier operatesat ± Fig. 7. Clock buffer circuit schematic with matched terminations and DCblocking capacitor filters on clock input and output.TABLE IIC
URRENT DRAW FOR EACH SUB - UNIT OF THE
EVB
Sub-Unit of EVB Type Supplyvoltage Currentdraw(standby) Currentdraw(active)
Power supply Active 5 V 4 mA 172 mAClock buffer Active 3.3 V < < IV. EVB F
ABRICATION AND INITIAL MEASUREMENTS
The final EVB is designed on a four-layer PCB withFR-4 dielectric insulation between layers. Micro-strip tracesinterconnecting components are routed on the top-layer withRF ground on the second layer plane. The third layer is usedto distribute power supply lines and the bottom layer forgrounding DC components in non-overlapping regions withthe second layer. Further, the top-layer RF traces are shieldedon either side by regions grounded with vias connected to thesecond layer RF ground. Such ground shielded traces mini-mize additional parasitic impedance from outward radiatingfringing fields, prominent at mmWave and THz frequencies.Based on Eq. (3), the PCB has a top-layer copper of thickness(t) 1.4 mils, a separation (h) of 9.13 mils between each layerwith FR-4 insulation of ǫ r Ω is obtained for micro-strip traces with width (w) of 15.75mils. Differential signal traces on the top-layer have a pairseparation (d) of 25 mils for a differential impedance of 96.56 Ω . The PCB features 50 Ω SMA connectors to interface withexternal components. The final PCB layout of the channelsounder EVB is presented in Fig. 8.Following component assembly, EVB operation yielded apeak current draw of 172 mA at 5 V input when generating atransmit PN sequence at α of 1 GHz, with an energy peak of-30 dBm at 1 GHz in the measured spectrum power profile.The PN waveform showed consistent runs of ones and zeros,as described in [16], at 600 mVp-p for α and β input downto 70 mVp-p from 100 MHz to 1 GHz. ig. 8. Top view of the sliding correlator based channel sounder EVB withall components assembled. Channel sounder IC at the center. C ONCLUSION
A wideband sliding correlator based channel sounder ICfabricated using 65 nm CMOS processes is featured in anEVB design for interfacing with the 142 GHz channel soundersystem at NYU WIRELESS. The monolithic channel sounderIC design, using low-cost CMOS technology, achieves aremarkable 1 Gbps baseband operation; the EVB for theIC implements the baseband of an entire channel soundersetup with null-to-null RF bandwidth of over one GHz. Thisdesign reduces channel sounder system costs from hundredsof thousands to a few thousand dollars while reducing sys-tem complexity, compressing size to portable volumes, anddelivering higher resolution channel measurements. Futureresearch involves interfacing the EVB and channel soundersystem and measuring the board performance in operation.R
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