Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing
Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
22019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in anycurrent or future media, including reprinting/republishing this material for advertising or promotional purposes, creating newcollective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in otherworks.. a r X i v : . [ c s . A R ] J a n ccelerating Transient Fault Injection Campaignsby using Dynamic HDL Slicing Ahmet Cagri Bagbaba ∗† , Maksim Jenihhin † , Jaan Raik † , Christian Sauer ∗∗ Cadence Design Systems, Munich, Germany; † Tallinn University of Technology, Tallinn, EstoniaEmail: ∗ { abagbaba, sauerc } @cadence.com, † { maksim.jenihhin, jaan.raik } @taltech.ee Abstract —Along with the complexity of electronic systemsfor safety-critical applications, the cost of safety mechanismsevaluation by fault injection simulation is rapidly going up. Toreduce these efforts, we propose a fault injection methodologywhere Hardware Description Language (HDL) code slicing isexploited to accelerate transient fault injection campaigns bypruning fault lists and reducing the number of the injections.In particular, the dynamic HDL slicing technique provides fora critical fault list and allows avoiding injections at non-criticaltime-steps. Experimental results on an industrial core show thatthe proposed methodology can successfully reduce the numberof injections by up to 10 percent and speed-up the fault injectioncampaigns.
Index Terms —fault injection, fault simulation, functionalsafety, transient faults, ISO26262, RTL, CPU
I. I
NTRODUCTION
With new and increased capabilities in applications suchas autonomous driving, the complexity of electronics systemsfor safety critical applications is growing exponentially. Thisis causing a shift in the traditional design flow and is push-ing ISO26262 compliance down in the semiconductor chainto the individual IP provider and even into the traditionalElectronic Design Automation tools. As a result, functionalsafety compliance becomes a part of the requirements for thedevelopment of complex electronics systems. During the de-sign of ISO26262 compliant chips, designers need to evaluateeffectiveness of the design to deal with random hardware fail-ures. This is usually done by Fault Injection Simulations. Also,ISO26262 standard highly recommends using of fault injectionduring the development process of integrated circuits [1].Fault injection is a powerful technique that shows the be-haviour of a circuit under the effect of a fault [2]. The objectiveof fault injection is to mimic the effects of faults originatinginside a chip as well as those affecting external buses. Differentapproaches to fault injection and dependability evaluation havebeen proposed. These include emulation-based fault injectionusing FPGA architectures as hardware accelerators to speedup estimation of systems’ fault tolerance [3], [4] and formalmethod based approaches [5], [6]. This paper focuses on thesimulation-based fault injection approach, which can be ap-plied to larger designs compared to the formal and emulation-based solutions.Having enormous number of possible faults in moderndesigns is a major drawback of simulation-based fault injection technique as designers need to execute a fault-free simulationas well as thousands of faulty simulations [7]. Therefore, it istoo hard to inject all possible faults in an acceptable time in allpossible locations and at each clock cycle [8]. One solutionis to use Statistical Fault Injection (SFI) [8] in which onlya randomly selected subset of possible faults is injected. SFIcan provide a better execution time by reducing the numberof the injections with an error margin. Moreover, [9] havedemonstrated that with randomly selected fault lists the ratioof faults which do not produce errors may range as low as2 to 8 percent, depending on the design under simulation.In consequence, minimization of fault injection locations orpruning fault lists are advantageous ways to reduce the faultinjection simulation time significantly while allowing injectionof a considerably larger number of relevant faults.This work proposes a simulation-based fault injectionmethodology based on Dynamic HDL Slicing to minimizethe number of fault injections. The proposed methodologyidentifies critical faults which cause the system to fail inthe absence of a safety mechanism, and injects only criticalfaults during the transient fault injection simulation campaigns.Using critical faults to estimate fault coverage eliminates thepossibility of fault injection experiments to produce no error.The main contribution of this work is three-fold as follows: • Dynamic slicing on HDL to generate critical fault list • Implicit fault collapsing within the slicing model: Thefault list obtained by the proposed slicing method has anadditional feature of avoiding injections at time-steps asdata inside registers is not being consumed. • Language-agnostic RTL fault injection supported by in-dustrial grade EDA tool flowAs a result, this method can successfully reduce the numberof fault injections on an industrial core. The fault modelimplemented in this paper is based on single-clock-cyclebit-flip faults within the RTL registers. This fault model istargeting single Single-Event-Upsets (SEUs) in all the registersof the design. The proposed methodology is demonstrated onCadence tools but it remains applicable to other tool flows aswell. This work is an extension of our previous work [10].The major difference is that we extend dynamic slices’ scopeby including both sequential and combinational parts as it isexplained in Section III-C1. This brings 100% accuracy inthe results. In the previous work, less accuracy is adopted asonly sequential parts are considered in dynamic slices. The second difference is that we evaluate our methodology in theindustrial size CPU with different workloads to demonstratethe potential of the proposed methodology.This paper is structured as following. Section II gives anoverview of related works. We describe our dynamic HDLslicing methodology in Section III. Experimental results areshown in Section IV. Section V concludes this paper.II. R
ELATED W ORKS
There exist many advanced tools and methods forsimulation-based fault injection. In [11], a tool called VERIFY(VHDL-based Evaluation of Reliability by Injection FaultsEfficiently) is presented that utilizes an extension of VHDL fordescribing faults correlated to a component, enabling hardwaremanufacturers, which provide the design libraries, to expresstheir knowledge of the fault behaviour of their components.Although it provides multi-threaded fault injection as well ascheckpoints and comparison with a golden run to speed upthe simulation of faulty runs, the drawback is that it requiresmodification of the VHDL language itself. [12] proposesMEFISTO-C: A VHDL-based fault injection tool that conductsfault injection experiments using VHDL simulation models. Avariety of predefined fault models are supported by the tool;however, it does not provide specific optimizations to speedup the simulation.Several approaches to generate the critical fault list tobe considered as the basis of fault list injection have beenproposed. In [13], a method for generating a critical faultlist is presented. The system under test is described by adata flow graph, the fault tree is constructed by applyingthe instruction set architecture fault model to the data flowdescription with a reverse implication technique, the faultinjection is performed, and fault collapsing on the fault treeis employed. The proposed method is very costly in terms ofCPU time and it therefore not applicable to systems with highcomplexity.[7] presents a new technique and a platform for acceleratingand speeding-up simulation-based fault injection in VHDLdescriptions. Use check-pointing to reload the fault-free stateif the design allowing to start the fault simulation from theclock-cycle of fault injection. In addition, a golden-run faultcollapsing technique is utilized that discards all fault injectionsbetween read-write and write-write operations of the memoryelements. However, the approach does not take advantage of the dynamic slicing benefits. [9] proposes fault collapsingbased on extracting high-level decision diagrams from theVHDL model. Although significant speed-up can be achieved,the step of efficient decision diagram synthesis from the fullsynthesizable subset of VHDL remains an issue.There are several papers dealing with transient fault in-jection. [14] shows the results collected in a series of faultinjection experiments conducted on a commercial processor.Here, the authors inject a fault in a given sequential element ata given instant of time. However, as it is hard to inject a faultin each of the tens of thousands sequential elements in theprocessor, the execution is divided into the parts and, for eachof these parts, a random fault injection instant is selected. [15]analyses fault injection campaign in the CPU registers bychoosing a random instant when the fault is injected. [16]identifies the optimal set of flip-flops but injection time israndomized uniformly over the active region of the simulation.Similarly, [17] injects a fault randomly in time and location inRT-level. Lastly, [18] deals with single and multiple errors inprocessors by randomly selecting injecting time and choosingregisters. As opposed to these works, our approach shows thefault injection time explicitly instead of random instants.Dynamic slicing technique is used in [19], [20]. The formeruses dynamic slicing for statistical bug localization in RTL.The latter proposes dynamic slicing and location-ranking-based method for accurately pinpointing the error locationscombined with a dedicated set of mutation operators.Different from the works listed above, this paper proposesa dynamic HDL slicing based technique that implicitly coversthe golden run fault collapsing, thereby significantly speedingup the fault injection process.III. F
AULT I NJECTION BASED ON D YNAMIC
HDL S
LICING T ECHNIQUE
In this work, fault injection simulation campaigns are opti-mized by pruning the fault list to the critical faults identifiedusing HDL slicing on the RTL design model. The proposedflow is shown in Fig. 1 and starts with the (1) extractionof static slices for the target observation point. In parallel,code coverage data is generated by (2) simulation-based codecoverage analysis for the design with pre-defined stimuli in thetestbench. Next, (3) the dynamic slicing procedure identifiesthe intersection of the identified static slice and coveredcode items and results in a set of clock-cycle-long dynamic ig. 2. HDL slicing on a motivational example chopper [10]. slices for the given observation point. Finally, (4) the faultinjection simulation selects critical faults from the dynamicslices, injects them at the specified time and evaluates the faultpropagation. We explain the details of the methodology in thefollowing subsections using a motivational example depictedin Fig. 2, i.e. a VHDL implementation of a signal chopper design [21]. Following subsections explain each step of theproposed methodology in detail.
A. Static Slicing
Static slice, as it is implemented in the current paper,includes all statements that affect the value of a variable v for all possible inputs at the point of interest, e.g., atthe statement x , in the program. In the RTL code, staticslice shows the dependency between HDL statements [22]. Asimple design chopper in Fig. 2 has four outputs representingdifferent chops for the input signal SOURCE based on thedesign configuration by inputs
INV and
DUP . It is possible toperform a search backward to find dependencies in the HDL.The resulting static slice is computed for the chopper design’soutput
TAR F as shown in Fig. 3 by the help of formal analysistool’s structural analysis capability. The column Static Slice inFig. 2 marks HDL statements of a static slice on the
TAR F output. For instance, as the static slice of
TAR F does notinclude Line 40, H0 is counted as outside of the static slice and for a TAR F output there is no need to inject fault on H0 .Fig. 2 also implies that, static slice does not depend on clockcycles (shown as C1, C2, C3, C4 and C5) while executedstatements and dynamic slice may change for each clockcycle. In summary, static slice includes statically availableinformation only as it does not make any assumptions oninputs. Static slice is the first step of the proposed methodologyto prune fault list. B. Coverage Analysis
In parallel to static slicing step, the RTL design is simulatedin the logic simulation tool to dump and analyse the coveragedata. In this step, we dump coverage data for each clock cycleso that we can find what statements in the RTL are executedfor each clock cycle. In the proposed methodology, one clockcycle defines the size of our dynamic slice. We use coveragetool and coverage metrics in order to find executed statements.After loading a simulation run into the coverage tool, wecan analyze coverage metrics data scored in that run. In thiswork, we use code coverage which measures how thoroughlya testbench exercises the lines of HDL code. Code coverageincludes block coverage, branch coverage, statement coverage,expression coverage, and toggle coverage. All these coveragetypes except toggle coverage can be used in this work. Blockcoverage identifies the lines of code that get executed during aimulation run. It helps us determine if the testbench executesthe statements in a block. Branch coverage complementsblock coverage by providing more precise coverage results forreporting coverage numbers for various branches individually.Statement coverage is just a subset of block coverage andit shows execution of all the executable statements in theRTL. Expression coverage provides information on why aconditional piece of code was executed. At the end of thisstep, we generate executed statements data to find dynamicslices in the next step. Fig. 2 shows executed statements forfive clock cycles (C1, C2, C3, C4, C5).
C. Dynamic Slicing
Dynamic slice, as it is implemented in the current paper,includes those statements that actually affect the value of avariable v for a particular set of inputs of the RTL so it iscomputed on a given input [23]. It provides more narrow slicesthan static slice and consists of only the statements that affectthe value of a variable for a given input.In a nutshell, dynamic slice is the intersection of static sliceand executed statements. We illustrate the concept of dynamicslice in Fig. 2. This figure also shows how dynamic slicesnarrow down the fault space when compared to state-of-the-artstatic slice approach. For instance, during the time window C5,register FF (Line 27) is not in dynamic slice meaning that wedo not need to inject fault in FF at C5 time window. Dynamicslice gives us critical faults and eliminates those faults thatare not critical. In this way, we manage to reduce fault list byinjecting only critical faults. This provides a speed-up in thefault injection simulation time as each injected fault increasestotal run time of fault injection campaign.
1) Implicit Fault Collapsing in Dynamic Slices:
In ourproposed methodology, dynamic slices cover both sequentialand combinational parts. In this way, all faults outside ofdynamic slices are 100% undetected and can be collapsed toexclude them from the fault list. When considering the averageCPU time per a fault, an undetected fault spends more CPUtime than a detected fault as the fault injection simulation foran undetected fault lasts until the end of the simulation. Hence,it is very effective to identify undetected faults without runningfault injection campaigns.
Fig. 3. Backward static slice on the signal
TAR F in the chopper design.
In the previous work [10], only sequential parts are con-sidered in dynamic slices; however, both registers (sequential)and combinational parts that are connected to the registers arecounted in dynamic slices in this work. In Fig. 4, dynamicslice is built by considering the register inst dest bin and inst dest (combinational) so that we can have 100% accurateresults. This is called as implicit fault collapsing since weavoid injections at time-steps as data inside registers is notbeing consumed.
D. Fault Injection Simulation
Fault injection enables to verify the capability of a safetymechanism to recognize failures in a design’s functionality, byinjecting faults into the design. In a fault injection simulation,target system and the possible hardware faults are modeledand simulated by the simulator. In this process, the systembehaves as if there is a hardware fault.To inject faults into a design, fault injection simulator needsto know fault target at which to inject fault. In this work,we enable fault instrumentation on the dynamic slices, morespecifically on registers that are in dynamic slices. In otherwords, the proposed method identifies critical faults fromdynamic slices and inject them at the specified times. As afault model, we use Single Event Upset (SEU) fault type whichinverts the value of output of a sequential element and holdthe modified value until it is assigned a new value. Anotherthing that fault injection simulations need is an observationpoint , since the purpose of a fault campaign is to verify thatan error will be observed at some specific point in the design.By defining explicit observation points when running a goodsimulation, we can generate data that will help us to determineif an injected fault is detected or undetected at one or morespecified nets.In brief, fault injection simulation is used to show theeffectiveness of the proposed method. We inject one fault inone simulation run. Also, in the case of having more thanone observation point in the analysis, the proposed methodprevents multiple injection of faults within the overlap of staticslices. IV. E
XPERIMENTAL R ESULTS
In order to verify the accuracy of the proposed fault injectionmethod, we evaluate our application on industrial CPU withdifferent workloads [24]. In the following subsections, firstly,
Fig. 4. Implicit fault collapsing. e explain our experimental setup. Then, we show the resultsin detail.
A. Experimental Setup
Aiming to automate the execution of fault injection cam-paigns using the different tools, an application is developed asin the Fig. 5. This is the more detailed illustration of Fig. 1.We create generic scripts to activate the tools and automatethe flow. In this work, the proposed methodology is integratedinto Cadence flow but it can be applied using tools by anymajor EDA vendor.In the first step, backward static slice is built for a selectedobservation point by using Cadence® JasperGold Formal Ver-ification Platform. Then, we generate coverage results throughCadence® Xcelium™ for each clock cycle that defines the sizeof the dynamic slices. In the next step, static slice and executedstatements data are sent to fault injection simulation to definefault target for the campaign. Annotation results provideinformation regarding to number of injected faults, numberof detected and undetected faults. Moreover, we also use theprofiling feature of the tool that measures where CPU timeis spent during simulation. The profiler generates a run-timeprofile file that contains simulation run-time information thatis useful for comparing execution time of different campaigns.Cadence® Xcelium Fault Simulator is used for fault injectionsimulations.
B. Evaluation and Results
We evaluate our methodology on a 16-bit microcontrollercore [24] with a single address space for instructions anddata. To show the effectiveness of the proposed method,we use three different workloads on openMSP430 . We showour results in two categories as fault list reduction and timesavings. Then, we evaluate the accuracy of this methodologyby comparing our results to a state-of-the-art static slicingoptimization method.In the first step, backward static slice is built from dmem din observation point which is the main output of the core and then
Fig. 5. Overall flow of experimental setup. Fig. 6. Fault list reduction based on three different workloads. coverage data is calculated. Next, considering the registersin static slice, instruction source and destination registers areselected as fault targets to apply the proposed method sincethese registers are widely used in fault injection applicationsas they hold all instructions.Table I shows the comparison of two techniques: a ) state-of-the-art static slicing and b ) dynamic HDL slicing. We performa fault injection campaign for each workload and a fault target(and) for each approach. For the execution of Dhrystone andCoremark workloads with static slicing, we select 100k faultsafter the warm-up phase of the CPU.
1) Fault List Reduction:
Fig. 6 shows the reduction in thenumber of faults injected. All detected faults seen in Fig. 6are critical faults. As seen in this charts, dynamic HDL slicingis effective in pruning the fault list as compared to the staticslicing. Table II shows the percent reduction in the number offaults injection. The best reduction is achieved in Sandboxworkload as a reduction of 9.94%. The magnitude of thefault list reduction depends on the workload characteristics.In this experimental results, the fault list reduction variesbetween 1.36% and 9.94%. These analysis reveal that dynamicHDL slicing prune the fault list and identify the critical faultssuccessfully while analysis and optimization effort costs arevery minor. Additionally, to identify undetected faults andexclude them from the fault list provides a increased faultcoverage as it can easily be seen in Table I.
2) Time Savings:
Table I shows the total CPU time ofoverall regression for each fault injection campaign. Dynamicslicing provides various time savings from 1.58% to 16.91%as shown in Table III. As in fault list reduction, time savings
ABLE IE
XPERIMENTAL R ESULTS ON OPEN
MSP430
Sandbox Dhrystone CoremarkStatic Slicing Dynamic Slicing Static Slicing Dynamic Slicing Static Slicing Dynamic Slicing inst dest bin
Detected 8036 8036 56236 56236 48891 48891Undetected 3996 2852 43764 42404 51109 47809Total 12032 10888 100000 98640 100000 96700Total CPU time of overall regression 1197.1s 994.7s 658919.7s 622459.0s 3437663.0s 3323109.9sFault Coverage 66.788% 73.806% 56.236% 62.735% 48.891% 50.559% inst src bin
Detected 2423 2423 34766 34766 45161 45161Undetected 9609 8413 65234 63498 54839 48051Total 12032 10836 100000 98264 100000 93212Total CPU time of overall regression 1488.2s 1284.2s 803009.1s 790300.0s 3575198.1s 3178378.2sFault Coverage 20.137% 22.361% 34.766% 35.380% 45.161% 48.450%
TABLE IIP
ERCENTAGE OF REDUCTION OF THE TOTAL NUMBER OF INJECTIONSWITH DYNAMIC
HDL
SLICING
Sandbox Dhrystone CoremarkPercentage of reduction Percentage of reduction Percentage of reduction inst dest bin inst src bin
TABLE IIIT
IME SAVINGS USING DYNAMIC
HDL
SLICING
Sandbox Dhrystone CoremarkDynamic slicing time saving Dynamic slicing time saving Dynamic slicing time saving inst dest bin inst src bin depend on the workload characteristic. When consideringthe need of multiple fault injection campaigns in real lifeapplications, this time savings can expeditiously increase.
3) Accuracy:
In this work, we show the results of a faultinjection campaign performed using dynamic slicing, alongwith a state-of-the-art static slicing approach. These resultsreveal that dynamic slicing achieves the same number ofdetected faults as static slicing campaign. This means thatdynamic slicing can be used for different purposes as it isan accurate fault injection methodology. For instance, SFI [8]prunes the fault list in terms of margin of error with a givenconfidence level. However, dynamic slicing exclude only non-critical faults and find all critical faults with a 100% accuracy.V. C
ONCLUSIONS
Fault injection on RTL requires excessively long simulationtime which prevents detailed reliability evaluation of hardwarecomponents with significant number of injections. This paperpresents a method to speed-up fault injection campaigns byminimizing of fault injection locations. The method appliesdynamic slicing on HDL to accurately pinpoint fault injectionlocations and allows injection of critical faults in these timewindows. In this way, this paper narrows down the fault space and provides reduced simulation time. Moreover, average 5-10% extra gain in simulation time for fault injection is asignificant improvement of the total chip validation costs, asthis phase is the most time consuming. The proposed method islanguage-agnostic and suitable for industrial grade EDA toolflows. Experimental results on industrial-size example showthat we achieve significant speed-up of the fault injectionsimulation when comparing to the state-of-the-art flows.A
CKNOWLEDGEMENT
This research was supported by project RESCUE fundedfrom the European Union’s Horizon 2020 research and inno-vation programme under the Marie Sklodowaska-Curie grantagreement No 722325. R
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