Analysing and Measuring the Performance ofMemristive Integrating Amplifiers
Jiaqi Wang, Alexander Serb, Christos Papavassiliou, Sachin Maheshwari, Themistoklis Prodromakis
11 Analysing and Measuring the Performance ofMemristive Integrating Amplifiers
Jiaqi Wang, Alexander Serb, Christos Papavassiliou, Sachin Maheshwari, Themistoklis Prodromakis
Abstract —Recording reliably extracellular neural activities isan essential prerequisite for the development of bioelectronicsand neuroprosthetic applications. Recently, a fully differential,2-stage, integrating pre-amplifier was proposed for amplifyingand then digitising neural signals. The amplifier featured a finelytuneable offset that was used as a variable threshold detector.Given that the amplifier is integrating, the DC operating pointkeeps changing during integration, rendering traditional analysis(AC/DC) unsuitable. In this work, we analyse the operation ofthis circuit and propose alternative definitions for validating thenecessary key performance metrics, including: gain, bandwidth,offset tuning range and offset sensitivity with respect to thememory states of the employed memristors. The amplificationprocess is analysed largely through investigating the transientbehaviour during the integration phase. This benchmarkingapproach is finally leveraged for providing useful insights anddesign trade-offs of the memristor-based integrating amplifier.
Index Terms —neural spike detection, threshold detection, hy-brid CMOS/memristor circuit, integrating amplifier, high sensi-tivity
I. I
NTRODUCTION R ECORDING neural signals using implantable microsys-tems is essential to the development of diagnostic andtherapeutic solutions [1], Brain Machine Interfaces (BMIs)[2] and neuroscience research [3]. The implantable devicetypically contains electrodes as well as front-end and back-endmodule, where raw neural signals collected from electrodeswill be fed into the other two modules for further processing[4]. After processing, analogue neuronal trains [5] or digitalformat [6] will be transmitted to external devices wirelessly.With digital output, a neural spike (Action Potential, AP)detection algorithm which comprises threshold detection anddigitisation can be applied in back-end stage typically [7]. Foran implantable device, this is required to have low power/heatdissipation ( < mW/cm ) in order to avoid damagingsurrounding tissue [8]. The low power dissipation contributesto high integration density. Furthermore, both dc offset [9] andminute extracellular neural activity signals (in the order of 10s-100s of µV ) picked up by electrodes will be fed into front-end devices for amplification and filtering [10]. In summary,the implantable front-end module needs to have low-powerdissipation, low-noise and also to reject dc offset and othernoise interference.To achieve low power consumption, a number of multi-channel neural recording architectures has been proposed [11] J. Wang, A. Serb, S. Maheshwari and T. Prodromakis are with the Centrefor Electronics Frontiers, Zepler institute, University of Southampton, UK,SO171BJ. C. Papavassiliou is with the Department of Electrical and ElectronicEngineering, Imperial College London, UK. Corresponding author e-mail:([email protected]). [12] [13]. It is clear that the energy consumed in the analoguemultiplexer before ADC can be reduced to improve powerefficiency. From the system level point of view, Serb et al. [14]propose to perform spike detection and digitisation directly onthe neural signal from electrodes in order to save power fromprocessing local field potentials (LFP) which will be discarded.Preamplifiers are critical for boosting the extremely weakinput signals to levels where they can be further processedand so they act as the first stage in any neural recordingprocessing (a result of the Friis formula) [15]. Alternatively,the operational transconductance amplifier-capacitor (OTA-C)structure is suitable for bio-electronic devices as the low-pass filter for neural signals [16]. The objective of combiningan OTA with load capacitor is to integrate signals insteadof simply amplifying them in continuous mode in order toboost effective gain. A different technique has been proposedto compensate the DC offset of the electrode-tissue interface[17] [18] [19]. The Harrison topology is capable of rejectinglarge dc offset, operates in continuous mode and is the currentstandard in the field [20]. It is possible to conduct thresholddetection directly on the signals in Harrison amplifier. [14].With the characteristic of analogue modulation of theirresistive state, memristive devices can be utilised in CMOScircuit as trimming component [21]. Such an integrating pre-amplifier enhanced with offset tuning for ultra-fine thresholddetection was proposed [14]. In this work, memristive deviceswere utilised as non-volatile resistive loads [22] to trim theoffset voltage with high precision.The architecture and preliminary analysis presented in [14]demonstrated the general operating principle of what we maydescribe as a ”memristive integrating amplifier”. In this workwe add detail on the operation of this type of amplifier as wellas investigate how important parameters such as clocking anddifferential/common input voltage affect performance. One ofthe challenges identified in doing this is defining importantperformance (e.g. gain, bandwidth, CMRR and etc.) in amanner suitable to the operation of integrating amplifiers. Weprovide such metrics that suit the particular implementationof the memristive integrating pre-amplifier. The mathematicaldescriptions of the resulting metrics and insight obtainedfrom examining the behaviour of transistors during the keyintegration phase of the amplifier illuminate various trade-offsthat characterise the design. This work has been done usingcommercially available . µm CMOS technology with . V supply voltage across all the experiments.The paper is organised as follows: A brief overview of thepre-amplifier and its operation, followed by the re-definitionof its key performance metrics is presented in section II. a r X i v : . [ c s . ET ] S e p Simulation set-up, analysis and results are shown in section III.A discussion of design trade-offs and other points of interestpertaining to the amplifier design is in section IV. Finally,section V summarises and concludes the paper.II. F
UNDAMENTAL OPERATION AND ANALYSIS
A. Amplifier design overview
The architecture studied is a modified/simplified versionof the original design proposed in [14]; it is shown in Fig.1. It consists of three main sections: I) a fully differentialcore amplifier (effectively a single-stage analogue amplifieracting as the 1st stage of the design), II) a dynamic latchedcomparator (DLC) amplifying and quantising the output stateof the core amp and III) a current bias unit powering thesystem’s core. The overall system operates as a thresholddetection circuit which compares two minute input signals andultimately outputs a binary flag, as shown in Fig.2.Each threshold detection operation is carried out in fourphases that we label as: (i) reset, (ii) integrating, (iii) digitisa-tion and (iv) off. These are illustrated in Fig. 3. They remainunchanged from the original work and act as follows:In the reset phase (i) the core amplifier is on ( clk ana , clk rst : high, clk , clk anabar : low) and the load capacitorsare discharged ( V mida/b = 0 ), so that voltage/current incore amplifier is initialised and cleared before integrationcommences in the next phase.In the integrating phase (ii) ( clk ana : high, clk anabar , clk rst , clk : low) the reset transistors (M8&M9) are switchedoff and the currents flowing through the branches of the coreamplifier drain into the load capacitors. From a ‘large signal’perspective, V mida and V midb continuously increase duringintegration. In terms of ‘small signal’, ∆ V mida − midb increaseswith time and normal operation is maintained so long as thecascode transistors M6&M7 remain in the saturation region.The voltage difference between nodes mida and midb isimpacted by the charging speed/current and integration time.Memristors R1&R2 work as trimming devices and tune theoffset of the core with very high sensitivity ( µV /k Ω shownin the original paper). At the end of this phase, V mida/b should be high enough to successfully trigger the DLC and ∆ V mida − midb should be as large as possible for maximisinggain.In the digitisation phase (iii) ( clk ana , clk : high, clk anabar , clk rst : low) clk goes high, triggering the DLCto perform the conversion of V mida/b into the final digitaloutputs. By convention we take the output from the branchwhere output ‘1’ represents a spike while ‘0’ represents theabsence of a spike. Shortly after the decision is committedby the DLC, the core amplifier is turned off as the systemre-enters the off phase.Finally, in the off phase (iv) ( clk : high, clk ana , clk anabar , clk rst : low), the tail current is cut off by setting clk ana to zero. The pre-amplfier is turned off and stopsrecording neural signals. clk anabar is also deactivated (goesto high) thus preventing the accumulated charge across thelarge gate capacitances of M4&M6 from draining away. I II
III
M1 M2 M3M4 M5M6 M7M9M8 R1 R2R3 C1 C2
Vdd
M10clk_ana clk_anabarclk_rstM11 M12 M13 M14M17
Vdd
OUTAOUTBclk clkclk INA INBMIDA MIDB M18M16M15 M19drain_a drain_b
Fig. 1. Architecture of the simplified pre-amplifier. (a) The circuit can bedivided into three parts: (I) core integrating amplifier, (II) dynamic latchcomparator, (III) current bias control unit. In this paper, the clocking signalsare all assumed to be generated by a shared source and be strictly periodic.
B. Differences vs. the original design
The design under study has been simplified vis-a-vis theoriginal from [14] as follows: First a fixed clocking schemewas adopted. The previous design featured an asynchronousclock generation circuit embedded in each channel. Whenit determined that the result would be available on nodes mida/midb it triggered, on-demand, the clocks. However, ithas been observed that the integration results for the very smalldifferential input signals of interest always become availableat fixed intervals; therefore, an on-demand triggering systemis not required here. Second, the sizes of the input transistorpair were decreased. In [14], huge transistors were introducedas input pair to reduce noise. However, the associated largeparasitic capacitances together with the µA tail currents resultin a low transit frequency ( f T ). Therefore, in considerationof speed and power consumption the sizes of input transistorshave been decreased. C. Key performance metrics
The main performance indicators for the core amplifierinclude: gain, bandwidth, offset tuning range and sensitiv-ity on memristor resistance, noise performance, input range,common-mode rejection ratio (CMRR) and power consump-tion. All these metrics (with the exception of power) mostlydepend on the integrating phase, when amplification is con-ducted. In this stage the cascode transistors are in saturation
TABLE IS
IZES OF DEVICES IN THE PROPOSED ARCHITECTURE , WHERE THE BIASCURRENT OF CORE AMPLIFIER IS I tail = 3 µA . R IS REPLACED BY ADIODE CONNECTED
NMOS. T
HE SUPPLY VOLTAGE IS . V AND CONTROLSIGNALS ARE DESIGNED TO FULL RANGE SWING EXCEPT clk anabar
SWINGS BETWEEN . V AND . V .Devices W/L ( µm ) Devices W/L ( µm )M1, M2, M3 3/3 M11-M14 2/0.6M4, M5 200/1 M15,M16 1/0.6M6, M7 20/1 M17, M18 2/0.6M8, M9 1/0.6 M19 1/0.6M10, R3 5/1 C1, C2 200 fF g () V o lt a g e ( V ) g () V o lt a g e ( V ) Time (ms) +100uV1.1V-100uV
V(ina) V(inb)V(outa) V(outb) (b)(a)
Fig. 2. Pre-amplifier basic functionality test: Input A (ina) is slowly sweptbetween [ . V − µV , . V + 100 µV ] over ms while the pre-amplifieris carrying out a conversion every µs to detect the relationship betweeninputs A and B. Input B (inb) remains stable at . V throughout. In this testthe amplifier was balanced ( R R ). When V ina < V inb , the left branchcurrent is larger than the right branch current, inducing V mida − V midb > .The DLC captures this relation and generates binary signals: V outa = 1 and V outb = 0 , which appears in the bottom trace as a predominantly orangeoutput trace. Conversely when V ina > V inb , V outa = 0 and V outb = 1 ,which appears as a combined orange/blue output trace. Note: this type ofsimulation can also be used to test the offset tuning range and tuning sensitivityon the resistive state of memristive devices. When R > R , V ina must belower than V inb to ensure a balanced output, creating an offset. This is readin the output trace as an encroachment of the blue region into the orange (andvice versa for R < R ). mode. As V mida/b keep increasing throughout the integrationphase, there is no set DC operating point. nonetheless, be-cause this is an extremely small signal amplifier, the currentflowing through each branch is under normal circumstancesapproximately the same and constant. This allows for analysissimilar in spirit to regular small-signal analysis by usingtransient simulations for obtaining the relevant data. StandardDC operating point and AC analysis cannot be applied heredirectly. It is perhaps more appropriate to think of V mida/b as‘large signal’ in the mV -range and ∆ V mid = V mida − V midb as ‘small signal’ in the µV -range.
1) Gain:
The gain is defined, as usual, as the ratio ofthe output signal amplitude over the input signal ampli-tude, δV out /δV in . For the core amplifier this translates into δV mid /δV in , where δV mid is taken at the end of the integrationphase and δV in is considered constant for the purposes of thisanalysis. V o lt a g e ( V ) V o lt a g e ( V ) Time (ns) V o lt a g e ( V ) (a)V(drain_b) V(midb) (b) V(outa) V(outb) (i) (ii) (iii) (iv)
V(clk_ana) V(clk_anabar) V(clk_rst) V(clk)(c)
Fig. 3. Timing diagram for neural signal detection. The timing diagram iscaptured from one detection cycle, where we set this cycle starts from ns .The signal-detection cycle period was set at ns , which is subdivided intofour operational phases: (i)reset, (ii) integrating, (iii) digitisation and (iv) offphases. Top panel: clocking scheme (see schematic in Fig. 1). Middle panel:drain signal of input transistor M5 ( drain b ) and integrating node voltage( midb ). Bottom panel: digital output signals; it is these signals that generatethe bottom panel of Fig. 2. (In this simulation, ina = 1 . V + 50 µV and inb = 1 . V ) A more explicit formula can be obtained for the gain: Theinput differential voltage induces through the input differen-tial pair and its associated current branches a difference incurrents: δi = δV in · g m (1)where g m is the transconductance of the input differential pairin normal operating conditions. This induces a difference ofcharge on the load capacitors: δQ = δi · τ (2)where τ is the integration phase duration. Finally, this getstransformed into the voltage difference we observe at δV mid through the load capacitances C : δV mid = δQ/C (3)Combining the above yields the gain (G): G = δV mid δV in = g m · τC (4)Given that we know that the currents filling each loadcapacitor are approximately constant and equal we can expressintegration time τ as a function of the difference in V mid levelsat the start and end of integration ∆ V mid = V mid | t = t e − V mid | t = t , where t and t e denote the start and end of theintegration phase. In our case V mid | t = t = GND = 0 andtherefore ∆ V mid = V mid | t = t e . This is a voltage level thatwe can adjust by choosing appropriate values for the tailcurrent of the amplifier and the integration time. Given thisinterdependence we now seek to find an expression for τ that depends only on engineering parameters. We begin byobserving that: ∆ V mid = ∆ Q/C (5)where ∆ Q is the total charge accumulated on each node( mida/b ) as a result of the tail current. This can, however,be easily expressed as: ∆ Q ≈ i tail/ · τ (6)where i tail/ is the half-tail current of the amplifier core. Thisallows us to express τ as follows: τ = ∆ V mid · C/i tail/ (7)where we replaced the approximation symbol with an equalityfor clarity, since the deviation is expected to be sufficientlysmall under normal operation.Now we can substitute Eq.7 into Eq. 4 and obtain gain as: G = g m · ∆ V mid i tail/ (8)which further simplifies to: G = T E · ∆ V mid (9)where T E is the transconductor efficiency factor of the inputdiff pair transistors. In other words the differential gain of thepre-amplifier core only depends on the
T E and the voltagerange over which we are integrating. Integration time and tailcurrent can be freely traded off, in principle (but considernoise, etc.). Note that ∆ V mid represents voltage differenceduring the integration phase, while δV mid is the output thatcaptured at the end of integration.
2) Bandwidth:
In an integrating amplifier, such as the onestudied here, the notion of bandwidth is somewhat differentthan in continuous mode systems because the output is nota continuous waveform whose Fourier component at somefrequency can be compared in magnitude to an input stimulusof the same frequency. Instead, our amplifier output is asingle value that is influenced (in magnitude) by the inputin proportion to the input’s absolute integral. For a unitmagnitude pure tone signal of angular frequency ω = 2 πf ,the maximum absolute integral within a time window a isgiven by: I eff,max ( ω ) = (cid:12)(cid:12)(cid:12)(cid:12)(cid:90) a − a cos ( ωt ) dt (cid:12)(cid:12)(cid:12)(cid:12) = (cid:12)(cid:12)(cid:12)(cid:12) sin ( ωa ) ω (cid:12)(cid:12)(cid:12)(cid:12) ≤ (cid:12)(cid:12)(cid:12)(cid:12) ω (cid:12)(cid:12)(cid:12)(cid:12) (10)where I eff stands for ’effective integral’. There is no needfor introducing a phase shift φ into cos ( ωt ) ; using the trig-nomoetric identity for cosine of sum of angles we can easilyprove that I eff maximises for φ = 0 .At DC the integral is simply a and subsequently it de-creases within the envelope of /f as frequency increases. Ifwe divide I eff,max by the length of the window we obtainwhat can be interpreted as an attenuation factor: λ ( ω ) = (cid:12)(cid:12)(cid:12)(cid:12) sin ( aω ) aω (cid:12)(cid:12)(cid:12)(cid:12) = | sinc ( aω ) | ≤ (cid:12)(cid:12)(cid:12)(cid:12) aω (cid:12)(cid:12)(cid:12)(cid:12) (11) Fig. 4. Illustration of bandwidth definition within the context of the integratingamplifier. Left panel: Illustration of a pure tone wave fitting exactly 1.5 timeswithin a time window of length 1. Right panel: Attenuation factor (Eq. 11) asa function of tone frequency f in units of cycles/window period ( πτ = πa ).An indicative bandwidth value (BW) is shown for p = 20% . λ declines with aω . Fig. 4 illustrates the evolution of λ with f ; the frequencyof the sinusoid in units of πa . We many now define theeffective bandwidth of the amplifier as the frequency abovewhich λ ( f ) is always below a certain value p . An indicativemeasure of bandwidth may be given by p = 20% . Foran integration period of µs this yields around . M Hz bandwidth. Naturally, p can be set to another suitably chosenvalue to yield different appropriate bandwidth figures. Thismetric holds only so long as the resulting frequency is muchlower than all other RCs in the amplifier core, and thus wehave no additional attenuation. It is worth noting that the mosttypical neural signals of interest, action potentials (spikes), lastin the order of ms . This implies that the even spike featuresof the order of 100s of µs will be integrated without anysignificant attenuation.Throughout our analysis we make the following approxima-tion: the amplifier is integrating linearly throughout its inte-gration voltage range ∆ V mid . The input differential signals ofinterest are so small that linear approximations can be assumedto hold throughout the whole system (eqs. (1) and (6)). Inpractice, there will be some additional distortion due to thechanging V ds experienced by the cascode transistors, but wecurrently ignore this effect in our analysis.
3) Tuning Sensitivity and range:
The memristive devicesapplied in the current branches regulate the charging speed toload capacitors by modulating the effective output resistanceof the core amplifier as seen by the capacitive load. To seethe mechanics of this action we refer to the schematic in Fig.1 and the standard equation for the impedance of a drain-degenerated MOSFET, looking into the source. When this isapplied to the source of M6 we obtain: Z s ≈ g m (cid:18) R R o (cid:19) (12)where Z s is the impedance looking into the source of M6, g m is the differential transconductance of M6, and R o theoutput resistance of M6.Extending this principle to calculate the impedance of M4,as drain-degenerated by the M6-R1 cascade we obtain: Z s ≈ g m (cid:18) Z s R o (cid:19) (13)which eventually unfolds to: Z s ≈ g m + 1 g m g m R o + R g m R o g m R o (14)A similar expression also applies for the right currentbranch.Setting A = g m + g m g m R o and B = g m R g m R o wecan express the impedances seen by M3 looking into eachcurrent branch as: Z l ≈ A + BR (15) Z r ≈ A + BR (16)where Z l = Z s is the left current branch impedance and Z r is the right branch impedance.Next, examining the distribution of tail current across thebranches we obtain an expression for the left branch current i l as follows: i l ≈ i T A + BR A + B ( R + R ) (17)where i T = i is the tail current. Given that B (cid:28) (as it isthe product of two maximum FET amplifier gains), i l can befurther approximated as follows: i l ≈ i T (cid:18) − B A ( R − R ) (cid:19) (18)Similarly for the right branch current i r : i r ≈ i T (cid:18) B A ( R − R ) (cid:19) (19)This yields a total current imbalance of: i l − i r ≈ ∆ i = − i T · B A ( R − R ) (20)which if divided by the common transconductance of theinput differential pair transistors yields the required voltageoffset to rebalance the branches as a function of the differencein RRAM resistive states: V os ≈ V ina − V inb = ∆ ig m , (21)which when fully unfolded yields: V os ≈ − ( R − R ) i T R o,cas g m,in (1 + g m,cas R o,in ) (22)where we have renamed our variables to explicitly stressthe common values of output impedances and differentialtransconductances of the input differential pair and cascodetransistors ( R o,cas = output impedance of cascode transistor, g m,in = diff. transconductance of the input diff pair).This result relies on the standard small-signal assumptionsthat the various g m s and R o s remain constant, all transistorsinvolved remain saturated (either over or below threshold)and crucially, it makes no other assumptions on the voltagepresent at the load capacitors. So long as: a) the g m s of alltransistors remain mostly unchanged and b) the change inload capacitor voltage does not affect the absolute difference in RRAM resistive states seen by the system, the capacitorscharge uniformly under balanced conditions ( V in = V os ).Whilst condition (a) can be reasonably approximated as truein saturation, condition (b) is not generally true because of thenon-linearity in the I − V of the RRAM devices [23]. Analysisof this phenomenon is outside the scope of the paper as itis RRAM technology-specific, but in general if the absoluteresistive state difference changes as the integration processprogresses, we obtain offset voltage drift that may potentiallyaffect operation when a fixed, non-zero offset is specificallyrequired (e.g. for threshold detection with the offset acting asthreshold).Overall, Eq. 22 shows that in small-signal conditions theoffset voltage of the core amplifier is proportional to thedifference in RRAM resistive states divided by the maximumtransistor gains of the input diff pair and cascode transistors.This division explains the extreme fineness of tuning achiev-able.The tuning range can in principle be extended under therule of Eq. 22 for as long as the underlying assumptions hold.We note two important limiting conditions: 1) If the imbalancein currents becomes large, eventually the assumption of equal g m s on both current branches collapses. Exactly when thisoccurs depends on the tightness of the specifications. 2) If thevoltage dropped across the larger of the pair R , becomescomparable to the capacitor voltage range through which theamplifier can integrate while maintaining transistor saturation(normal operation), eventually the amplifier will run out ofintegration voltage headroom. Thus, introducing a headroomvs. maximum tuning range headroom (so long as condition (2)remains the dominant limit).
4) Input-Referred Noise:
The amplifier’s core noise is dom-inated by the input differential pair. The reasons are the sameas in continuous mode amplifiers such as the Harrison [20]:the input pair provides substantial gain through its g m and thusmitigates the input-referred contributions from downstreamelements (primarily the cascode transistors and the RRAMdevices).The standard MOSFET input referred-noise model contain-ing both thermal and flicker noise is given by the followingexpression for spectral density [24]: V in ( f ) = 4 kT γ g m + KC ox W Lf (23)where k is Boltzmann’s constant, T is the absolute temper-ature, γ = for long-channel transistors and higher forshorter channel devices, K a typically empirically determinedfactor scaling /f noise, C ox the gate capacitance, W, L thetransistor sizes and f denotes (linear) frequency.In our amplifier the noise from each transistor in the inputdifferential pair from Eq. 23 propagates to the output via thegain G from Eq. 8 and is then moderated by the attenuationfactor λ from Eq. 11. Moreover, bearing in mind that theamplifier’s output is the difference V mid and that it is operatingin a ‘nearly balanced’ regime, the total noise spectral densityequation at the outputs becomes: V out,total ( f ) = 2 · V in ( f ) · G · λ ( f ) (24) where we substitute all ω s with f for simplicity and haveassumed that both branches contribute equally to noise.We note the following: First, the application of λ ( f ) turnswhite noise into /f (more accurately /af ) and /f noiseinto /f , as is typical of single-pole low-pass filters. Sec-ond, if we desire short integration periods, noise moderationeffect by λ ( f ) may become too weak to make any practicaldifference because of the a (cid:28) factor.Finally, input-referring Eq. 23 and the contributions of λ ( f ) (which can be ignored in this case), we obtain the followingnoise profile: V in,total = 2 · λ ( f ) (cid:18) kT g m + KC ox W Lf (cid:19) (25)where the g m , W and L factors are the same (at leastapproximately) for both transistors in the input diff pair.
5) Input Range:
Under normal operation, the input differ-ential pair transistors M4,5 must be in subthreshold saturation.This implies two operating conditions: (1) A minimum drain-source voltage | V ds,min | = m · V T , where V T is the thermalvoltage and good rule of thumb for ensuring subthresholdsaturation is ≤ m ≤ (here we will use m = 4 ) [25]. (2)We need an appropriate gate-source voltage | V gs, | ( < | V th | ) that allows the transistor to pass ≈ i tail / in subthresholdsaturation. This is treated as approximately constant in thisanalysis.Therefore the common mode voltage V CM is bounded: Thetop boundary is simply: V DD − | V ds,sat, | − | V gs, | ≥ V CM (26)where V ds,sat,x is the drain-source saturation voltage of tran-sistor x . Exceeding the boundary causes M3 to triode andsimultaneously encroaches on V gs, , progressively shutting theamplifier down.The bottom boundary hinges on maintaining the input difer-ential pair in subthreshold saturation ( | V ds, | ≥ | V ds,min, | ): | V ds, | ≈ ( V CM + | V gs, | ) − ( V anabar,low + | V gs, | ) ≥ · V T (27)where V gs, is the gate-source voltage allowing the cascodetransistor to pass ≈ i tail / . This is also treated as approxi-mately constant in this analysis. The 2nd term is recognisedas V drain a under normal operation and node voltage V drain a can be seen in the schematic of Fig. 1. This unfolds to: V CM ≥ V anabar,low + | V gs, | − | V gs, | + 4 · V T (28)Here, the cascode transistor M6 enforces a specific and rela-tively fixed value of V drain a under the control of V anabar,low (similarly for M7 and V drain b ). Combining Eqs. 26 and 28we can find the approximate value of V anabar,low above whichthe input differential pair runs out of common mode range: V anabar,low = V DD − | V ds,sat, | − · V T − | V gs, | (29) From here we can see the trade-off between common modeand integration voltage ranges (directly connected to gain). Ifthe input stage of the amplifier is AC-coupled, the required V CM range may become very small.
6) CMRR and CMGD:
In continuous mode amplifiersCMRR (common more rejection ratio) is defined as the ratioof the differential gain vs. the common mode gain. In our casethis is given by: CMRR = A dm A cm = dGdA cm (30)where A dm , A cm are the differential and common mode gainsrespectively.In a perfectly balanced amplifier (nominal design) this willbe zero at first order, so it would be perhaps more informativeto measure this directly in silico.There is a slightly different effect which will impact ourintegrating amp and can be analysed easily: Gain distortionvs. common mode voltage V CM :We define this ‘common mode gain distortion’ as:CMGD = dGdV CM (31)Taking Eq. 9 and substituting g m = i tail/ V gs, we obtain: G = ∆ V mid V gs, (32)We can now unfold the derivative dGdV CM as follows: dGdV CM = d ∆ V mid V gs dV gs · dV gs dV g = − ∆ V mid V gs · dV gs dV g (33)where dV gs dV g ≈ due to the high impedance of M3.We note that this value could easily be as low as 1 (e.g.consider the case of ∆ V mid = 0 . V and V gs = 0 . V ). Thismeans that for every Volt of change in V CM the gain deviatesby a unit (e.g. G = 25 at V CM = x V means G = 26 at V CM = ( x − V ). Nevertheless, for indicative values of G =25 and V CM fluctuations in the low 100s of mV we obtaingain deviations/errors in the order of .III. P ERFORMANCE MEASUREMENTS AND R ESULTS
In this section, the suitably defined performance parametersfrom the previous section will be assessed for an exampledesign in simulation. We split the results into two groupsfor convenience: differential mode and common mode effects.Under differential mode-related effects we examine the differ-ential gain, bandwidth, and tuneable range/sensitivity of offsetvs. RRAM device resistive state. Under ‘Common mode-related effects’ we include input range (largely determineby the common mode by assumption) and CMRR/CMGD.Finally, power consumption is discussed on its own at theend. For these simulations we used a commercially available . µm CMOS technology with VDD = 1 . V . A. Differential Mode Effects1) Gain:
For the purposes of amplifier gain analysis, wehave run multiple, single data-point amplification transientssweeping a range of input differential voltages centred aroundzero. These simulations are under nominal conditions for thisstudy: no added noise, mismatch or process variation wasincluded.There are two main experiments: First we set an integrationphase run where δV in (cid:54) = 0 and the clk signal does not interruptthe integration process, but rather lets it run its course untilboth V mida/b saturate. Thus, the important features of theresulting waveform (e.g. position of peaks) are revealed. Akey question we seek to answer here is whether there is anoptimum time to stop the amplification in order to reliablyobtain maximum gain, and if so when that occurs. The secondexperiment uses a fixed clock allowing us to explore thegain linearity for fixed integration period: we run multiplesimulation runs with δV in swept from − µV to µV with integration period τ = 150 ns . The key question here iswhether the amplifier has a usable linear range centred aroundthe V differential input and if so, how wide it is.The first experiment is illustrated in Fig. 5(a). We observethat for all test inputs δV in ∈ {− , − , − , , , } µV ∆ V mid increases linearly to a global peak at ≈ ns intothe integration phase and then gradually decreases to zero, atwhich point both V mida/b have saturated and any potentialdifference they had is erased. The peak occurs because aswe keep integrating, the voltage at mida/b nodes eventuallyincreases to the point where the cascode transistors enter thetriode mode. This causes the rate of voltage accumulation onwhichever V mid node is highest to slow first, allowing the othernode to catch up (and leading to the post-peak drop in ∆ V mid ).At this point we are past maximum gain and continuing theintegration eventually equalises the V mid s.Next, we note that the peak gain time is nearly perfectlyaligned for all input samples; the maximum peak time differ-ence is only ps . The high quality of alignment arises becausethe time at which the V mid voltages start trioding the cascodetransistors is determined primarily by the tail current and notthe differential currents. The small discrepancy is explained bythe fact that the peak gain time is technically determined bythe time at which the first of V mida/b reaches the point whereit triodes its cascode transistor. This has two key engineeringimplications: 1) It allows us to set a universally optimal DLCtriggering time. 2) It states that the optimal trigger time isbounded by the trioding time obtained for V mida = min and V midb = max (or vice versa), in which case we have the fastesttrioding corner.The results from the 2nd experiment are shown in Fig.5(b). The differential output voltages δV mid for τ = 150 ns are plotted versus input differential voltage δV in . We noticeexcellent gain linearity arising again from the extremely smalleffect that the differential voltages have on the behaviour of thevoltages at V mida,b . For this experiment the differential inputvoltage was swept on the basis of a fixed input V midb = 1 . V and a swept input V inb ∈ [1 . V − µV, . V + 100 µV ] .Results were linearly fitted yielding a gain of G = 25 V /V δ V(ina) -V(inb) = -100 -50 -5 5 50 100 V, , , , ,(a)(b)
Fig. 5. Simulation results of differential gain analysis. In this simulation, inb was set at . V while ina was swept from . V − µV to . V +100 µV with in steps of µV . (a) ∆ V mid throughout an intentionally excessively longintegration phase. As V mida,b increases the cascode transistors eventuallytriode causing the gain to peak and then start decreasing. Peak gain timesoccur at t = 170 ns and are aligned within ps difference. An indicativeintegration time leaving substantial margin for error can be set to e.g. ns (dashed line in (a)). (b) Output voltage difference δV mid at integration time τ = 150 ns vs. input differential voltage. The result is excellently fitted by alinear curve. The gain is constant at approx. G = 25 .Fig. 6. Simulated bandwidth profile of proposed integrating amplifier.Attenuation factor as a function of tone frequency f in units of cycles/windowperiod ( πτ = πa ), with a = 150 ns in this design. Dashed line indicatestheoretical prediction. ( dB ) with excellent linearity throughout the range (MSE = 0 . ).
2) Bandwidth:
We operated our amplifier with an integra-tion period of ns as shown in Fig.3 and ran a collectionof transient analyses for fixed amplitude pure tone signalinputs. The tone frequencies ranged from 1Hz to M Hz (covers around four cycles of window) and for each frequencythe phases where stepped in increments of o . Additionallywe also carried out a DC run ( δV in = 100 µV ). For eachsimulation run we looked at the amplifier output δV mid after ns of integration. The outcome was a plot of maximum | δV mid | as a function of frequency, as illustrated in Fig.6(normalised to | δV mid | at DC). The resulting curve is closelybounded by the envelope calculated by Eq. 11 indicating nosurprises. To keep λ > , the bandwidth achieves four fifthscycles/window period in Fig.6 that yields . M Hz bandwidth.
We note that if we assume that the highest frequencyspectral component of interest in a neural spike lies at k Hz,the maximum attenuation of this particular design is around . . Therefore we can reliably sample spiking waveformswith this design.
3) Tuneable Range and Tuning Sensitivity:
To obtain thetuneable range and sensitivity of implanted memristive de-vices, multiple transient simulations such as those seen in Fig.2can be repeated while sweeping both RRAM device resistivestates ( R and R ). By tracking at what difference ∆ V in theoutputs flip value we can obtain an estimate for the offset. Thequality of the estimate is calculated as follows: if at cycle n we had V outa = 0 and at cycle n + 1 we obtained V outa = 1 ,it means that somewhere between δV in | n and δV in | ( n + 1) we crossed the amplifier’s offset voltage. The tracking will beapplied in both ascending and descending phase, after whichoffset voltage will be averaged. Assuming that the amplifieralways makes a decision at approximately the same relativetime in each cycle (in our case always at ns into theintegration phase), the duration of this interval is fixed andgiven by the total swept range over the number of samplingcycles. In our case, we run 200 cycles ( µs /cycle for a totalduration of ms ) and sweep the input across a range of µV ( µV ascending and µV descending)Table II shows the offset voltage as a function of R , R .From there we observe: 1) The overall trimming range forthis particular design is ≈ µV . 2) The maximum inducedoffset occurs, as expected, at the maximum R , R imbalancecorners. 3) The offset sensitivity is close to µV /k Ω for anycombination of R , R . 4) The table is almost symmetric (asexpected). The slight asymmetry indicates that the commonmode voltage influences the offset voltage. This effect will bethe subject of a dedicated study. Finally, the quoted offsetswere checked and are the same both on the upward and thedownward slopes, indicating no history-dependence. TABLE IIO
FFSET VOLTAGE OF PRE - AMPLIFIER VS . RRAM
DEVICE RESISTIVESTATE QUOTED AT µV RESOLUTION .R1 \ R2 10 k Ω k Ω k Ω k Ω k Ω k Ω k Ω -35 0 25 55 9570 k Ω -60 -25 0 25 55100 k Ω -85 -50 -25 0 30130 k Ω -115 -80 -50 -25 0
4) Input-Referred Noise:
To estimate the noise behaviourwe employ the following trick: we take the core of the basiccircuit shown in Fig. 1, balance the inputs and add a pair ofideal, noiseless resistors that sink the baseline value of i tail/ for some suitably chosen equilibrium voltage V mida/b = V equil within the amplifier’s integrating range. This is shown in Fig.7(a) (note that we have removed M17&M18 for simplicity -they only increment node capacitance by a small fraction).Then, we need to run our noise analysis and apply the sincmoderation (Eq. 11) in order to obtain our final results.Before we begin, we need to make some key observa-tions/assumptions: 1) At DC equilibrium, what is left on V mid after removing the baseline tail currents is fluctuations due M4 M9M8C1 R2 C2R1M6 M7M5M3drain_a drain_bMIDA MIDB
Vdd clk_rst clk_anabar
INA INBVbRcomp Rcomp Frequency (Hz) -9 -8 -7 -6 unmoderated noisemoderated noise I npu t - R e f e rr e d N o i s e ( V / s q r t ( H z )) (a) (b) Fig. 7. Noise Simulation. (a) Schematic used for running noise analy-sis. Noiseless baseline current compensation resistors R comp = 330 k Ω were used. The resistors divert the baseline current coming from the tailtransistor M3 so that at equilibrium any remaining voltage fluctuations onnodes MIDA,B are attributable to noise. (b) The noise spectrum presentsunmoderated and moderated input-reffer noise respectively. to noise; there is no other possible source of fluctuation.2) Any distortions introduced by the finite impedance ofthe compensation resistors is negligible due to the minuteinput signals at play. 3) Input-referred output noise levels areexpected to be comparable throughout the entire integrationrange given that most of the noise is generated by theinput differential pair. Additionally, running the noise test athalf-gain is compensation against underestimating the noisegenerated by other sources (most notably the cascode pair).Now we can run our noise analysis.For baseline compensation resistances R comp = 330 k Ω ,we get V equil ≈ . V and a noise spectrum (with andwithout sinc moderation) as shown in Fig. 7(b). Across a [0 . Hz − M Hz ] bandwidth we obtain a root-mean square(RMS) voltage noise level of ≈ µV unmoderated, drop-ping to µV moderated. This represents a saving of ≈ .We also observe a /f corner frequency around Hz . Wehave tested that expanding the included noise bandwidth bothto the left and to the right does not change the above figuressignificantly. The present analysis excludes noise contributionsfrom the RRAM devices.The overall result suggests that for neural probing, the noiselevels obtained for this design may still be slightly too high,especially if we include additional noise from the RRAMdevices. In this case switching to longer integration periodswould help. δ (a)(b)V(outa) V(outb) (c) Fig. 8. Input range results of pre-amplifier. In this simulation, the commonmode voltage was swept from zero to . V with µV differential input.For V CM ∈ [0 . − . V we notice that V midb (a) reaches sufficientlyhigh voltage to prompt a stable output from the DLC (c) within ns oftriggering, and for our chosen differential input the output is always correct.However, the analogue gain in (b) of the core is maximised in the narrowerrange [0 . , . V . B. Common Mode Effects1) Input and Range:
In order to experimentally demonstratethe input range of the amplifier we performed a series of ex-periments querying different potential range limitation factorsin practice. First, we checked the behaviour of the systemat different stages as a function of common mode voltageby running a series of integration cycles whilst sweeping V CM from 0V to VDD in steps of mV . At each run thedifferential input was µV and the outputs were registeredafter integrating for ns . Results were registered at: i) V midb , ii) δV mid and iii) the overall system output after theDLC. Results are shown in Fig. 8. Note: in order to check forpossible input signal history-dependence during these tests,each test integration cycle was preceded by three integrationcycles ran with V CM = 1 . V . We have sample-tested a fewruns with initial V CM between 0.1V and 1.8V and confirmthat the history-dependence effect is negligible.From the results in Fig. 8 we can draw three key conclu-sions: 1) The DLC successfully triggers for V CM betweenapprox. . V and . V . This means that V midb is sufficientlyhigh for the DLC to settle to an output within ns of ittriggering (which occurs when clk goes high). 2) In this casethe DLC provides the correct answer so long as it triggers,but this might change towards the edges of the range oncewe take noise into account. 3) The actual analogue gain ofthe amplifier remains close to maximum ( ≈ dB ) withina narrower region: approx [0 . , . V . We would recommendthat maximum gain area is taken as the effective V CM rangein order to maximise the chances of correctly capturing smalldifferential inputs under noisy conditions. Nevertheless, thisshows that by de-rating the specification of the amplifier tohigher δV mid we can extend its effective input range.In order to visualise the effects leading to loss of gain out-side the region V CM ∈ [0 . , . V we ran some unrestricted CM = 0.9 1.0 1.1 1.2 1.3 1.4 V, , , , ,
Fig. 9. Intermediate differential output ∆ V mid evolution as a function of V CM . Differential input voltage is µV and the integration phase is nottime-constrained, (see Fig.5). Voltage traces for different V CM s follow eachother closely except in the edge cases V CM ∈ { . V, . V } . integration tests as shown in fig. 5 for different values of V CM .The results are shown in Fig. 9 where we observe that for V CM between . V and . V the integration traces follow eachother very closely, with traces at . V and . V beginning toshow more substantial deviations. We note how excessivelylow V CM s shorten the peak without shifting (a result ofdesaturating the input differential pair but not changing theintegration range) whilst excessively high V CM s shift the peakwithout changing its magnitude.
2) CMRR and CMGD:
For evaluating the CMRR we set thedifferential input to 0V and swept V CM between [0 . , . V.Since we deliberately don’t account for process variations andmismatch in this work, we obtain the expected common modegain of 0.For CMGD, we run a series of integration runs with fixeddifferential input voltage ( µV ) and sweep V CM in steps mV and plot the gain as illustrated in Fig. 10(a). Thehighlighted region where the gain maximises is then resampledat mV step and for each consecutive pair of data pointswe calculate the derivative. As per Eq.33 this yields ourCMGD. Converting appropriately we obtain CMGD ≥ dB for V CM ∈ [0 . V, . V ] . To exemplify this effect, a 0.15Vchange in common mode voltage ∆ V CM causes less than 1.5%change in the output of the amplifier core ( dGdV CM ∆ V CM ). C. Power Consumption
The power consumption has to be assessed for all operatingphases of the pre-amplifier. The most power-hungry phase isthe reset phase since it is the only one where a DC pathexists between the power supplies. For this reason the resetphase should be kept as short as possible. However, it isalso during the reset phase that the core amplifier reachessteady state at all nodes so that the integrating phase can thencommence without any history-dependence, i.e. influence fromor ‘memory of’ its previous inputs. Finding the optimal resetphase duration is a key optimisation task for this design. Next,the cost associated with the integration and digitisation phasescan be split into two main components: First, the integrationcost is equal to charging the core amplifier’s capacitors fromGND to their equilibrium level, where the integration self-terminates ( ≈ . V in our case - note how this integrationcost currently spans both integration and digitisation phasesbecause we do not stop the integration once we trigger theDLCs). Second, the comparison cost is equal to the energy G a i n ( V / V ) CM Voltage (V) -40-20020406080 C M GD ( d B ) CM Voltage (V) (a)(b)
Fig. 10. CMGD simulation results. (a) Core amplifier gain vs. V CM ( ns integration period). The gain remains high and stable in the highlighted area( V ∈ [0 . V, . V ] ). (b) CMGD appropriately converted to dB for therange highlight area in (a). New highlight indicates CMGD ≥ dB . needed to operate the DLC. Finally, during the ‘off’ phasepower dissipation is mainly down to leakages.Through one detection cycle ( ns ), the average energyconsumption is . pJ , of which f J during the re-set phase, f J during the integration phase and f J during digitalisation. This yields a power rating of . µW for continuous operation (no off phase), of which the coreamplifier accounts for µW . If we operate the amplifierat typical biointerface sampling rates of ≈ k Hz, powerdissipation becomes . nW (assuming practically zero ‘off’mode dissipation).For a more complete, multiple channel pre-amplifier, ad-ditional power will be dissipated by 1) the current referencegeneration unit (III in Fig.1), 2) the control system, including clk ana , clk anabar , clk rst and clk generators. Both ofthe above would be shared across multiple channels, yieldinga certain degree of amortisation.IV. D ISCUSSION
From the analysis and simulation of the integrating amplifierwe highlight some key conclusions:First, the performance improvement of the integrating am-plifier over more traditional e.g. Harrison designs relies on theintegration process, which enhances the gain and decreases theeffective bandwidth (helping reduce noise in the process). Tovisualise this let us consider an integrating amplifier usingthe same tail current as a standard OTA first stage. Duringintegration the power dissipation is effectively the same, butthe gain and bandwidth are different. In this sense the designrepresents a trade-off between gain and bandwidth withoutchanging power dissipation or using feedback.Next, we note that there is a natural trade-off between tailcurrent and integration time while keeping the overall energydissipation approximately constant. This is the result of thefixed duration of the reset phase (just enough to clear anyresidual charge at the V mid nodes) and the fact that energy consumption during the integration phase only depends on thesize of the load caps and the voltage change across them duringthat phase. Thus, in principle we can design for a wide rangeof required sampling rates or bandwidths for the same energybudget.The trade is not completely free: Changing the tail currentaffects gain, bandwidth and noise performance, by alteringthe g m s of all transistors involved and the integration period.Furthermore, if using real RRAM devices with non-linearIV curves, changing the tail current also changes the staticresistance of the RRAM devices. Together with changes intransistor g m s this means that the tuneability range is alsoaffected since it depends on the impedance balance betweenRRAM and transistors. Thus, whilst the integrating amplifierclearly offers a lot of design flexibility, the precise designtrade-off space is also not trivial, much like as it is forOpAmps. This is an important subject meriting its own dedi-cated study.The last design decision to highlight concerns the size ofthe load capacitors C . The gain analysis in section II showsthat C doesn’t affect the gain, but it does affect the integrationperiod and therefore can be used to adjust the bandwidth, iffor some reason that cannot be achieved by tweaking the tailcurrent. Effectively it is a design parameter that trades awayenergy for design flexibility.In terms of operation, we note the importance of ensuringthat the integrating amplifier is cleared properly in preparationfor each integrating phase in order to avoid history-dependenceof the output. This means that all node voltages should beequalised across the left and right branches prior to the com-mencement of the sensitive integration phase. In the currentdesign this is achieved by forcefully flushing the system duringthe reset phase, but more energy-efficient approaches are underdevelopment as the rest phase represents a substantial fractionof the energy budget.Finally, we compare our amplifier’s performance with afew standard designs as shown in Table III. We observe aslightly reduced gain and increased noise levels traded againstpower dissipation as a result of our design decisions so far.Importantly, for relatively low precision operations such asthreshold detection of neuronal spikes a 10-fold increase innoise may be an acceptable price for a 100-fold reduction inpower dissipation. We also note that the present design is notcompletely optimised, with an increase in integration time asa very promising avenue of investigation for decreasing noiselevels within the same power envelope. TABLE IIIP
ERFORMANCE AND COMPARISON OF THE PROPOSED AMPLIFIER . IRN:
INPUT - REFERRED NOISE
Work [20] [26] [27] This workTech. ( µm ) 1.5 0.18 0.18 0.18Power ( W ) µ . µ . µ . n @20 kHz Gain ( dB ) 40 40 60 28BW ( Hz ) . k . k k . M IRN @freq.( µV rms ) 2.1 2.14 3.4 34 . − k − k . − k . − M V. C
ONCLUSION
In this work we have performed a theoretical analysis ofthe core functionality of memristive integrating amplifiers andused industrial CAD-level simulations to provide a specificexample for an integrating amplifier design targeting electro-physiological applications. Throughout our analysis we haveconcluded that the performance enhancement over traditional,continuous mode amplifiers can be most intuitively understoodas a gain boosting effect arising from the integration processand showed how this process erodes the amplifier’s effectivebandwidth (which is desirable for electrophysiology applica-tions). Moreover, we have explained how standard metricsof amplifier performance such as gain and input commonmode range, but also new metrics such as offset voltagetuneability range can be described by governing equations foruse by designers. Finally, we implemented an exemplar designin commercially available nm CMOS and demonstratedtypical values for all studied performance parameters that canbe expected from a . µm node technology. These includedgain of V /V , offset tuning range of µV , input-referrednoise of µV rms and power dissipation of . nW at k Hzsampling rate. These are competitive vs current literature foran not fully optimised design.This work is a stepping stone towards de-risking and doc-umenting the RRAM-based integrating amplifier. We believethat the trade-off induced by the integration process in com-bination with the offset trimming enabled by RRAM has thepotential to add a powerful circuit topology to the arsenal ofthe analogue designer.A
CKNOWLEDGMENT
The authors would like to acknowledge this work wassupported in part by the Royal Society Industry Fellow PhDStudent Scholarship and Engineering and Physical SciencesResearch Council (EPSRC) under Grant EP/R024642/1 inFunctional Oxide Reconfigurable Technologies (FORTE) pro-gramme. R
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IEEE Transactions on Circuits and Systems II: ExpressBriefs , pp. 1–1, 2020. Jiaqi Wang received her bachelor degree in Micro-electronic Science and Engineering from ShenzhenUniversity, China, in 2017 and her M.Sc. degree inMicroelectronics Systems Design from University ofSouthampton, UK, in 2018. And she is currentlypursuing her PhD studies in Zepler Institute, Uni-versity of Southampton, working towards memristor-based hardware design, analogue and mixed-signalintegrated circuit design for biosignal processing.
Alexander Serb received his degree in BiomedicalEngineering from Imperial College in 2009 and hisPhD in Electrical and Electronics Engineering fromImperial College in 2013. Currently he is a researchfellow at the Zepler Institute (ZI) dept., Universityof Southampton, UK. His research interests are:cognitive computing, neuro-inspired engineering, al-gorithms and applications using RRAM, RRAMdevice modelling and instrumentation design.
Christos Papavassiliou received the B.Sc. degree inphysics from the Massachusetts Institute of Technol-ogy, and the Ph.D. degree in applied physics fromYale University.,He is currently with the ElectricalEngineering Department, Imperial College London.He currently works on memristor applications, sen-sor devices, and systems and antenna array technol-ogy. He has contributed to over 70 publications onweak localization, GaAs MMICs, and RFIC.
Sachin Maheshwari received his Bachelor’s de-gree in Electrical and Electronic Engineering fromthe ICFAI University, India and Master’s in Mi-croelectronics from Birla Institute of Technologyand Science, Pilani, India. He then obtained hisPhD degree in Electronics Engineering from theUniversity of Westminster, London, U.K. Currently,he is a Research Fellow at the Centre of ElectronicsFrontiers, University of Southampton, Southampton,U.K. His research interest is in Energy RecoveryLogic and Regenerative Neural Networks.