Anomalous Subthreshold Behaviors in Negative Capacitance Transistors
Yu-Hung Liao, Daewoong Kwon, Suraj Cheema, Ava J. Tan, Ming-Yen Kao, Li-Chen Wang, Chenming Hu, Sayeef Salahuddin
11 Anomalous Subthreshold Behaviors in NegativeCapacitance Transistors
Yu-Hung Liao, Daewoong Kwon, Suraj Cheema, Ava J. Tan, Ming-Yen Kao, Li-Chen Wang,Chenming Hu,
Life Fellow, IEEE, and Sayeef Salahuddin,
Fellow, IEEE,
Abstract —Recent measurements on ultra-thin body NegativeCapacitance Field Effect Transistors have shown subthresholdbehaviors that are not expected in a classical MOSFET. Specif-ically, subthreshold swing was found to decrease with increasedgate bias in the subthreshold region for devices measured overmultiple gate lengths down to 30 nm. In addition, improvement inthe subthreshold swing relative to control devices showed a non-monotonic dependence on the gate length. In this paper, usinga Landau-Khanatnikov ferroelectric gate stack model calibratedwith measured Capacitance-Voltage, we show that both theseanomalous behaviors can be quantitatively reproduced withTCAD simulations.
Index Terms —Negative Capacitance, Ferroelectric, ShortChannel Effects
I. I
NTRODUCTION N EGATIVE capacitance field effect transistors (NCFET)rely on a ferroelectric gate insulator to provide an ampli-fication of the gate signal [1]–[3]. This boost, which dependson the capacitance matching between the ferroelectric and Siunderneath, in turn, reduces the power supply voltage require-ments. In a properly designed MOSFET, such a boost can alsolead to a sub-thermal subthreshold swing (SS). However, thestrong function of Si capacitance with voltage and inadequacyof available ferroelectric materials makes it difficult to obtaina sub-thermal subthreshold swing without hysteresis [4], [5].On the other hand, the objective of reducing supply voltagecan be achieved by improving the swing near the thresholdand this can be done without violating the condition necessaryfor zero hysteresis [6]. NCFET so designed can show obviousnon-classical behaviors.Indeed, substantially improved I-V characteristics and non-classical subthreshold behavior have recently been observedin Zr doped HfO gate stack (HZO) [7]–[11] that has a polarorder [12], [13]. Despite the same thermal processing, doping,and MOSFET geometry (Fig. 1(a)), the HfO (Control) andHZO (NCFET) gate stack devices demonstrate opposite trendsof subthreshold swing with respect to gate bias (Fig. 1(b)) [7].Figure 2 shows that for all gate lengths ( L G ) at V DS =0.05V, Y.-H. Liao, D. Kwon, A. J. Tan, M.-Y. Kao, C. Hu and, S. Salahuddinare with the Department of Electrical Engineering and Computer Sciences,University of California, Berkeley, Berkeley, CA 94720, USA. (e-mail:yh [email protected]).S. Cheema and L.-C. Wang are with the Department of Material Scienceand Engineering, University of California, Berkeley, CA 94720, USA.D. Kwon is now with the Department of Electrical Engineering, InhaUniversity Yonghyeon Campus, Incheon 22212, South KoreaY.-H. Liao and D. Kwon contributed equally to this work.This work was supported by the Berkeley Center for Negative CapacitanceTransistors. Fig. 1. (a) Schematic cross-section of the SOI n-MOSFETs. Both HfO (Control) and HZO (NC) devices have the same geometry. (b) SS of HfO andHZO devices demonstrating conventional and anomalous trend with respectto I D , respectively. (c) Equivalent circuit diagram for understanding theMOSFET channel barrier height in subthreshold regime. the NCFET SS is similar to SS of the Control of the samegeometry at low drain current ( I D =10pA/ µ m) but is lowered asthe gate bias increases. The I D at which NCFET subthresholdswing reaches its minimum is almost 4 orders of magnitudelarger than the OFF current. In addition, the difference inthe subthreshold swing between Control and NCFET devices(measured in the range I D =0.1nA ∼ µ m) increases sig-nificantly from L G =100nm to L G =50nm but decreases from L G =50nm to L G =30nm (Fig. 3). Remarkably, these two trendsfor the HZO devices cannot be explained by assuming a“higher- κ ” linear dielectric gate stack which would lead tomonotonically increasing improvement of SS as L G shrinks.Neither are they explainable with a better interface qualitythan the Control, as it would result in a constant SS reductionover different L G . In contrast with normal dielectric theory,these anomalies indicate that NCFET gate capacitance ( C g )(Fig. 1(c)) is affected significantly by both V GS and L G ,of which the explanation lies in the non-linear polarizationresponse to the applied electric field for the HZO gate stacklayer [4], [14].II. TCAD M ODEL C ALIBRATIONS
Sentaurus TCAD [15] simulator parameters are calibratedto C-V and I-V data from [7]. For both Control and NCFET, a r X i v : . [ phy s i c s . a pp - ph ] J un −11 −10 −9 −8 −7 SS ( m V / d e c ) DS =0.05V30nmV DS =0.05V (a) Cont ol (meas)NCFET (meas)Cont ol (TCAD)NCFET (TCAD) −11 −10 −9 −8 −7 DS =0.05V70nmV DS =0.05V (b) −10 −9 −8 −7 D ain Cu ent (A/μm) SS ( m V / d e c ) DS =0.50V30nmV DS =0.50V (c) −10 −9 −8 −7 D ain Cu ent (A/μm) DS =0.50V70nmV DS =0.50V (d) Fig. 2. (a)-(d) Measured and TCAD-simulated SS- I D relations for Controland NC n-MOSFETs of two gate lengths. Two different drain biases areconsidered. Multiple devices are measured for each gate length, all of whichexhibit negligible hysteresis. the gate insulator constitutes of a chemical oxide (8) and2.8nm layer of HfO or HZO. HfO MOSCAP AccumulationC-V measurements can be well matched by a 1.1 nm EOTgate stack in the TCAD model (Fig. 4(a)). The HZO stackdemonstrates a higher capacitance which could be fitted withvery high dielectric constant for the HZO stack. However, thiswould require an effective dielectric constant ( > κ ” dielectric would not be able to replicate theanomalous subthreshold behaviors that we observed. Instead,the capacitance boost is captured by the potential amplificationeffect [11], [14], [21] induced by a the presence polar phaseinside the HZO layer.The calibrated simulation reproduces the experimentallyobserved subthreshold behavior for the Control MOSFET(Fig. 2, 3(a)). NCFETs are simulated by introducing theLandau-Khalatnikov (LK) model for simulating the gate stack,but non-gate-stack parameters are unchanged from the Controldevices. The LK parameters are chosen such that the Ferro-electric in the positive capacitance (PC) region results in thesame gate stack EOT (1.1 nm) as the Control. Therefore, theSS in the low I D (10-100pA/ µ m) region are matched betweenControl and NCFET devices. As the gate bias is increased,the Ferroelectric enters into the negative capacitance (NC)region, which results in a reduced gate stack EOT of 0.9nm inaccordance with the HZO C-V. This transition from positiveto negative capacitance regime successfully captures the near-threshold SS reduction (Fig. 2) with respect to I D as well asthe non-monotonic SS improvement trend with respect to L G (Fig. 3(b) inset). This is discussed in more details later.III. R ESULTS AND D ISCUSSIONS
Fig. 4(b) shows threshold voltage ( V t ) calibration resultswith tungsten work-function set to 4.6eV according to C- Gate Length (nm) SS ( m V / d e c ) (a) Con(rol (TCAD)NCFET (TCAD) Con(rol (meas)NCFET (meas)
Ga(e Len (h (nm) SS c o n t r o l − SS N C ( m V / d e c ) Meas)remen((b)
TCAD
Fig. 3. (a) SS averaged over I D =0.1 ∼ µ m at V DS =0.05V for measuredand TCAD-simulated Control and NC MOSFET. Each marker presents onedevice having the corresponding gate length. (b) Experimentally estimated SSimprovement for different gate lengths. Each error bar presents the estimatedmean and one standard deviation. (Inset) TCAD-modeled Improvements forthe four gate lengths. −1.00 00.75 00.50 00.25 0.00 Ga.e Vol.age (V) G a . e C a p a i . a ) e ( μ F / ( ) (a) ZHO ((ea−/red)HfO ((ea−/red)TCAD (EOT=1.1)()TCAD (EOT=0.9)() Ga.e Le)g.h ()() T h r e − h o l d V o l . a g e ( V ) Charge-NeutralReference (TCAD)
NegativeFixed Charge (b)
Control (TCAD)NCFET (TCAD) Control (meas)NCFET (meas)
Fig. 4. (a) Measured and TCAD-simulated C-V for p-type doped MOS capac-itors with HfO and ZHO gate stacks. (b) Constant-current ( I D =10nA/ µ m)threshold voltage (Vt) at V DS =0.05V for measured and TCAD-simulatedControl and NC MOSFET. Each marker represents an extraction for onedevice. Experimental V t are 0.18V larger than simulated V t without interfacecharge. The discrepancy is resolved when -0.6 µ C/cm fixed charge is addedto the Si/SiO interface. V calibrations (Fig. 4(a)). Note that Control MOSFET V t would be underestimated by 0.18V if no net defect charges areassumed, and this discrepancy is insensitive to geometry anddoping profiles when SS scaling trend is captured. Therefore,the difference between the MOSCAP and MOSFET V F B isascribed to additional defect charges introduced by transistorfabrication processes. A fixed charge density of -0.6 µ C/cm at the Si/SiO interface can not only account for the V t shiftbut also explain the small measured V t difference betweenControl and NC devices (Fig. 4(b)). The voltage drop on thegate stack induced by the charges is less for the NCFET thanthe Control because of its larger C g , which results in a lower V t that is consistent with the experiments. On the other hand,if there were no fixed charges, the NCFET V t would be largerthan the Control V t because of mitigated short channel effects.Note that, the introduction of negative fixed charges into themodel is consistent with our previous work as described in[22] where the transistor fabrication followed essentially theexact same procedure.Fig. 5 shows the transitions from positive to negativecapacitance region of the HZO stack. When V GS ramps up,both I D and the external electric field on the gate stack( E ext = Q G /(cid:15) ) increases. The HZO polarization is directlydetermined by E ext if polarization gradient energy is negligi-ble. The Q G - I D slope in the subthreshold regime is associated Electric Field E tot (MV/cm) G a t e C h a r g e Q G ( μ C / c m ) I n c r e a s i n g V G μ (a) −13 Drain Curren− (A/μ() G a t e C h a r g e D e n s i t y ( μ C / c m ) Solid: Mid-channelDash: Mid-Channel+15nm "NC""PC"(b) E x t e r n a l E l e c t r i c F i e l d ( M V / c m ) Fig. 5. (a) Extracted Q-E relation for the polar layer of the gate stack at themid-channel of NCFETs at V DS =50mV. For each gate length, the gate voltageis ramped at which ID is from 0.1nA/ µ m to 1nA/ µ m. (b) Simulated relationsbetween drain current and (left axis) local gate charge density / (right axis)local external electric field at V DS =0.05V for NCFETs. For each gate length,the solid line is extracted at mid-channel gate stack region, and the dash lineis extracted at the region 15nm laterally from mid-channel toward the drain.The white-background region corresponds to bias conditions at which thepolar layer exhibits negative capacitance, while the dark background standsfor positive-capacitance regime. with input capacitance C gg = ( C g + C s + C d + C Q ) − , whichincreases for reduced L G because of C s and C d increase. Asthe device enters the negative capacitance region, a voltageamplification ensues and drives down the subthreshold swing.This explains why, for the NCFET, the subthreshold swing getssteeper in the sub-threshold regime as V GS or I D increases. Tofully understand the observed anomalous behaviors, especiallythe effect of L G ,one needs to consider the inner fringing fieldthat plays a crucial role on the capacitance matching effect[22], [23]. This field leads to the gate stack-to-source and gatestack-to-drain capacitive coupling which reduces Q G to bal-ance the positively ionized source and drain donor charges forn-MOSFET in subthreshold regime. When L G shrinks, mid-channel Q G corresponding to the same I D decreases becauseof the increased inner fringing field. As a result, although themid-channel gate stack is in the negative capacitance regimefor L G from 50nm to 100nm at I D =0.1nA/ µ m, it remains inthe positive capacitance regime for the 30nm case (Fig. 5).Therefore, the improvement in the subthreshold swing forNCFETs drops for L G =30nm as shown in Fig. 3(b).Notably, the extracted Q G at which the HZO gatestack starts to exhibit negative capacitance is approximately0.5 µ C/cm (Fig. 5(a)). In other words, the S curve is pushedup in the charge axis. This is a consequence of the negativefixed charge that simultaneously explains the V t trend for bothControl and the NCFET. The atypical response can be a resultof antiferroelectric behavior of the tetragonal phase [13] in theHZO or a small but finite leakage that induces positive chargetrapping at the SiO /HZO interface and effectively shifts theS-curve [24], [25]. IV. C ONCLUSION
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