BBest CNTFET Ternary Adders?
Daniel Etiemble
Computer Science Laboratory (LRI)Paris Saclay University
Saint Aubin, [email protected]
Abstract —The MUX implementation of ternary half addersand full adders using predecessor and successor functions leadto the most efficient efficient implementation using the smallesttransistor count. These designs are compared with the binaryimplementation of the corresponding half adders and full addersusing the MUX technique or the typical complementary CMOScircuit style. The transistor count ratio between ternary andbinary implementations is always greater than the informationratio ( log (3) /log (2) = 1.585) between ternary and binary wires. I. I
NTRODUCTION
Many ternary half adders and full adders have been pre-sented in the last decade. The most significant papers are [1],[2], [3], [4]. [5], [6], [7]. In [8], we have compared differentimplementations of quaternary adders. The best quaternaryone has been presented in [9]. It is based on the use ofmultiplexers. In this paper, we show that this approach alsoleads to the best implementation of ternary half and fulladders. The design is based on CNTFET technology. Thistechnology is far from being a mature technology. As of2020, FinFET technology integrates millions of times moretransistors than CNTFET technology. However, CNTFET hasa big advantage for designing multivalued circuits. While itbasically uses the typical CMOS circuit styles, the thresholdlevels of the different multivalued gates can be got by adjustingthe diameter of each used transistor. This technology is usedin this paper. We first present the MUX based design of theternary half adder. Then we present the full adder design.These implementation are compared with the similar MUXbased implementation and the conventional implementation ofthe binary versions.II. T
ERNARY H ALF A DDERS
Table I presents the truth table of the ternary half-adder.Ternary half adders and full adders have ternary inputs andoutputs and binary carry inputs and outputs. • Ternary values (0,1,2) corresponding to 0, V dd / and V dd voltage levels • According to the circuit style that is used, the binaryvalues may have levels 0 and V dd / or 0 and V dd .The technique used in [9] is based on multiplexers. In thisapproach, the carry signals are used as control inputs of MUX:they are never used as input values of these MUX. The binarylevels are thus 0 and V dd . The corresponding binary values are0 and 2. TABLE IH
ALF ADDER TRUTH TABLE
SUM CARRYX/Y 0 1 2 0 1 20 0 1 2 0 0 01 1 2 0 0 0 12 2 0 1 0 1 1TABLE IINI
AND PI BINARY FUNCTIONS
NI PI0 2 21 0 22 0 0
Computation of the Half Adder SUM is processed by thefollowing rules: • When X = 0, SUM = Y • When X = 1, SUM = (Y+1) mod (3). The correspondingcircuit is called successor circuit. • When X = 2, SUM = (Y-1) mod (3). The correspondingcircuit is called predecessor circuit. • According to X, a ternary MUX provides the correctSUM output.Threshold detectors circuits are implemented by the in-verters NI and PI, according to Table 2. These inverters aregenerally called NTI and PTI, but this is confusing as theyare binary inverters: the outputs are binary ones and they onlyhave one threshold level. The only difference with typicalbinary inverters is the specific threshold levels. Assuming V dd , V dd / and 0 ternary levels, the threshold levels are V dd / and V dd / when the threshold level of a binary inverter is V dd / .The NI and PI threshold levels are obtained by choosing theappropriate diameter for the different CNTFET transistors.They are shown in left part of Figure 1. The implementationof the ternary MUX is shown in right part of Figure 1.Figure 2 presents the Successor and Predecessor circuitswith two power supplies ( V dd and V dd / . A, B, C, D outputsof NI and PI inverters control the different transistors: for eachternary input X, only one path is active between V dd or V dd / or ground and the corresponding output. The drawback of thisapproach is the supplementary power supply. Figure 3 presentsthe successor and predecessor circuits with only one powersupply ( V dd ) . The intermediate level is got through a voltage a r X i v : . [ c s . A R ] J a n ig. 1. Threshold detectors and ternary MUX (Ternary inputs and ternarycontrol) divider by using resistor-like transistors. The drawback of thisapproach is a static power dissipation when the output is 1. Fig. 2. Successor and Predecessor Circuits (2 power supplies)Fig. 3. Successor and Predecessor Circuits (1 power supply)
Figure 4 presents the ternary half-adder circuit. The carryoutput is: • When X = 0, C out = 0 • When X = 1, C out = 1 if Y = 2 ( P I ( Y ) = 2 ) accordingto Table 2) • When X = 2, C out = 1 if Y ≥ ( N I ( Y ) = 2 ) accordingto Table 2)Table III presents the transistor count for the half adders.Table IV presents the transistor count for different ternaryhalf adders proposed in the last ten years.III. T ERNARY F ULL A DDERS
When C in = 0, the full adder truth table was presented inTable 1 (half-adder).When C in = 1, the truth table is given inTable V. Fig. 4. Ternary Half AdderTABLE IIIT
RANSISTOR COUNT FOR THE T ERNARY H ALF A DDER
Still using the MUX approach, the SUM output of the fulladder is given by • If C in = 0, then SU M
F A = SU M HA else SU M
F A =( SU M HA + 1) mod (3) Another approach directly computes
SU M
F A as a functionof C in and X. • When X = 0: if C in = 0 then SUM = Y else SUM =(Y+1) mod (3). • When X = 1, if C in = 0 then SUM = (Y+1) mod (3) elseSUM = (Y-1) mod (3). • When X = 2, if C in = 0 then SUM= (Y-1) mod (3) elseSUM =Y. C out is the carry output when C in = 1: • When X = 0, C out = 1 if Y = 2 ( P I ( Y ) = 2 accordingto Table 2) • When X = 1, C out = 1 if Y ≥ ( N I ( Y ) = 2 accordingto Table 2) • When X = 2, C out = 1 TABLE IVT
RANSISTOR COUNT OF DIFFERENT HA S Ternary Half Adder [1] [2] [3] [4] New 2 PS New 1PSTransistor count 136 112 112 85 42 48TABLE VF
ULL ADDER TRUTH TABLE WHEN C in = 1 SUM CARRYX/Y 0 1 2 0 1 20 1 2 0 0 0 11 2 0 1 0 1 12 0 1 2 1 1 1 C in = 0 then C outF A = C outHA else C outF A = C out Fig. 5. Ternary Full Adder(version 1)Fig. 6. Ternary Full Adder (version 2)
Figure 5 and Figure 6 use two new different types ofMUXes: • MUXes with ternary inputs and binary control; • MUXes with binary inputs and binary control.Both types use the same typical MUX2 binary circuit (Figure7)
Fig. 7. Typical MUX2 with binary control)
Table VI presents the transistor counts for the two versionsof the ternary full adder with two power supplies. Table VIIprovides the same information for one power supply.Table VIII presents the transistor count for different ternaryfull adders proposed in the last decade.
TABLE VIT
RANSISTOR COUNTS FOR THEE TERNARY FULL ADDER (2 POWERSUPPLIES )Carry SUM V1 SUM V2 FA-V1 FA-V2SUCC- PRED 0 12 8MUX3 16 8 16MUX2 4 4 4PI-NI 0 24 16NOT 6 2 2TOTAL 26 50 46 76 72TABLE VIIT
RANSISTOR COUNTS FOR THE TERNARY FULL ADDER (1 POWER SUPPLY )Carry SUM V1 SUM V2 FA-V1 FA-V2SUCC- PRED 0 21 14MUX3 16 8 16MUX2 4 4 4PI-NI 0 24 16NOT 6 2 2TOTAL 26 59 52 83 78
IV. C
OMPARING WITH BINARY ADDERS
A. Binary Half Adder
Using the same MUX technique, the binary half-adder isshown in Figure 8. It uses 12 T. Permuting the MUX inputsand adding an output inverter would lead to 14 T with restoredoutput levels. The transistor count is then the same as a typicalconventional approach used in standard cell libraries [10], asshown in Figure 9 .
Fig. 8. Binary Half Adder (MUX technique)
B. Binary Full Adder
With the MUX approach, the binary full adder is presentedin Figure 10. It corresponds to the following rules: • If C in = 0 then SU M
F A = X XOR Y else X NXORY. XOR and NXOR functions are implemented usingMUXes. • If C in = 0 then C out = X.Y else C out = X+Y.The MUX based full adder has 30 T. A version with restoredoutput levels would have 34 T. It could be outlined that TABLE VIIIT
RANSISTOR COUNT OF DIFFERENT TERNARY FA S Ternary Full Adder [5] [6] [7] ProposedTC (2 power supplies) 106 132 72TC (1 power supply) 142 78 ig. 9. 14 T binary Half Adder) the MUX approach has more transistors than the typicalconventional full adder with complementary CMOS shown inFigure 11. Many proposals using less than 28 T have beenproposed in the literature. Fig. 10. Binary Full Adder (MUX technique)Fig. 11. 28 T binary Full Adder)
V. C
ONCLUSION
The proposed ternary half adders and full adders have lesstransistors than all the previously proposed ones. It seems thatthe MUX approach with successor and predecessor circuitsis the best one to implement ternary arithmetic circuits. Itlooks like the transistor counts are close to the minimalpossible value. The only valid comparison between ternary andbinary circuit is based on the information ratio. According toShannon theory of information, when N events have the sameprobability to occur, the corresponding amount of informationis I = log ( N ) bits (or Shannon). When N = 2, I = 1 bit.When N = 3, I = 1.585 bits. A ternary wire carries 1.585times the amount of information of a binary one. This 1.585information ratio must be used to compare binary and ternarycircuits. For instance, an 8-bit binary adder can be comparedto a 5-trit ternary adder as they process approximately thesame amount of information. 8/5 is close to 1.585. Thedifference results from rounding issues. Considering the mostconservative implementation of binary circuits, the transistorcount ratio between ternary and binary half adder is 42/14= 3 and 72/28 = 2.57 for the full adder when using twopower supplies for the ternary case. With only one powersupply, the ratios are respectively 48/14 = 3.4 and 78/28 =2.8. Both ratios are greater than 1.585. It means that the bestternary implementation leads to more transistors, more chiparea, more interconnects and more power dissipation than thecorresponding conservative binary ones. These results are notsurprising. 3 is not the best base for computation [11] andmultivalued circuits are restricted to a small niche [12].R EFERENCES[1] S. Lin, Y-B. Yin and F. Lombardi, “CNTFET-Based Design of TernaryLogic Gates and Arithmetic Circuit", IEEE Transactions on Nanotech-nology, Vol 10, N o
11] D. Etiemble, “Ternary circuits: why R = 3 is not the Optimal Radix forComputation", August 2019, arXiv:1908.06841 [cs.AR],[12] D. Etiemble, “Why M-Valued Circuits are restricted to a Small Niche”,in Journal of Multiple Valued Logic and Soft Computing, Vol. 9 , N o1,2003.