Compact Device Models for FinFET and Beyond
Darsen D. Lu, Mohan V. Dunga, Ali M. Niknejad, Chenming Hu, Fu-Xiang Liang, Wei-Chen Hung, Jia-Wei Lee, Chun-Hsiang Hsu, Meng-Hsueh Chiang
Compact Device Models for FinFET and Beyond
Darsen D. Lu , Mohan V. Dunga , Ali M. Niknejad , Chenming Hu , Fu-Xiang Liang , Wei-Chen Hung , Jia-Wei Lee , Chun-Hsiang Hsu , Meng-Hsueh Chiang National Cheng Kung University, Tainan, Taiwan R.O.C. SanDisk Corporation, Milpitas, CA, USA University of California, Berkeley, CA, USA E-mail: [email protected]
Abstract
Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.
Keywords
Compact models, FinFET, RRAM, neuromorphic, deep learning.
1. Introduction
The concept of compact device models exist since SPICE [1] was introduced to the world about than 40 years ago. Compact device models, or compact models, consist of a set of analytical expressions that can be as simple as Ohm’s Law for the current-voltage relationship of an ideal resistor, or a significantly larger set of expressions and more than 100 model parameters for the case of state-of- the-art MOSFET compact models such as BSIM4 [2]. The evolvement of compact model development is strongly tied to device technology. The FinFET technology has been introduced in 1999 [3] and started to become mainstream CMOS about a decade later [4]. BSIM-CMG [5], a compact model for common multi -gate MOSFET transistor, was introduced and selected as industry standard FinFET model in 2012 in anticipation for the technology change. With the rapid growth of semiconductor technology, a wide range of new electronic device have emerged, such as tunneling FET, negative capacitance FET for CMOS, resistive memory (RRAM), phase change memory (PCM) for non-volatile memory, and organic thin- film transistors (OTFT) for display technology and RFID’s. The Verilog-A language [6] has facilitated the quick development of compact models for these new devices, such as those published on the NEEDS online platform [7]. The availability of compact models for many new devices facilitates the evaulation of new circuit applications for emerging technologies. One such application is the design of neuromorphic circuits and systems with emerging non- volatile memory devices, such as RRAM, PCM, spin-torque transfer magnetic memory (STT-MRAM) and ferroelectric memory (FeRAM). We may use emerging memory compact models to perform neuromorphic simulation in the circuit and system level. This allows us to link fundamental device characteristics to the performance of artifical neural network implemented using neuromorphic circuits – a proimsing future direction for artificial intelligence (AI) systems. In this paper, we first introduce BSIM-CMG and BSIM- IMG, focusing on their surface-potential-based model formulation and versatile modeling capability to cover many different multiple-gate devices. Subsequently, we discuss compact models for emerging memory devices, using RRAM compact model as an example [8]. We have successfully applied it to simulate simple neuromorphic systems. On-going work is to build a neuromorphic simulation platform that links the characteristics of any novel memory devices to the energy consumption, computational speed and throughput, as well as classification accuracy of future AI systems based on novel memory devices.
2. Multiple-Gate MOSFET Compact Modeling
As CMOS scaling has reached sub -50nm technology nodes, control of short channel effects becomes extremely difficult. The introduction of High-K and metal gates allowed continued scaling for about two more generations [9]. Further scaling had required multiple-gate MOSFET, which included thin -BOX FD- SOI [10] (Fig. 1(a)) and FinFET (Fig. 1(c)(d)) devices. The former is modeled by BSIM- IMG, where the double-gate structure is considered and the front- and back- gate stacks are allowed to be asymmetric; the latter is modeled by BSIM-CMG, where the two sides of the double-gate structure is assumed to be symmetric. Even though BSIM -IMG is originally designed for planar FD-SOI with back-gate, it can also be used to model independent-gate FinFETs (Fig. 1(b)). BSIM-CMG may also be used to model nanowire MOSFETs (Fig. 1(e)) and vertical transistors (Fig. 1(f)). Both BSIM- IMG and BSIM-CMG are modeled using surface-potential-based formulations. For example, BSIM- CMG starts from the very basic Poisson’ s equation considering inversion electrons and body doping: ( ) ( ) ( ) ( ) ,2 2 , B ch q x y V yi AkTSi Si x y qn qNex ψ φ ψ ε ε − − ∂ = ⋅ +∂ (1) where V ch is the channel potential, which varies from 0V at the source end to drain- to-source voltage V ds at the drain end, and N A is the body doping concentration. Even with several simplifying approximations, the solution to (1) for a given V ch is still an implicit expression which takes the following form: = s f ψ (2) where ψ s is the surface potential, the potential at the surface of the MOSFET. Third order Householder’ s method is applied to express ψ s as an explicit function of boundary conditions such as the gate voltage V g . Such approximation has worked very well for most N A values and geometry such as body thickness ( T si ) except for extreme values of N A and geometry. Subsequently, drain current ( I d ) and terminal charge ( Q s , Q d , and Q g ) are derived as explicit function of ψ ss ( ψ s at the transistor source terminal) and ψ sd ( ψ s at the transistor drain terminal). The complete expression for I d is as follows: dsiBSitBtSititoxid QQCVQVCVQVCQLWI +++−+= )5ln()5(22 µ (3) where ( ) Bdssfbgoxdis
QVVCQ −−−= )()( ψ (4) siAB TqNQ = (5) For details of the derivations for I d and complete C-V expressions, one may refer to [5]. In addition to the aforementioned core (long- channel) I d and charge models, BSIM-CMG consists of a number of models for real device effects, such as field -dependent mobility, velocity saturation, source velocity limit, parasitic resistances and capacitances, leakage currents, etc. The overall model is evaluated against BSIM4 in terms of computational efficiency (Fig. 2). It was shown that the surface-potential-based BSIM-CMG has similar speed compared to V th -based BSIM4 model, which has been widely applied to real-world circuit design. (a) (b) (c) (d) (e) (f) F i g . 1 M u l t i p l e - g a t e D e v i c e Ty p e s c o v e r e d b y B S I M- C M G a n d B S I M - I M G . ( a ) B a c k - g a t e d U T B - S O I M O S F E T a n d ( b ) i n d e p e n d e n t - g a t e F i n F E T d e v i c e s a r e m o d e l e d b y B S I M - I M G , w h e r e a s ( c ) S O I a n d ( d ) b u l k F i n F E T, ( e ) nanowire FET and vertical pillar FET’ s are modeled by BSIM- CMG. FGBG
S D
The derivation for BSIM-IMG follow similar surface-potential-based approach. However, the asymmetric front- and back-gate stacks complicates the calculation of surface potential, I d and charge. Details of model derivation is available in [11]. BSIM-IMG has been validated against various thin- BOX fully-depleted SOI technology with excellent agreements, e.g. [12].
3. RRAM Compact Modeling
Compact modeling techniques can also be applied to memory devices. In Verilog-A and the SPICE environment, memorization of the system state is done by either: 1.
Storing information in a real-valued variable in Verilog-A. 2.
Representing the system state using the voltage of an extra node. Typically, the latter is preferred since the life cycle of Verilog- A variables is not well-defined across all simulation platforms. In fact, i n BSIM models, history-dependent phenomenon such as self- heating and floating body effect are modeled by introducing the temperature node and the floating- body node, respectively [13]. Similarly, for modeling RRAM characteristics, an R-C network is introduced to model the time-dependent RESET process [8]. Fig. 3(a) illustrates the typical bipolar- switching RRAM I- V characteristics as generated using transient SPICE simulation. The model parameters were calibrated to an HfO -based RRAM technology [8]. Fig. 3(b) illustrates the 1-transistor- 1-RRAM (1T1R) circuit block, which is often used in memory arrays for F i g . 2 E v a l u a t i o n r e s u l t s f o r c o m p u t a t i o n a l e f f i c i e n c y o f a v a r i e t y o f Ve r i l o g - A m o d e l s ( B S I M 4 a n d B S I M - C M G ) a n d s u r f a c e p o t e n t i a l c a l c u l a t i o n o p t i o n s . “ S P - d o p e d , ” “ S P- u n d o p e d ” a n d “ S P- p i l l a r ” r e f e r t o t h e s t a n d a r d s u r f a c e p o t e n t i a l ( S P ) c a l c u l a t i o n c o n s i d e r i n g d o p e d b o d y, s i m p l i f i e d S P c a l c u l a t i o n a s s u m i n g l i g h t l y - d o p e d b o d y, a n d S P c a l c u l a t i o n f o r c y l i n d r i c a l g e o m e t r y, r e s p e c t i v e l y [ 5 ] . Basic Features Ig and GIDL Rgate C o m pu t a t i on T i m e ( µ s ) BSIM4 BSIM-CMG (SP-doped) BSIM-CMG (SP-undoped) BSIM-CMG (SP-pillar) ( a ) ( b ) ( c ) F i g . 3 S i m u l a t i o n r e s u l t s f o r Ve r i l o g - A b a s e d R R A M c o m p a c t m o d e l [ 8 ] : ( a ) S E T - R E S E T I - V c h a r a c t e r i s t i c s ( b ) S i m u l a t i o n s e t u p f o r t h e 1 T- 1 R c i r c u i t ( c ) I l l u s t r a t i o n o f c o nt i n u o u s c o n d u c t a n c e t u n i n g w i t h v a r i o u s S E T c o m p l i a n c e c u r r e n t , o r M O S g a t e v o l t a g e d u r i n g S E T o p e r a t i o n . (Vpos=1.0V for SET operation) V g 𝑉 𝑝𝑜𝑠 = 0.1vReRAM Conductance Range V pgm (V) better isolation. This is as opposed to the cross-bar array, which can cause unwanted leakage across unselected cells. Fig. 3(c) illustrates the continuous resistance tuning simulation. The RRAM is initially at the RESET state with high resistance. V pgm is the voltage applied to the transistor gate terminal for programming (or SET operation, V pos =1.0V). I read is the resulting RRAM current during read ( V pos =0.1V). The fact that RRAM conductance can be continuously varied over a wide range makes it attractive as candidate for neuromorphic circuit design, wherein the RRAM conductance represents the synaptic weights in neural networks.
4. Neuromorphic Circuit Design with RRAM
The compact model for RRAM is applied to the design of neuromorphic circuits [14] . Fig. 4 shows the array configuration considered in this study. Since the conductance of RRAM is always positive, we take the conductance difference between two RRAM devices as the weight of the synapse in question [15]. The input pattern (fixed voltage or pulse train with varying numbers and durations) is passed on horizontal (word ) lines; the output current is taken at vertical (bit) lines, with amplification circuitry at each bottom end to read out information and providing virtual ground. We have successfully applied this circuit configuration and offline backward-propagation supervised learning algorithm to train a 3x1 neural network to reproduce the “ AND” logic operation, as demonstrated in SPICE [14]. The activation function is implemented offline with software.
5. Floating-gate Based Neuromorphic Circuits and System Level Simulations
Neuromorphic circuit may also be designed with different types of memory devices. Essentially, this allows us to avoid separation of computation (such as the CPU in today’s computer systems) and storage (such as DRAM), which is very often the bottleneck for computational throughput. The use of non- volatile memory also eliminates the requirement to load programs into memory during each execution. We may use, for example, the conventional flash memory device as synaptic devices [16]. (a) (b) (c) F i g . 5 S i m u l a t i o n o f a n o v e l f l o a t i n g - g a t e s y n a p t i c t r a n s i s t o r. ( a ) D e v i c e s t r u c t u r e w i t h s e p a r a t e n e g a t i v e f e e d b a c k g a t e ( n f b ) f o r p r o g r a m m i n g a n d s y n a p t i c g a t e ( s g ) r e a d o u t . ( b ) E q u i v a l e n t c i r c u i t d i a g r a m f o r c o m p a c t m o d e l i n g (c ) S i m u l a t i o n r e s u l t s w i t h i l l u s t r a t e d w e i g h t ( d r a i n c u r r e n t ) w e a k e n i n g a f t e r n e g a t i v e f e e d b a c k p u l s e a n d w e i g h t s t r e n g t h e n i n g a f t e r p o s i t i v e f e e d b a c k ( p f b ) p u l s e . fg pfb nfb sg d nfb pfbdsg fg time (sec) nfb (V) pfb (V) fg (V). M1 Gate current sg (V)
Output ("d") current
F i g . 4 R R A M -based neuromorphic array. Each synapse of the neural network consists of two RRAM device, whose conductance difference represents synaptic weight [15]. The input pattern (voltage value or pulse train) is passed on word lines; the output current is taken at bit lines, with amplification circuitry to reading out information and providing virtual ground.
A A2 devices per synapseInputpattern
Fig. 5 shows the simulation of a floating- gate synaptic transistor. As illustrated in Fig. 5(a), this special floating-gate device has separate programming terminals (negative feedback, “ nfb” and positive feedback, “pfb”) and synaptic gate (“ sg”). This allows the synaptic gate to be always connected to the input, without the need of complicated switches to separate programming mode and read mode. The expected drawback is the reduction in coupling ratio, or charge sharing, which reduces the strength of “ sg.” Fig. 5(b) shows the sub- circuit for implementing this new floating- gate memory device. No extra Verilog- A code is required other than the modification of existing MOS models (a simplified version of BSIM model for use in coursework) to include Fowler-Nordheim (FN) tunneling. Even though we use FN tunneling for this example, hot carrier programming is also viable to achieve faster speed. Fig. 5(c) illustrates SPICE simulation results. The output (drain) current, which represents the weight for neural networks, can be enhanced or reduced depending on the pulse applied to the programming terminals. Even though compact model, after calibration against experimental data, is a very accurate representation of the DC and time-dependent behavior of electronic devices, there is a limit to the number of transistor that can be included in each simulation. The maximum number of elements that can be handled with conventional SPICE is on the order of 100,000. For the typical MNIST [17] database which consists of 60,000 training sample with 28x28 handwritten digit images (784 input pixels, each with 256 levels), an estimated 228,500 synapses is required. Simulation such large circuits with 60,000 or more training cycles is beyond imagination, not to mention larger databases such as ImageNet [18] . One solution is to use FastSPICE, for which the number of elements that can be handled is on the order of 10,000,000. The other solution is to develop a dedicated neuromorphic simulation platform. NVMLearn is one example of such neuromorphic simulation platform which accounts for component level characteristics as represented by Verilog-A code, but is scalable to large deep learning problems [19]. We have tested NVMLearn on 784x1000x125x10 fully -connected neural network, with 94.3% accuracy achieved for MNIST handwritten digits recognition. Further enhancement of recognition accuracy may require convolutional neural networks, which is part of future work.
6. Conclusions
The Verilog-A programming language has allowed fast implementation of compact models for logic, memory devices, and beyond. Industry standard BSIM-CMG and BSIM- IMG models are developed using the surface-potential-based framework, without sacrificing computational efficiency, to model FinFET and back- gated FDSOI technologies. RRAM and floating- gate transistor compact models have also been developed for future neuromorphic applications. Continuous tuning of RRAM conductance and floating- gate current levels makes these device viable for representing the analog weights of neuromorphic circuits. To link fundamental device characteristics to system level energy, speed, and pattern recognition accuracy, a new neuromorphic simulation platform, NVMLearn, is being developed for large scale non-volatile-memory-based neural networks.
Acknowledgements
The authors would like to express sincere gratitude to Chip Implementation Center (CIC), Hsinchu, Taiwan for providing SPICE simulation environment for RRAM simulations.
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