Correct-by-design Control Synthesis for Multilevel Converters using State Space Decomposition
Gilles Feld, Laurent Fribourg, Denis Labrousse, Bertrand Revol, Romain Soulat
SS.-W. Lin and L. Petrucci (Eds.): 2nd French SingaporeanWorkshop on Formal Methods and ApplicationsEPTCS 156, 2014, pp. 5–16, doi:10.4204/EPTCS.156.5 c (cid:13)
G. Feld, L. Fribourg, D. Labrousse, B. Revol & R. SoulatThis work is licensed under theCreative Commons Attribution License.
Correct-by-design Control Synthesis for MultilevelConverters using State Space Decomposition
Gilles Feld
SATIE, ENS Cachan & CNRS, France
Laurent Fribourg
LSV, ENS de Cachan & CNRS, France
Denis Labrousse
SATIE, ENS Cachan & CNRS, France
Bertrand Revol
SATIE, ENS Cachan & CNRS, France
Romain Soulat
LSV, ENS de Cachan & CNRS, France
High-power converters based on elementary switching cells are more and more used in the industryof power electronics owing to various advantages such as lower voltage stress and reduced powerloss. However, the complexity of controlling such converters is a major challenge that the powermanufacturing industry has to face with. The synthesis of industrial switching controllers relies todayon heuristic rules and empiric simulation. The state of the system is not guaranteed to stay withinthe limits that are admissible for its correct electrical behavior. We show here how to apply a formalmethod in order to synthesize a correct-by-design control that guarantees that the power converterwill always stay within a predefined safe zone of variations for its input parameters. The methodis applied in order to synthesize a correct-by-design control for 5-level and 7-level power converterswith a flying capacitor topology. We check the validity of our approach by numerical simulations for 5and 7 levels. We also perform physical experimentations using a prototype built by SATIE laboratoryfor 5 levels.
Switched control has gained much attention recently due to its property of being easily implemented,especially in the field of power converters. Power converters play an important role in the field of re-newable energy: they are used to connect renewable sources to powergrids, optimize the efficiency ofsolar panels and wind generators (see, e.g., [1]). In some topologies, there is however a dramatic increaseof the number of switches, which entails an increasing number of degrees of freedom, and complicatesthe controller design . There is therefore a niche of application for formal methods in order to producecorrect-by-design control methods. The general function of a multilevel power converter is to synthe-size a desired voltage from several levels of DC voltage. For this reason, multilevel power converterscan easily provide the high power required by large electric drive systems. A multilevel converter is apower converter made of capacitors and switching cells (as well as opposite switching cells which are incomplementary positions);In this paper, we consider the design of control policies for power converters with a number of levels (cid:96) = (cid:96) =
7. A multilevel converter for (cid:96) = Correct-by-design control synthesis for multilevel converters
Figure 1: Electrical scheme of a 5-level flying capacitor converterFigure 2: Staircase output voltage waveform for a 5-level converterrange defined by the device blocking voltage rating. The control must thus guarantee a safety property ,called “capacitor voltage balancing”: the voltage of each individual capacitor should stay inside a limitedpredefined interval. The synthesis of industrial switching controllers relies today on heuristic rules andempiric simulation. The state of the system is not guaranteed to always satisfy capacitor voltage bal-ancing. In this paper, we show how to synthesize a control, by applying a formal method, called statespace decomposition procedure [4]. The synthesized control is “correct-by-design” because it is ensuredto make the electrical state parameters of the system stay within predefined safe zones of variations. Nu-merical simulations, performed at levels (cid:96) = ,
7, confirm the safety properties of the synthesized control.Physical experimentations are also successfully performed on a prototype built by SATIE ElectronicsLaboratory, at level (cid:96) = Outline of the paper
In Section 2, we present the principles of the state space decomposition method. In Section 3, we ap-ply the method in order to synthesize the control of multilevel converters with a flying capacitor topology,for 5 and 7 levels. In Section 4, we present physical experimentations done with a prototype of 5-levelconverter. We conclude in Section 5.
A multilevel converter can be seen as a “switched system”, where the different operating modes dependon the positions of the switching cells. In this section, we describe a general method that is useful forproving properties of switched systems. The method will be subsequently applied to multilevel convertersin Section 3. . Feld, L. Fribourg, D. Labrousse, B. Revol & R. Soulat A switched system Σ is defined by a finite family of differential equations of the form { ˙ x = f u ( x ) } u ∈ U where U is a finite set of modes (see, e.g., [5, 14]). In the following, we consider that the dynamicsof the subsystems are affine (i.e., f u ( x ) is of the form A u x + b u with A u ∈ R n × n and b u a vector of R n ).The control problem for a switched system Σ is to find a piecewise constant law u : R ≥ → U in order toachieve some pertained goals. The switching instants are the times at which u changes its value. An affinesampled switched system is a switched system for which the switching instants occur at integer multiplesof τ (called sampling parameter ). We will use x ( t , x , u ) to denote the point reached by Σ at time t undermode u from the initial condition x . This gives a transition relation → τ u defined for x and x (cid:48) in R n by: x → τ u x (cid:48) iff x ( τ , x , u ) = x (cid:48) . Given a set X ⊂ R n , we define: Post u ( X ) = { x (cid:48) | x → τ u x (cid:48) for some x ∈ X } . It can be seen that
Post u ( X ) is the result of an affine transformation of the form C u X + d u with C u ∈ R n × n and d u a vector of R n .A pattern π is defined as a finite sequence of modes. A k-pattern is a pattern of length at most k . Themapping Post π is itself an affine transformation.Given a pattern π of the form ( u · · · u m ) , and a set X ⊂ R n , the unfolding of X via π , denoted by Unf π ( X ) , is the set (cid:83) mi = X i with: • X = X , • X i + = Post u i + ( X i ) , for all 0 ≤ i ≤ m − π to the states of X . A safety property is typically expressed using a subset S of the continuous state space, called safe set .In a simple formulation, S is a box , i.e., a cartesian product of intervals that specify the minimum andmaximum values tolerated for each state component. Given a safe set S , and a domain of interest R ⊆ S ,we can define the notion of “safe control” in this context as follows. Definition 1
Given a domain of interest R and safe set S with R ⊆ S, a safe control of R w.r.t. S is afunction that associates to each x ∈ R a pattern π such that: • Post π ( { x } ) ⊆ R, and • U n f π ( { x } ) ⊆ S. Given a domain of interest R and a set S with R ⊆ S , the safety control problem consists in finding asafe control of R w.r.t. S . In [4], in order to solve such a problem, we introduced the notion of “(safe)decomposition”. Definition 2
Given a set R ⊂ R n and a set S with R ⊆ S, a safe decomposition of R w.r.t. S is a set ∆ ofthe form { V i , π i } i ∈ I , where I is a finite set of indices, V i s are subsets of R, π i s are k-patterns, such that: • (cid:83) i ∈ I V i = R, • for all i ∈ I: Post π i ( V i ) ⊆ R, and • for all i ∈ I: U n f π i ( V i ) ⊆ S. Correct-by-design control synthesis for multilevel converters
A decomposition ∆ = { ( V i , π i ) } i ∈ I naturally induces a state-dependent control on R . Furthermore, thecontrolled trajectories starting from R never leave S . Indeed, given a starting state x in R , we know that x ∈ V i for some i ∈ I (since R = (cid:83) i ∈ I V i ); one thus applies π i to x , which gives a new state x that belongsitself to R (since Post π i ( V i ) ⊆ R ); furthermore, since U n f π i ( V i ) ⊆ S , all the intermediate states producedby application of π i are guaranteed to belong to S . The process can then be repeated on x , and so oniteratively. Formally, we have: Proposition 1
Suppose that ∆ is a safe decomposition of R w.r.t. S. Then the control of R induced by ∆ issafe w.r.t S. The problem of finding a safety controller thus reduces to the problem of finding a safe decomposition ∆ .The latter problem can be solved by using the state space decomposition method [4], as explained below. We give here a simple algorithm, adapted from [4], called Decomposition algorithm. Given a set R anda set S with R ⊆ S , the algorithm outputs, when it succeeds, a decomposition ∆ of R w.r.t S , of the form { V i , π i } i ∈ I . The input sets R and S are given under the form of boxes of R n (i.e., cartesian productsof n closed intervals). The subsets V i s of R are boxes that are obtained by repeated bisection. At thebeginning, the Decomposition procedure calls sub-procedure Find Pattern in order to get a k -pattern π such that Post π ( R ) ⊆ R and U n f π ( R ) ⊆ S . If it succeeds, then it is done. Otherwise, it divides R into 2 n sub-boxes V , . . . , V n of equal size. If for each V i , Find Pattern gets a k -pattern π i such that Post π i ( V i ) ⊆ R and U n f π i ( V i ) ⊆ S , it is done. If, for some V j , no such pattern exists, the procedure is recursively appliedto V j . It ends with success when a safe decomposition of R w.r.t. S is found, or failure when the maximaldegree d of decomposition is reached. The algorithmic form of the procedure is given in Algorithms 1and 2. (For the sake of simplicity, we consider the case of dimension n =
2, but the extension to n > W , R , S , D , K ) is called with R as input value for W , d for input value for D , and k as input value for K ; it returns either (cid:104){ ( V i , π i ) } i , True (cid:105) with (cid:83) i V i = W , (cid:83) i Post π i ( V i ) ⊆ R , (cid:83) i U n f π i ( V i ) ⊆ S or (cid:104) , False (cid:105) . Procedure Find Pattern( W , R , S , K ) looks for a K -pattern π for which Post π ( W ) ⊆ R and U n f π ( W ) ⊆ S : it selects all the K -patterns by non-decreasing lengthorder until either it finds such a pattern π (output: (cid:104) π , True (cid:105) ), or none exists (output: (cid:104) , False (cid:105) ). Thecorrectness of the procedure is stated as follows.
Theorem 1
If Decomposition(R,R,S,d,k) returns (cid:104) ∆ , True (cid:105) , then ∆ is a safe decomposition of R w.r.t. S. In [4], we have developed a tool that implements the Decomposition procedure, using zonotopes [6],and is written in Octave [10]. We now describe the application of this tool, called MINIMATOR [9], forsynthesizing controllers of multilevel converters.
There are different possible topologies for multilevel power converters: neutral-point clamped, cascadedH-bridge, Modular Multilevel Converter (see e.g., [12, 2, 7, 8]). We focus here on the flying capac-itor topology [8]. The electrical scheme of a 5-level converter was given in Figure 1. There are 4pairs of switching cells S , S , S , S (the high-side switch conducting position is indicated by 1 andthe lowside switch conducting position by 0), and 3 capacitors C , C , C . The state of the system is x ( t ) = [ v ( t ) v ( t ) v ( t ) i ( t )] T where v j ( t ) is the voltage across C j (1 ≤ j ≤
3) and i ( t ) is the currentflowing in the circuit. The duration of a cycle is T = τ . The mode of the system is characterized by the . Feld, L. Fribourg, D. Labrousse, B. Revol & R. Soulat Algorithm 1:
Decomposition( W , R , S , D , K ) Input : A box W , a box R , a box S , a degree D of decomposition, a length K of pattern Output : (cid:104){ ( V i , π i ) } i , True (cid:105) with (cid:83) i V i = W , (cid:83) i Post π i ( V i ) ⊆ R and (cid:83) i U n f π i ( V i ) ⊆ S or (cid:104) , False (cid:105) ( π , b ) : = Find Pattern ( W , R , S , K ) if b = True then return (cid:104){ ( W , π ) } , True (cid:105) else if D = then return (cid:104) , False (cid:105) else Divide equally W into ( W , · · · , W n − ) for i = . . . n − do ( ∆ i , b i ) := Decomposition( W i , R , S , D − K ) return ( (cid:83) i = ... n − ∆ i , (cid:86) i = ... n − b i ) Algorithm 2:
Find Pattern( W , R , K ) Input : A box W , a box R , a box S a length K of pattern Output : (cid:104) π , True (cid:105) with
Post π ( W ) ⊆ R and U n f π ( W ) ⊆ S , or (cid:104) , False (cid:105) when no pattern maps W into R for i = . . . K do Π : = set of patterns of length i while Π is non empty do Select π in Π Π : = Π \ { π } if Post π ( W ) ⊆ R and U n f π ( W ) ⊆ S then return (cid:104) π , True (cid:105) return (cid:104) , False (cid:105) value (0 or 1) of the switching cells, i.e., by the value of vector S = [ S S S S ] T . There are thus 2 = S induces an output voltage v o of value Σ j = ( S j + − S j ) v j + S v high − ( − S ) v low , where v low and v high are the input voltages of low level and high level respectively. For the sake of simplicity, wesuppose: v high = v low = v input . The system then outputs 5 different levels of voltage which go from − v input up to + v input with steps at − v input , , v input . The ideal value v ∗ i of the voltage across capacitor C i (1 ≤ i ≤ v input . Here we use: v input = V , and v ∗ = V , v ∗ = V , v ∗ = V . The5-level converter can be seen as a switched system. Given a mode S , the associated dynamics is of theform ˙ x ( t ) = A S x ( t ) + b S with: A S = − R C S − S C − R C S − S C − R C S − S C S − S L Load S − S L Load S − S L Load − R Load L Load and b S = ( S − ) v input L Load
By controlling the modes at each sampling time, one can synthesize a 5-level staircase function. Notall the transitions between modes are admissible: we allow to switch only one (pair of) cell(s) at a time. Besides, we have: S = ¬ S , S = ¬ S , S = ¬ S and S = ¬ S . Correct-by-design control synthesis for multilevel converters
The graph of admissible transitions during a cycle is depicted in Figure 3. The nodes of the graph arelabeled by the modes. Each path represents a possible pattern for one cycle, leading from voltage − v input (mode 0000) to voltage + v input (mode 1111) through voltages − v input , 0, v input then back to voltage − v input (mode 0000) through voltages v input , 0, v input . There are thus 576 possible patterns for generating a 5-levelstaircase signal on one cycle.We explain in the following how to apply the tool MINIMATOR in order to find a safe decompositioninvolving these patterns. Figure 3: Transition graph corresponding to a cycle of 5-level staircase signal
We consider the following numerical values of the electrical parameters: v input = R Load = Ω , C = C = C = . L Load = . R = R = R = , Ω , T = τ = . s (which correspondsto a frequency of 50Hz).In this context, a 5-level converter outputs ideally a staircase waveform with an amplitude of 200V,centered around 0V. We consider that a variation of ± V is admissible as it represents a variation of10% on the least charged capacitor C . It is interesting to notice that at each beginning of a cycle thevalue of i is null. This suggest to look for a state-dependent control which depends only on the capacitorvoltages v , v , v , and not on the value of i . We will thus focus on the voltage dimensions of the controlbox R and disregard its intensity dimension. For R , we take R = [ , ] × [ , ] × [ , ] , whichcorresponds to a product of intervals centered around the ideal values with a variation of ± V (i.e., 10%of the least charged capacitor C ). For S , we take R + ε with ε = V , which means that we have anadditional tolerance of ± V for the fluctuations occurring between two beginnings of cycle.Given R = [ , ] × [ , ] × [ , ] and S = [ , ] × [ , ] × [ , ] , we perform theprocedure of Decomposition, implemented in MINIMATOR tool, on a machine equipped with an Intelcore2 CPU X6800 at 2.93GHz and with 2GiB of Ram memory. With parameters d = k =
8, theprocedure outputs in 60 seconds a decomposition ∆ = { ( V i , π i ) } i = ,..., with: • V = [ , ] × [ , ] × [ , ] • V = [ , ] × [ , ] × [ , ] • V = [ , ] × [ , ] × [ , ] . Feld, L. Fribourg, D. Labrousse, B. Revol & R. Soulat • V = [ , ] × [ , ] × [ , ] • V = [ , ] × [ , ] × [ , ] • V = [ , ] × [ , ] × [ , ] • V = [ , ] × [ , ] × [ , ] • V = [ , ] × [ , ] × [ , ] and • π : ( → → → → → → → → ) • π : ( → → → → → → → → ) • π : ( → → → → → → → → ) • π : ( → → → → → → → → ) • π : ( → → → → → → → → ) • π : ( → → → → → → → → ) • π : ( → → → → → → → → ) • π : ( → → → → → → → → ) By Proposition 1, the control of R induced by ∆ is safe w.r.t. S : under the control induced by ∆ , allthe trajectories starting from R always stay in S . This guarantees that the property of capacitor voltagebalance is satisfied. We present in Figures 4 and 5 a numerical simulation of this controller on the systemstarting from the point v ( ) = V , v ( ) = V , v ( ) = V and i ( ) = − A . This simulation hasbeen performed using tool PLECS [11]. One can check on the simulation that the system state alwaysstays inside S . We now consider the case of an (cid:96) -level converter with (cid:96) =
7. There are now 6 pairs of switching cellsand 5 capacitors C , . . . , C . The state of the system is x ( t ) = [ v ( t ) v ( t ) v ( t ) v ( t ) v ( t ) i ( t )] T where v j ( t ) is the voltage across C j (1 ≤ j ≤
5) and i ( t ) is the current flowing in the circuit. The generatedwaveform now goes from − v input up to + v input with steps at − v input , − v input , 0, v input , v input , and thecycle duration is T = τ . There are now 518 ,
400 possible patterns for generating an 7-level staircasesignal on 1 cycle. We used the following values for the system constants: output at 50Hz, capacitancesof 0 . F , resistor values 50 Ω , inductor values 0 . H , v input = V . Ideally, the output is thus a staircasewaveform with an amplitude of 600V, centered around 0V, and the ideal values v ∗ i of the capacitor voltagesof the capacitor C i are given by: v ∗ = V , v ∗ = V , v ∗ = V , v ∗ = V , v ∗ = V . For R , wetake R = [ , ] × [ , ] × [ , ] × [ , ] × [ , ] , which corresponds to a product ofintervals centered around the ideal values with a variation of ± V (i.e., 5% of the least charged capacitor C ). For S , we take R + ε with ε = V , which means that we have an additional tolerance of ± V forthe fluctuations occurring between two beginnings of cycle. On the same machine as in Section 3.2, withparameters d = k =
12, MINIMATOR outputs in 98 minutes a decomposition ∆ which is safe w.r.t. S . See [3] for more details.We present in Figures 6 and 7 a numerical simulation of the controlled system starting from the point v ( ) = V , v ( ) = V , v ( ) = V , v ( ) = V , v ( ) = V and i ( ) = − . A . One cancheck again on the simulation that the system state always stays inside S .It is difficult to perform experiments with (cid:96) greater than 7 with the present implementation. Thecomplexity of the state decomposition procedure is indeed exponential in the number (cid:96) of levels. We arepresently implementing MINIMATOR on a parallel computing architecture (see [9]) in order to increasethe tractable number of levels. which corresponds to T = τ = . s Correct-by-design control synthesis for multilevel converters (a) Voltage v = f ( t ) (b) Voltage v = f ( t ) (c) Voltage v = f ( t ) (d) Projection in plane ( v , v ) (e) Projection in plane ( v , v ) (f) Projection in plane ( v , v ) Figure 4: Capacitor voltages‘ (a) Current i (b) Output voltage v o Figure 5: Current and output voltage
A prototype of the 5-level flying capacitor has been realized by the SATIE Laboratory in order to test ourcontrol strategy on an actual system. See Figure 8 for a picture of the prototype. Our control strategywas applied to the system via Simulink and a dSpace R (cid:13) interface. The results are presented in Figure 9for the output voltage and the capacitor charges. In Figure 10, we present the same results but with alarger scale on the capacitor voltage to see the fluctuations around the reference values. As we can see,the experimental results are very closed to those obtained by simulation with PLECS of Section 3.2. InFigure 11, we represent the output voltage together with the current (after appropriate resizing) flowingthe load. During the experimentations, we have successfully tested the robustness of the controller inpresence of the following perturbations: . Feld, L. Fribourg, D. Labrousse, B. Revol & R. Soulat (a) Current i (b) Voltage v o Figure 7: Current and output voltage1. The ideal voltage source as input is no longer ideal but its values fluctuate around the referencevalue.2. We use a time-varying period T of cycle (instead of a constant one), and check the preservation ofthe capacitor voltages balance. The result of this experiment is depicted in Figure 12.Although these preliminary tests of robustness are promising, they need to be consolidated, in partic-ular in presence of significant variations of resistor loads. We have synthesized a control strategy for a 5-level and a 7-level flying capacitor converters using themethod of state space decomposition. This control is state-dependent and is interesting because: • at each electrical cycle, the controller indicates all the subsequent switching modes needed to pro-duce one period of the output voltage (instead of just the next switching mode), • the controller takes into account only the capacitor voltages state and not the intensity state; this isinteresting because for practical applications, a current sensor is not always desired (see [2]).4 Correct-by-design control synthesis for multilevel converters
Figure 8: Prototype built by SATIEFigure 9: Output voltage (above in green) and capacitor voltages (below)Figure 10: Zoom of output voltage (above) and capacitors voltages (below)We have checked by numerical simulations and physical experimentations that the control satisfies thecapacitor voltage balancing and the staircase shape of the output voltage. We have also checked therobustness of the method with respect to several sources of perturbation. . Feld, L. Fribourg, D. Labrousse, B. Revol & R. Soulat T The method can be easily refined in order to generate sinusoidal-like output signals rather than thetriangular-like output signals generated here: it suffices to adjust the switching instants within the period T of the cycle, instead of using uniformly τ .The method can be applied in principle to any number of levels for the flying capacitor topology.However, it suffers from an exponential increase of complexity when the level (cid:96) grows: the methodreaches its limit for (cid:96) =
9, which corresponds to a dimension n = (cid:96) = ,
7, the Decomposition procedure is well-suited to the flying capacitor topology: the patternlength input k is 2 × ( (cid:96) − ) where (cid:96) is the number of levels of the converter, and the depth input d is 1, which means that the decomposition is found after a single bisection. Note however that suchsimple decompositions of the state space do not necessarily exist for other topologies: for multilevelmodular converter toplogy [7], we had to propose in [13] a different and specialized algorithm whichtakes additionally into account the value of the intensity state.In future work, we plan to improve the robustness of the decomposition method for flying capacitortopology under variations of the resistive and inductive load. This will allow us to model the time-varyingload of electrical networks, which is a basic feature of electricity distribution, and a major challenge to-day for renewable-energy technologies. We are also implementing the tool MINIMATOR on a parallelcomputing architecture in order to synthesize correct-by-design controls for multilevel converters with agreater numbe (cid:96) of levels. Acknowledgement.
We are grateful to St´ephane Lefebvre for numerous helpful discussions. Wealso thank the anonymous referees for their constructive comments. This work has been done within the6
Correct-by-design control synthesis for multilevel converters framework of projects BOOST and BOOST2 supported by Institut Farman.
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