Data Freshness in Mixed-Memory Intermittently-Powered Systems
aa r X i v : . [ c s . I T ] F e b Data Freshness in Mixed-MemoryIntermittently-Powered Systems
James Scott Broadhead and Przemysław Pawełczak
Embedded and Networked Systems, EEMCS, Delft University of Technology, The NetherlandsEmail: { J.S.Broadhead, P.Pawelczak } @tudelft.nl Abstract —Age of Information (AoI) is a key metric to un-derstand data freshness in Internet of Things (IoT) devices. Inthis paper we analyse an intermittently-powered IoT sensor—with mixed-memory (volatile and non-volatile) architecture—that uses a Time-Dependent Checkpointing (TDC) scheme. Wederive the average Peak Age of Information (PAoI) and averageAoI of the system, and use these metrics to understand whichdevice parameters most significantly influence performance. Wego on to consider how the average PAoI of a mixed-memorysystem compares with entirely volatile or entirely non-volatilearchitecture, and also introduce an alternative TDC strategyto improve system resilience in unpredictable environmentalconditions.
I. I
NTRODUCTION
With an increasing paradigm shift towards battery-freeenergy harvesting-based design in low-powered embeddedsystems, new methods of operation have been developedto address the inherent intermittency of available harvestedenergy. Current intermittent computing techniques [1]–[5] seekto minimise the time and energy impact of power failure bystrategically checkpointing—effectively saving—the systemstate from Volatile Memory (VM) to Non-Volatile Memory(NVM) in mixed-memory systems [6] (such as the popu-lar Texas Instruments MSP430 micro-controller [1, Section3.1] [7, Section 2.1.1]). Whilst much work has been done todevelop new checkpointing strategies, there is still opportunityto better describe these systems mathematically [7, Section3.2.2], in particular from a data freshness perspective.A relevant metric to measure data freshness is the Ageof Information (AoI) [8]–[14], which will form the basis ofour analysis. We seek to model an Intermittently-PoweredDevice (IPD), implementing Time-Dependent Checkpointing(TDC) [15, Fig. 3], [16] where the VM system state is savedto NVM after a certain number of clock ticks have passed,and observe how fundamental system parameters (failure rate,checkpointing overhead, etc.) affect the freshness of locallysensed data. We also look to compare the mixed-memoryarchitecture of our IPD with single-type VM and single-typeNVM memory structures. We go on to introduce an alternativeTDC scheme, Split-Frequency Checkpointing (SFC), and con-sider how this can improve system resilience in unpredictableenvironmental conditions.Our work builds on [17] by accounting for the mixed-memory nature of many battery-free devices and the check-pointing schemes used to move data between memory types.To the best of our knowledge, this is the first evaluation and
Sense Processing
Volatile Memory
Checkpointed Device State
Non-Volatile Memory
TransmitCheckpoint Restoration
Figure 1. System model for an IPD that checkpoints its internal systemstate to protect from data corruption. The device performs sensing, on-boardprocessing (that takes P i clock ticks to complete), and transmission. Sensingand transmission occur instantaneously. Data stored in VM is checkpointedto NVM taking D i clock ticks, and system state restoration from NVM toVM takes V i clock ticks. The system suffers frequent power failures. comparison of AoI in IPDs with mixed-memory architecture.The efficiency of TDC has been considered in other areasof research, notably for distributed stream processing [18](which looked to minimise system utilization) and also inHigh Performance Computing (HPC) applications [19] (whichused wall-clock length as the objective). However, this form ofcheckpointing has not been analysed for transiently-operatingembedded devices, or with system freshness as the core tenetof consideration—which forms the premise of our work.In this paper we identify the average Peak Age of Infor-mation (PAoI) and average AoI for an IPD that uses TDC.These results allow us to better understand the role of mixed-memory architecture in IPDs and how the inter-checkpointingtime can be best adjusted to minimise AoI. We also show thatmixed-memory architecture can improve the system freshnessof an IPD compared with single-type VM, however it cannotsurpass entirely NVM architecture. We further show that SFCcan improve system performance in unpredictable environmen-tal conditions compared to inappropriately assigned single-frequency checkpoint intervals.II. S YSTEM M ODEL
We consider a communication device, presented in Fig. 1,which is powered by an intermittent energy source (sun,vibrations, temperature gradient, etc.) and consequently suf-fers frequent power failure. The device has mixed-memoryarchitecture (VM and NVM) and checkpoints the system state(processor registers, hardware registers, main memory, etc.)from VM to NVM after a fixed number of clock ticks, whereclock ticks act as a base unit for the system’s on-boardclock. The sensed data is then processed and transmitted,e.g. wirelessly through a low-powered LED [7], to a centralcollecting unit. acket Generation/Sensing.
Packets containing data froman on-board sensor are produced as required in a generate-at-will type policy—where sensing only occurs when processingof the preceding packet is complete—as considered in [17].We assume that sensing is instantaneous and that this data isthen immediately processed, from which a packet is created.Packets are not dropped due to power failure, since the lastcomputation state can always be restored from NVM to VM.
System Operation.
Data processing occurs in the volatilememory of Fig. 1 and encompasses a number of possible steps;such as peripheral control, filtering, and packet framing. Toreduce unnecessary system complexity we have considered allprocessing as one stage that takes P i clock ticks to complete.The time between data sensing and packet transmission, the completion time , is S i clock ticks and the time betweentwo sequential packet transmissions, the inter-completion time ,is Y i clock ticks, where the idle time between a packettransmission and the next generated packet is I i clock ticks. System Failure.
IPDs suffer frequent power failures dueto a lack of available harvested energy. We do not explicitlyconsider energy as part of our system model, as in [9, SectionV], [17], [20], rather assuming that the depleted energy willcause a number of random power failures. An amount ofprocessing time L i,j clock ticks, where the i represents theoverall cycle number and j the fail number within the cycle,will be wasted for each fail (since the updated system stateincluding this processing has not been checkpointed from VMto NVM before failure). Our system will also be inactive for aperiod of R i,j clock ticks after failure. During power failure nonew data is generated since the device cannot perform sensing.Once power is restored the system takes V i,j clock ticks torestore the last checkpointed system state from NVM to VM.For simplicity of analysis we assume that V i, = V i,j = V forall j . In practice this term would likely be fixed by design. Checkpointing Strategy.
The system will save the currentdevice state stored in VM to NVM with a pre-determinedregularity. This inter-checkpoint time is given by K i,n clockticks where n is the checkpoint number within cycle i . Theaction of checkpointing will also take a fixed amount of D i,n clock ticks to complete. Here, for simplicity of analysis, weassume that D i, = D i,n = D for all n . This is consistent with,for example, [15, Fig. 3]. We also assume that P i is a multipleof the inter-checkpointing time. Transmission.
Our model considers the transmissions ofpackets to be instantaneous and occurring after a final check-point. III. A
GE OF I NFORMATION B ACKGROUND
Let us now re-introduce several previously derived resultsthat form the basis of our analysis. Canonically we define AoIas [17, Eq. (1)] [9, Section II] ∆ ( t ) = t − u ( t ) , (1)where ∆ ( t ) is the AoI of data sensed by the device, t is thecurrent time, and u ( t ) is the time stamp of the last completedpacket. The AoI time evolution for our proposed system model TimeAoI ⨉ ● ⨉ ● ⨉ ● Q A,i Q A,i + S i − I i S i I i + Y i Y i + S i + ⨉ ☆ ☀ ‡ △▲ ☆ ● ⨉ K i,n D L i,j S i − R i,j V K i,n + D I i Figure 2. AoI evolution for an IPD that checkpoints its state with a fixedregularity. Symbol notation: ⨉ denotes the start of sensing, ‡ denotes devicefailure, ● denotes the end of the final checkpoint and instantaneous packettransmission, ☆ denotes the start of checkpointing from VM to NVM, ☀ denotes the end of checkpointing from VM to NVM, △ denotes start ofrestoration from NVM to VM, and ▲ denotes the end of restoration fromNVM to VM. All variables are defined in Section II. is depicted in Fig. 2. Using this graphical representation wecan calculate the expectation of (1) as follows. Let us denotea trapezium Q A,i , whose area is given by Q A,i = (( S i − + Y i ) − S i ) . (2)This is the isosceles triangle created by S i − + Y i minus thesmaller isosceles triangle with base S i . The area Q A,i + ishighlighted in Fig. 2 as an example. Given that S i − and Y i are independent and S i − and S i are identically distributed, asconsidered in [17, Eq. (5)], the expectation of (2) becomes E [ Q A,i ] = E [ Y i ] + E [ S i − ] E [ Y i ] . (3)As argued in [17, Eq. (6)], and in concordance with thegeometry presented in Fig. 2, the average AoI is E [ ∆ ] = λ E [ Q A,i ] , (4)where λ is the interarrival time of packets to the device. Sinceour system model considers packet generation, rather thanpacket arrival, the distribution of λ will be predicated on thedistribution of time between sensing (which is equivalent tothe distribution of time between transmission) hence λ = E [ Y ] .Here we introduce Y and S for the inter-completion time and completion time , respectively, when taking their expectedvalues, E [ Y ] and E [ S ] , as time tends to infinity. This ispossible due to the ergodicity of the system. As such (4)simplifies to [17, Eq. (6)] E [ ∆ ] = E [ Y ] E [ Y ] + E [ S ] . (5)The average PAoI, a more manageable measure of data fresh-ness compared to average AoI, is given by [17, Eq. (7)] [9,Eq. (8)] E [ ∆ Peak ] = E [ Y ] + E [ S ] . (6)V. C OMPLETION AND I NTER -C OMPLETION T IME
Given (5) and (6) it is imperative that we find expressionsfor Y i and S i from which we can calculate their expectedvalues, E [ Y ] and E [ S ] , over many cycles. From Fig. 2 wesee that the inter-completion time for cycle i is Y i = I i ® Idle time + f ∑ j = ( L i,j + R i,j + V )´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶ Events associated with failure + h ∑ n = K i,n ´¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¶ Processing ≜ P i + Dh, ± Checkpointing (7)where f and h are the number of system fails and the numberof successfully performed checkpoints during the period oftime Y i , respectively. The time between data being sensed anda packet being transmitted, the completion time , for cycle i is S i = Y i − I i . (8)V. E XPECTATION OF C OMPLETION AND I NTER -C OMPLETION T IME
To identify the expected values of AoI in (5) and (6),and hence understand the freshness of data produced by themodelled IPD, we must first find the expected values of (7)and (8) over many cycles. We assume that all variables in (7)and (8) have well-defined means and known variance. Due tothe assumed ergodicity of the system we can also simplifynotation when taking the expected values of variables (forexample, the expectation of I i is E [ I ] as t tends to infinity).By following the approach of [17, Eq. (10)], we use Wald’sidentity to find that the expected values of inter-completiontime and completion time are E [ Y ] = E [ I ] + E [ f ] ( E [ L ] + E [ R ] + V ) + E [ h ] E [ K ] + D E [ h ] , (9) E [ S ] = E [ Y ] − E [ I ] , (10)respectively. By definition, the amount of wasted processingper failure will take a value L i,j ∈ [ . . K i,θ + D ] clockticks where L i,j ∈ N + and θ is the checkpoint number of theprocessing cycle started but interrupted in L i,j . For instancein Fig. 2, θ = n + since the K i,n + cycle was initiallystarted in L i,j , however could not finish before failure. Wealso assume that all possible values of L i,j are equally likely.Therefore, based on these assumptions, the expectation ofwasted processing time per failure is E [ L ] = E [ K ] + D + . (11)Given the definition of processing time P i , given in the secondsummation of (7), its expected value will be E [ P ] = E [ h ] E [ K ] . (12)Substituting (11) and (12) into (9) yields E [ Y ] = E [ f ] ( C + E [ P ] E [ h ] ) + C + D E [ h ] , (13) where C = E [ R ] + V + D + , and C = E [ I ] + E [ P ] are definedfor compactness of presentation.VI. E XPECTATION OF A VERAGE PA O IGiven (6) and expressions (10) and (13) the average PAoIfor our mixed-memory IPD is therefore E [ ∆ Peak ] MM = E [ f ] ( C + E [ P ] E [ h ] ) + C + E [ P ] + D E [ h ] . (14)We can see from this expression the clear conflict betweenover and under checkpointing. If failure occurs, which is acore phenomenon associated with an IPD, then an increase inthe checkpointing frequency (meaning an increase in E [ h ] )increases E [ ∆ Peak ] MM through the final D E [ h ] term—i.e.the overhead associated with checkpointing. In contrast, anincrease in E [ h ] also reduces the E [ P ] E [ h ] term, since morefrequent checkpointing reduces the expected wasted process-ing time per power failure. From (14) we also observe thatthe constant C (and hence the constants V and D ) increasethe average PAoI, so these should be minimised by systemsdesigners. Further, increases in E [ I ] and E [ R ] will alsoincrease E [ ∆ Peak ] MM , however we consider these to be outsidethe control of the designer. Minimising the Average PAoI.
Due to the conflict of overand under checkpointing we can find a value of E [ h ] tominimise the average PAoI as follows. Taking the derivativeof (14), with respect to E [ h ] we have d E [ ∆ Peak ] MM d E [ h ] = D − E [ f ] E [ P ] E [ h ] . (15)Then, letting (15) equal to zero and solving for E [ h ] , we findthat (14) is minimised when E [ h ] = √ E [ f ] E [ P ] D . (16)This expression is comparable to [19, Eq. (7)] and showsthat checkpoint optimisation is not inherently changed bythe unique characteristics of the sensor device. Expression(16) shows that the optimum number of checkpoints in acycle is based on three fundamental parameters of the system; E [ f ] , E [ P ] , and E [ D ] . This is consistent with intuition sincea decrease in the expected number of failures would meanfewer required checkpoints, an increase in processing timewould necessitate more checkpoints, and an increase in thecheckpoint overhead would reduce its desirability.VII. E XPECTATION OF A VERAGE A O IFrom (5) we can find an expression for the average AoI ofour system by substituting in (13) and (10), and by finding E [ Y ] . Since we have assumed that the variance of each termin Y is known, we are able to use the definition of varianceto find E [ Y ] from E [ Y ] = Var ( Y ) + E [ Y ] . (17)y substituting (17) into (5) the expression for the averageAoI becomes E [ ∆ ] = Var ( Y ) E [ Y ] + E [ Y ] − E [ I ] . (18)As such, by substitution, we find that the average AoI of thesystem is E [ ∆ ] MM = Var ( Y ) C + C E [ h ] + D E [ h ] − E [ I ] + ( C + C E [ h ] + D E [ h ]) , (19)where C = E [ f ] C + C and C = E [ f ] E [ P ] are definedfor compactness of presentation. From (19) we see that theaverage AoI, as with the average PAoI, is dependent on E [ f ] and E [ h ] . Whilst minimisation of this expression with respectto E [ h ] is not presented here, a tractable solution can be foundby setting the derivative of (19) to zero and solving for E [ h ] .VIII. P EAK A GE OF I NFORMATION : M
IXED -M EMORY V ERSUS S INGLE -M EMORY A RCHITECTURE
Having identified an expression for the average PAoI ofour model in (14) we proceed to examine to what extentcheckpointing in mixed-memory architecture has affected theperformance of our IPD compared to a single-memory device.Whilst in practice, typical commercially available devices aremixed-memory [1, Section 1], we can consider two possiblealternatives, a single-memory IPD entirely comprised of NVM[22], [23], or a single-memory IPD entirely comprised of VM.We assume that both types of memory are able to performprocessing at the same rate.
Lemma 1.
An entirely NVM IPD will have a lower or equalaverage PAoI than a checkpointing mixed-memory IPD.Proof.
Using the same formulation as (7), the inter-completiontime for such an NVM IPD would be Y i = I i + f ∑ j = R i,j + P i , (20)since the device does not checkpoint and the only impact offailure is the system off-time. The completion time would takethe same form as (8). Following the same steps as Sections Vand VI, the average PAoI of the device would be E [ ∆ Peak ] NVM = E [ I ] + E [ f ] E [ R ] + E [ P ] . (21)We can compare the above expression with the average PAoIof our system by finding the difference between (14) and (21),i.e. E [ ∆ Peak ] MM − E [ ∆ Peak ] NVM = D E [ h ] + E [ f ] ( V + D + + E [ P ] E [ h ] ) , (22)which shows that E [ ∆ Peak ] NVM ≤ E [ ∆ Peak ] MM ∀ E [ f ] , E [ h ] , (23) and hence a system comprised of entirely NVM would alwaysperform better than or equal to the mixed-memory system. Lemma 2.
Under certain environmental conditions a mixed-memory IPD will have a lower average PAoI than a (single-memory) VM IPD.Proof.
A single-memory device comprised of entirely VM,following the same formulation as (7), would have an inter-completion time of Y i = I i + f ∑ j = ( R i,j + Γ i,j + I i,j ) + P i , (24)where Γ i,j is the amount of wasted processing that occurs dueto failure j in cycle i and the system does not checkpoint orrestore (rather it re-senses after failure). I i,j is the idle timebefore the system re-senses after failure j . The expected valueof Γ i,j will be E [ Γ ] = E [ P ]+ since the system could wasteup to P i clock ticks of processing per fail and each amount ofwasted processing time is equally likely. The completion time would take the same form as (8). Following the same steps asSections V and VI, the average PAoI of a single VM IPD is E [ ∆ Peak ] VM = E [ f ] ( E [ R ] + E [ P ] + + E [ I ]) + E [ I ] + E [ P ] . (25)The above expression can be greater than or smaller than (14)depending on the selected system parameters, hence ∃ E [ f ] , E [ h ] ∋ E [ ∆ Peak ] VM > E [ ∆ Peak ] MM , (26)and thus there is a set of environments in which check-pointing in mixed-memory architecture is more efficient thannot checkpointing in single-memory VM architecture. Thisimprovement is most evident when the mixed-memory IPDhas a low checkpointing overhead and high failure rate.IX. I MPROVING S YSTEM R ESILIENCE IN V ARIABLE E NVIRONMENTAL C ONDITIONS
Thus far we have considered a checkpointing system thatcan be optimised based on a known expected number of fail-ures, yet in reality IPDs are often placed in environments withvariable and unpredictable failure rates—making it difficultto pre-determine an optimum rate of checkpointing. We nowpropose an alternative method of TDC for mixed-memorydevices to improve system resilience—Split-Frequency Check-pointing (SFC)—in which the inter-checkpointing time variesbetween predefined intervals α and β . Here we once againuse the framework devised in Sections II and III. We nowassume that the duration of processing between checkpoints,previously K i,n , varies between two fixed amounts, K i,α and K i,β . Then, the processing time P i = ∑ h α α = K i,α + ∑ h β β = K i,β .Additionally, the expected wasted processing per fail wouldbe E [ L ] = p α E [ L α ] + p β E [ L β ] where p α and p β are theprobabilities of failure during an α and β checkpoint, respec-tively, such that p α = E [ K α ] E [ K α ]+ E [ K β ] and p β = E [ K β ] E [ K α ]+ E [ K β ] . E [ L α ] and E [ L β ] are the expected wasted processing due
20 40 60 80 100
Expected number of checkpoints E[h] A v e r a g e P A o I [ c l o c k ti c k s ] Average peak AoI [RF 1]Average peak AoI [RF 2]Minimum AoI values (a) Impact of Harvested Energy
Expected number of system failures E[f] A v e r a g e P A o I [ c l o c k ti c k s ] MMNVMVM (b) Impact of Memory Structure
Expected number of system failures E[f] A v e r a g e P A o I [ c l o c k ti c k s ] E[K i,n ] = 25E[K i,n ] = 5E[K i, ] = 5, E[K i, ] = 20 (c) Impact of Checkpointing StrategyFigure 3. Set of example numerical result (its source code is available at [21]). (a) Scenario RF 2 conditions require fewer checkpoints than
Scenario RF 1 .Under-checkpointing causes significant increase in average PAoI. (b) Mixed-memory performs better than VM for most failure conditions. (c) SFC is betterthan inaccurately selected single-frequency. to a failure in an α and β checkpoint, respectively, where E [ L α ] = E [ K α ]+ D + and E [ L β ] = E [ K β ]+ D + . This can alsobe expressed as E [ L ] = E [ K i,α ] + E [ K i,β ] ( E [ K i,α ] + E [ K i,β ]) + D + . (27)Following the same derivation of average PAoI as in Sec-tions V and VI, the average PAoI of a SFC system with twofrequencies is E [ ∆ Peak ] MM(split) = C + D ( E [ h α ] + E [ h β ]) + E [ P ] + E [ f ] ( C + E [ K i,α ] + E [ K i,β ] ([ E [ K i,α ] + E [ K i,β ]) ) . (28)From this expression we observe that the average PAoI isdependent on a number of system parameters (including E [ P ] , E [ f ] , and D ), however most interesting is the dependenceon inter-checkpointing times E [ K i,α ] and E [ K i,β ], which isnotably different to the E [ P ] E [ h ] → E [ K ] term in (14).X. N UMERICAL R ESULTS
We now provide a set of example numerical results in Fig. 3using
Scenario RF 1 and
Scenario RF 2 energy harvestingconditions, with data taken from [24, Fig. 1] and summarizedin Table I—we note that we have converted ms to our baseunits of clock ticks therein). Impact of Harvested Energy.
We present the averagePAoI of our considered mixed-memory IPD system (expres-sion (14)) in Fig. 3a using the parameters of Table I. FromFig. 3a we see that the average PAoI varies under differentenergy conditions and that the decrease in E [ f ] between RF 1 and
RF 2 decreases the value of E [ h ] that minimises averagePAoI. We also see that under-checkpointing has a far moresignificant impact of data freshness than over-checkpointing. Impact of Memory Structure.
We also consider the re-lationship between memory architecture and data freshness.Fig. 3b presents plotted expressions (14), (21), and (25) asa function of the expected number of failures E [ f ] (usingTable I RF1 parameters and E [ h ] = for MM). From Fig. 3bit is evident that, whilst not universally true, for an expectedcheckpointing overhead and above a low number of failures E [ ∆ Peak ] VM > E [ ∆ Peak ] MM > E [ ∆ Peak ] NVM . This shows thatwhilst entirely NVM architecture will always produce thebest possible average PAoI, mixed-memory structures using
Table IS
YSTEM P ARAMETER V ALUES USED FOR N UMERICAL R ESULTS E [ P ] ◇ E [ R ] ∗ E [ f ] ∗ E [ I ] ⊲ D ≀ V † Scenario RF 1
500 50 15 200 5 10
Scenario RF 2
500 75 6 200 5 10 ◇ Set as a baseline for the system. This value varies significantly based onprocessing needs. ∗ Representative of the dynamic variation of off-time forthe first two scenarios in [24, Fig.1] where failure occurs approximatelyevery
50 ms and
100 ms , respectively. ⊲ Approximate boot time of TinyOSfrom [24, Section 2]. ≀ Overhead can vary significantly in real-worldsystem, is of the order of magnitude expected compared with on-time in [24, Fig.1]. † Restoration overhead is typically around twice thecheckpoint overhead due to additional management and fixed boot costs. checkpointing can provide significant improvements in datafreshness compared with entirely volatile IPDs.
Impact of Checkpointing Strategy.
Finally we show theimpact of checkpoining strategy by plotting expressions (14)and (28). Results are presented in Fig. 3c. We see that thesystem using two inter-checkpointing times ( E [ K i,α ] = and E [ K i,β ] = ) is the most efficient for a range ⪅ E [ f ] ⪅ and also provides reasonable performance for all E [ f ] . Whilst SFC cannot exceed the theoretical optimum fora single frequency (expression (16)) it can provide additionalresilience by reducing the risk of a very high average PAoIdue to an inappropriately chosen inter-checkpoint interval inan environment with unknown or variable failure rate.XI. C ONCLUSION
In this paper we have considered an Intermittently-PoweredDevice (IPD) with mixed-memory architecture that periodi-cally checkpoints the system state from volatile memory tonon-volatile memory—from which it can be restored shouldpower failure occur. We have identified expressions for theaverage Age of Information (AoI) and average Peak Age ofInformation (PAoI) of the system, and found a relationship forthe expected checkpointing rate that minimises the expectedPAoI. We have also shown that a mixed-memory IPD usingTime-Dependent Checkpointing (TDC) can reduce the systemPAoI compared with a single volatile memory IPD for selectedsystem parameters. Further, we have proposed an alternativeTDC scheme, Split-Frequency Checkpointing, which can im-prove IPD performance compared with inaccurately selectedsingle-frequency checkpoint intervals.
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