Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing
Arnout Beckers, Farzan Jazaeri, Heorhii Bohuslavskyi, Louis Hutin, Silvano De Franceschi, Christian Enz
DDesign-oriented Modeling of 28 nm FDSOI CMOSTechnology down to 4.2 K for Quantum Computing
Arnout Beckers † , Farzan Jazaeri † , Heorhii Bohuslavskyi ‡ , Louis Hutin ‡ , Silvano De Franceschi ‡ , and Christian Enz †† Integrated Circuits Laboratory (ICLAB), Ecole Polytechnique F´ed´erale de Lausanne (EPFL), Switzerland, ‡ CEA-L´eti, Grenoble, Francearnout.beckers@epfl.ch
Abstract —In this paper a commercial 28-nm FDSOI CMOStechnology is characterized and modeled from room temperaturedown to 4.2 K. Here we explain the influence of incompleteionization and interface traps on this technology starting fromthe fundamental device physics. We then illustrate how thesephenomena can be accounted for in circuit device-models. We findthat the design-oriented simplified EKV model can accuratelypredict the impact of the temperature reduction on the transfercharacteristics, back-gate sensitivity, and transconductance effi-ciency. The presented results aim at extending industry-standardcompact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.
I. I
NTRODUCTION
Quantum computing can reshape many fields by providingthe computing power to solve exponentially-growing prob-lems. To reach this computing power, an important challengetoday is the scale-up to larger qubit numbers [1], [2]. Each ad-ditional qubit adds to the complexity of the room-temperaturecontrol-equipment, introducing more interconnections, wiringcapacitance and thermal-noise pickup. Implementing the con-trol equipment in miniaturized cryo-CMOS represents aninteresting solution for scalability and fast qubit-informationprocessing. Digital, analog and RF circuits are then required tooperate down to deep-cryogenic temperatures. In this context,silicon-on-insulator technology provides an excellent platformto create a complete, scalable quantum computing system [3],[4]. CMOS-compatible spin qubits have been developed in aFDSOI nanowire technology [5], [6], and can be co-integratedwith the required qubit-control circuits designed in a FDSOICMOS process. Increased digital/analog performances downto 4.2 K have been reported for advanced FDSOI CMOStechnologies [7], [8]. The suitability of the 28 nm node forqubit-control electronics has been reported in [7]. Furthermore,the FDSOI back-gate offers a versatile tool to control thepower consumption close to the qubits [7], which may becomeessential to keep decoherence at bay in co-integrated quantum-classical circuits. Due to a strong reduction of the coolingpower at millikelvin temperatures, the control circuits areenvisioned to operate at 4.2 K or higher—and eventually thequbits as well [2]. However, designing the cryo-CMOS qubit-control circuits—while meeting a stringent speed-power trade-
This project has received funding from the European Union’s Horizon 2020Research & Innovation Programme under grant agreement No. 688539 MOS-Quito. TABLE II
NVESTIGATED D EVICES (28- NM FDSOI CMOS P
ROCESS ) Symbol Type W/L (cid:108) n MOS 1 µ m / 1 µ m (cid:115) p MOS 1 µ m / 1 µ m (cid:116) n MOS 1 µ m / 28 nm (cid:110) n MOS 210 nm / 28 nm (cid:117) n MOS 80 nm / 28 nm off—is not an easy task, since cryo-CMOS device models arecurrently lacking in circuit-simulators. In order to keep pacewith the rapid qubit-developments, device models remainingphysically accurate down to 4.2 K are urgently required. Tothis purpose, important physical phenomena at deep-cryogenictemperatures, i.e. interface trapping and incomplete ionization,need to be included. Here, after a brief discussion of themeasurement results down to 4.2 K, the temperature-trends ofthe main technological parameters are investigated (Sec. II).To explain some of these trends, we examine the temperaturedependencies of interface trapping and incomplete ionizationin the device physics of this technology (Sec. III). It will beevidenced that these phenomena can respectively alter theslope factor and the threshold voltage. As we will demonstrate,adjusting the corresponding model parameters in the design-oriented simplified EKV model, allows to model the DCcryogenic device-performance down to 4.2 K, including theeffect of the back-gate (Sec. IV). These results pave the waytowards the extension of industry-standard compact modelsdown to the deep-cryogenic temperature regime [9], [10]. Thiswill allow to explore optimal cryo-CMOS circuit designs formultiple applications, in particular qubit-control systems.II. M
EASUREMENTS AND C HARACTERIZATION
The set of devices under investigation, fabricated in acommercial 28 nm FDSOI CMOS process, is listed in Table I.Details on the fabrication procedure can be found in [7].A schematic cross-section of the FDSOI n MOS transistor isdrawn in Fig. 1a. The transfer characteristics were measuredin the linear ( V DS = 50 mV) and saturation operational regimes( V DS = 0.9 V) at different temperatures [7]. The back-gatevoltage ( V back ) is swept from − V back = 0 V.The strong improvement of the SS with decreasing tem-perature is clear for all devices in Fig. 1. However, note a r X i v : . [ phy s i c s . a pp - ph ] A ug ) c)b) T (K)300 4.2 d) f)e)
T (K)300 4.2T (K)300 4.2T (K)300 4.2 T (K)300 4.2 n+ Buried oxide n+p+ pV G V D V S V back Si y Fig. 1. a) Schematic cross-section of a n MOS device fabricated in a 28 nm FDSOI CMOS process [7], b)-f) Transfer characteristics measured in saturation( | V DS | = 0.9 V) with V back = 0 V, at 300, 210, 160, 110, 77. 36, 10, and 4.2 K for b) n MOS
W/L = 1 µ m / 1 µ m, c) n MOS
W/L = 1 µ m / 28 nm, d) p MOS
W/L = 1 µ m / 1 µ m, e) n MOS
W/L = 210 nm / 28 nm, and f) n MOS
W/L = 80 nm / 28 nm. The EOT for n MOS is 1.55 nm, and for p MOS 1.7 nm. Thegate-source voltage is increased with a step size of | V GS | = that the improvement from 36 K down to 4.2 K is marginal,especially for the short devices. Based on the measurementsin Fig. 1, the following technological parameters have beenextracted (Fig. 2): the subthreshold swing ( SS ), slope factor( n ), threshold voltage ( V th ), transconductance in linear andsaturation ( G m,lin , G m,sat ), and the on-state current ( I on ).As illustrated in Fig. 2a, for temperatures below ≈
160 K,the extracted average SS -values show an increasing offset, ∆ SS , from the thermal limit, U T ln 10 , with U T (cid:44) kT /q the thermal voltage. ∆ SS reaches around 10 mV/dec at 4.2 Kfor long n MOS, since U T ln 10 predicts ≈ SS are extractedin Fig. 2b using n = SS/ ( U T ln 10) . From this figure, ahyperbolic temperature-dependency of n is evident, which isnot strongly dependent on geometry at cryogenic temperatures.The data points below 77 K in Fig. 2a cannot be explainedby n U T ln 10 with a slope-factor n limited by 2, accordingto n = 1 + C dep /C ox , where C dep is the depletion capaci-tance and C ox the oxide capacitance. Moreover, including theinterface-trap capacitance, C it = qN it , i.e. n = 1 + ( C dep + C it ) /C ox with N it the density-of-interface-traps per unit area,would lead to very high extracted values for N it in theorder of cm − at 4.2 K [11]–[13]. However, it should beemphasized that in this n -formula the temperature-dependentoccupation of interface-traps is not taken into account. Thiswill be further investigated in Sec. III. The shift in thresholdvoltage at 4.2 K with respect to room temperature increasesin the order of 0.1 − V th -increase is observed for p MOS, similarly to a 28-nm bulkprocess [14]. Furthermore, the maximum G m,sat and G m,lin (Figs.2d-e) improve down to 4.2 K, e.g. respectively × × n MOS
W/L = 1 µ m / 1 µ m.In Fig.2f, I on is extracted at | V GS | = I on with temperature is strongly dependent on thebias and the device-type. At a standard supply-voltage of 1 V,the on-state current increases with decreasing temperature forlong n MOS (Fig. 1b), while it decreases for p MOS (Fig. 1d).The drain-induced barrier-lowering (DIBL) is approximatelyzero for the long devices. For the short devices, small im-provements have been extracted down to 4.2 K, but the short-channel effect remains largely temperature-independent, e.g.decreasing from 0.07 V/V (300 K) to 0.068 V/V (4.2 K) for n MOS
W/L =
80 nm / 28 nm, and from 0.065 V/V (300 K)to 0.059 V/V (4.2 K) for n MOS
W/L =
210 nm / 28 nm (ex-tracted at I D = 10 − A ).III. D EVICE P HYSICS
The improvements of ( SS , G m,sat , G m,lin ) and the increasein V th follow directly from the temperature-scaling of theFermi-Dirac distribution function, f ( E ) . As illustrated inFig. 3a, at 4.2 K f ( E ) is almost a step function. Therefore, theconduction band needs to be bent further downward to createsufficient overlap with the conduction-band density-of-statesto reach inversion, increasing V th . Note that the subthresholdregion happens only when E F lies within ≈ U T of E c .However, as indicated by ∆ SS in the previous section, theturn-on rate predicted in this way is too steep. In what follows,we investigate the impact of incomplete ionization/freeze-out and interface trapping to explain this observation. Bothphenomena are modeled by the Fermi-Dirac distribution as ) b) c)d) e) f) U T l n 1 0 ΔSS ∝ Fig. 2. Technological parameter extraction at 300, 210, 160, 110, 77. 36, 10, and 4.2 K, a) Subthreshold swing, modeled for long-channel devices by SS = n U T ln 10 + ∆ SS , with ∆ SS ∝ N it [15], [16], b) Slope factor in log-log scale highlighting its hyperbolic temperature dependency, c) Threshold-voltage shift with respect to 300 K, d)-e) Maximum transconductances in saturation and linear regions of operation, normalized to 300 K, f) On-state currentnormalized to 300 K. Colors indicate the temperature, and markers the device according to Table I. well, i.e. respectively f ( E A ) (for p -type doping) and f ( E t ) ,where E A and E t are the acceptor and trap energy levels.This is qualitatively shown in Fig.3a. In case the Si-channel(Fig. 1a) is truly undoped, incomplete ionization should notbe considered. However, if there is a certain backgrounddoping, e.g. p -type N A = 10 cm − , these impurities canbe frozen out in the flatband condition at 4.2 K. As shownin Fig.3a, the calculated E F -position for low-doped channelat 4.2 K lies under E A , leading to freeze-out ( f ( E A ) (cid:28) ).Nonetheless, these impurities will become quickly ionizeddue to field-assisted ionization [17], when E A bends under E F near the surface of the front-gate. In the subthresholdregion, when E F ≈ E c − U T , complete ionization can beassumed. Therefore, incomplete ionization cannot lead to thesubthreshold-swing degradation observed in the previous sec-tion. Note, however, that for non-zero doping concentrationsincomplete ionization can yield a small change in the thresholdvoltage, due to a modification of the charge-neutrality andthe resulting E F -position [16]. Fig. 3a highlights that thetemperature-dependency of interface-trap occupation, f ( E t ) ,may influence the turn-on rate of the device down to 4.2 K.Similarly to the derivation for bulk MOSFET presented in [16],by including f ( E t ) the temperature dependency of n ∝ /U T can be derived for the front-gate in FDSOI as well. Thisgives SS = n ( T ) U T ln 10 = n U T ln 10 + ∆ SS , where n is the slope factor without interface traps, and ∆ SS thesubthreshold-swing offset as observed in the previous section. ∆ SS is given by ( qN it /C ox ) ln 10 (cid:2) g t / (1 + g t ) (cid:3) with N it thedensity-of-interface-traps and g t the trap degeneracy factor. Note that in this model, N it does not become multipliedwith U T , resulting in reasonable extracted values for N it at4.2 K ( ≈ - cm − ) lower than [12], [13]. The ∆ SS -offset starts to increase below ≈
160 K since the subthresholdregion happens when E F lies closer to E c , where N it isobserved to be higher already at 300 K (Fig. 3a). From thissection, we conclude that interface trapping strongly degradesthe SS through the hyperbolic temperature-dependency of n ,and incomplete ionization slightly alters the V th -increase fornon-zero doping concentrations. These two parameters, n and V th , can be modified accordingly in design-oriented modelsto predict deep-cryogenic operation. In the next section wedemonstrate this relying on the simplified EKV model.IV. D ESIGN - ORIENTED M ODELING
The design-oriented simplified EKV model is describedin detail in [18]. The suitability of this model for FDSOIprocesses has been assessed at room temperature [19]. Usingthis model, the effects of the temperature reduction down to4.2 K on the transfer characteristics, the back-gate sensitivity,and the transconductance efficiency are modeled. The modelaccurately predicts the transfer characteristics down to 4.2 Kfor long (Figs. 3b-c) and short devices (Fig.3d). The strongincrease in the n model parameter at 4.2 K accounts forthe interface-trapping phenomenon. The V T model parametercaptures the change in the threshold voltage due to Fermi-Dirac scaling and incomplete ionization. Note that the usedvalues for n and V T correspond to the extracted values inFig. 2b and 2c. Furthermore, as illustrated in Fig. 3e, changingthe V T model parameter allows to capture the effect of the .2 K300 KL sat
300 4.2 300 77 4.2300 77 4.2 e) f)a) c)b)d) E c E D E A E v f(E A ) E i E t B u r i ed o x i de f(E) y E F (undoped) E F ( N A = cm − ) E t Fig. 3. Band diagram along the y -direction in Fig. 1a. The position of the Fermi-level, E F , is calculated at 4.2 K in the case of undoped and low-dopedchannel, including incomplete ionization and bandgap widening at 4.2 K. The simulated Fermi-Dirac distribution at 4.2 K is plotted for both cases. Thetemperature-dependent occupation of the interface traps, f ( E t ) , can degrade the subthreshold swing. Due to band bending of E A under E F at the front-gate,frozen-out impurities under the surface become completely ionized ( f ( E A ) = 1 ), long before subthreshold is reached ( E F ≈ E c − U T ) due to field-assistedionization. b)-e) Simplified EKV (solid lines) for b) n MOS
W/L = 1 µ m / 1 µ m, c) p MOS
W/L = 1 µ m / 1 µ m, and d) n MOS
W/L = 1 µ m / 28 nm at 300,77, and 4.2 K (markers) for V back =0 V. The model parameters, n , V T (threshold voltage), I spec (cid:3) (specific-current-per-square), and L sat (saturation length),are shown. e) Back-gate sensitivity at 4.2 K modeled with simplified EKV. The model is shown for V back = − IC , at 300 and 4.2 K. back-gate also at 4.2 K [19]. A small adjustment of the slopefactor is necessary as well, to account for the change in SS in-duced by the back-gate. Fig.3f verifies that the G m /I D design-methodology remains valid for a 28 nm FDSOI technologydown to 4.2 K. The normalized transconductance efficiency, G m nU T /I D , is plotted versus the inversion coefficient IC (cid:44) I D,sat /I spec , with I spec = I spec (cid:3) W/L = 2(
W/L ) nµC ox U T .The specific-current-per-square, I spec (cid:3) , decreases over oneorder of magnitude from room temperature down to 4.2 K. Forthe short-channel device, the additional L sat -parameter, whichdenotes the length of the channel in full velocity saturation,decreases down to 4.2 K due to a reduced phonon scattering.V. C ONCLUSION
In this work, the DC operation of a 28 nm FDSOI tech-nology is modeled down to 4.2 K by means of the simplifiedEKV model. A study of the device physics is first performedincluding the temperature dependencies of interface trappingand incomplete ionization. We find that the Fermi-Diractemperature dependency of interface-trap occupation explainsthe large degradation of the subthreshold swing at 4.2 K. Incase impurities are present, freeze-out is of minor importancefor device operation thanks to field-assisted ionization. Theseresults bring us one step closer to the realization of large-scalesilicon-based quantum computing systems. R
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