Development of a Low-noise Front-end ASIC for CdTe Detectors
Tenyo Kawamura, Tadashi Orita, Shin'ichiro Takeda, Shin Watanabe, Hirokazu Ikeda, Tadayuki Takahashi
DDevelopment of a Low-noise Front-end ASIC for CdTe Detectors
Tenyo Kawamura a,b, ∗ , Tadashi Orita b , Shin’ichiro Takeda b , Shin Watanabe c,b ,Hirokazu Ikeda c , Tadayuki Takahashi b,a a Department of Physics, University of Tokyo, 7-3-1 Hongo Bunkyo, Tokyo 113-0033, Japan b Kavli Institute for the Physics and Mathematics of the Universe (WPI), University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8583,Japan c Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency (ISAS / JAXA), 3-1-1 Yoshinodai, Chuo-ku, Sagamihara,Kanagawa 252-5210, Japan
Abstract
We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTeDSDs) and high spectroscopic imaging. It is implemented in a 0 . µ m CMOS technology (X-Fab XH035), consistsof 64 readout channels and has a function that performs simultaneous AD conversion for each channel. The equiv-alent noise charge of 54 . − ± . − (rms) is measured without connecting the ASIC to any detectors. From thespectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1 .
12 keV (FWHM) isobtained at 13 . . . Keywords:
ASIC; Low-noise; X-ray; Gamma-ray; CdTe; Analog front-end
1. Introduction
Imaging spectroscopy of photons from 10 keV to afew hundreds keV has a variety of applications in as-tronomy, medicine and industry. The wide use of thisimaging technique has driven the development of im-agers based on CdTe detectors, since they have high ab-sorption e ffi ciency comparable with that of NaI and CsI,and the predominance of photoelectric absorption up to ∼
250 keV [1, 2, 3].In the field of in-vivo molecular imaging, large detec-tion area of ∼
10 cm is required as well as the energyresolution of ∼ ∼ µ min order to image multiple radioisotopes[4]. A double-sided strip detector is a promising solution in terms ofits small number of readout channels compared to apixel detector. However large capacitance at the inputof the signal processing circuit degrades the noise per-formance. It is therefore crucial to design a low-noisereadout chip which operates under a large detector ca-pacitance. ∗ Corresponding author
Email address: [email protected] (TenyoKawamura)
We present our latest ASIC named KW04H64 whichwas designed for the readout of CdTe DSD having adetection area of ∼
32 mm ×
32 mm, a strip pitch of250 µ m, and a capacitance of ∼
10 pF for each channel.The ASIC has been modified from our previous versions(e.g. [5, 6]).Section 2 describes the signal processing architec-ture of the ASIC and its predicted performance basedon simulation results. Section 3 reports the first ASICmeasurements. In Section 3.2 and 3.3 we discuss themeasured noise performance and dynamic range of theASIC when not connected to a detector. In Section3.4, we evaluate the spectroscopic performance whenthe ASIC is connected to a CdTe and Silicon (Si) semi-conductor detector, and in Section 4 we propose a newlow-noise readout architecture.
2. ASIC Description
The KW04H64 ASIC is implemented in a CMOS0 . µ m technology (X-Fab XH035). The chip has 64readout channels with self-trigger capability and it mea-sures 7 .
12 mm × .
03 mm. The dual power supply line
Preprint submitted to Journal of L A TEX Templates September 2, 2020 a r X i v : . [ phy s i c s . i n s - d e t ] S e p DDVSS
LCC
Vbias - + R R - + - + R’ R’ - + - + TP - + VTH1 VSS1 HIT1ENAHIT ENBDHIT - + VTH2 VSS1 HIT2ENAHITAIN VGG - + - + Ramp signal4bit DAC4bit DAC 5bit DAC C in C f C f f R f R f f 5bit DAC - + AOUT C pz R pz C’ pz R’ pz C C C’ C’ C hSLOWTMLGAINSLOWTMLGAIN Leakage Current Compensation Resistance CircuitResistance Circuit
HOLD, FASTTM HOLDHOLD, POS C C C C C C C C C C Global chain
Ramp Generator
Ramp signalADCKENADC
Counter C C C C C C C C C C S S S S S S S S S S LATCH SUBTRACTIONComparator D T H D T H D T H D T H D T H D T H D T H D T H D T H D T H Digital Comparator
DHITInOut OutIn InOut OutIn
Figure 1: Schematic of the signal processing circuit implemented in each readout channel. Typical values of resistors and capacitors are R f = Ω , C f = .
032 pF, R pz =
50 M Ω , C pz = . R = R = Ω , C = . C = . R (cid:48) = R (cid:48) = . Ω , C (cid:48) = . C (cid:48) = . C (cid:48) h = . .
12 mm × .
03 mmNumber of channels 64Power rail ± .
65 VPolarity BothGain 170 mV / fCDynamic range ∼ . . − + . − / pF (Fast shaper)33 . − + . − / pF (Slow shaper)Peaking time ∼ . µ s (Fast shaper) ∼ . µ s (Slow shaper)Power consumption 2 . / channel of ± .
65 V has been adopted to process the signal ineither polarity, which is required for DSDs. The maincharacteristics of the ASIC are summarized in Table 1.Figure 1 shows the signal processing architecture ofthe ASIC. This architecture is the same as the previousKW04D64 chip version[7], with minor modificationsconcerning the circuit gain and includes additional func-tions. It has a dual path topology after the charge sensi-tive amplifier (CSA). As the names suggest, the “timingbranch” is dedicated to measuring time, and the “energybranch” is dedicated to measuring energy. The timingbranch has a pole-zero cancellation (PZC), a 2nd-orderlow-pass filter, and two separate comparators whichgenerate hit signals. The energy branch has same archi-tecture as that of the timing branch before comparators, followed by a sample-and-hold circuit and a WilkinsonADC which enables the AD conversion for all the chan-nels to happen simultaneously. The PZC and the low-pass filter e ff ectively work as the CR-RC shaper, whichis called the “fast shaper” and “slow shaper” for the tim-ing and energy branches and results from simulationsgive peaking times of ∼ . µ s and ∼ . µ s, respec-tively. The 5-bit and 4-bit DACs employed for the base-line adjustment have a pair of output ports. The currentsupplied from one port of the DAC is designed to be re-covered by the other port, which avoids any interferenceto adjacent circuits such as the bu ff er amplifier. Thesample-and-hold circuit is triggered by an external con-trol block at a given time after a hit signal is generated.The fast shaper signal from the timing branch can be se-lected as an input of the Wilkinson ADC in the energybranch. This is beneficial for the performance measure-ment and the baseline adjustment of the fast shaper.The signals are read out after the AD conversion atthe Wilkinson ADCs for each event. The ASIC has asparse readout mode as well as a full readout mode. Inthe sparse readout mode, only those channels carryingthe signal data are read out in order to reduce the out-put data size. Whether each channel carries the signal isjudged by either the state of the hit signal (HIT1 in Fig-ure1) or the value of ADC subtracted by low frequencycommon mode noise[8].2 igure 2: Schematic of the resistance circuit implemented in theshaper. Connected to a current DAC, PCOMP and NCOMP can beused to calibrate a baseline coarsely. Voltage difference (mV) O u t pu t c u rr en t ( n A ) IBSLOW=10 uAIBSLOW=20 uAIBSLOW=40 uAIBSLOW=80 uAIBSLOW=120 uA
Figure 3: DC performance of the resistance circuit at the slow shaperpredicted by simulations.
The CSA employs a folded cascode scheme with aPMOS input transistor having W / L = µ m / . µ mproviding a transconductance of ∼ ∼ µ A. The drain current can be changedby an externally located potentiometer. In this paper, thefeedback capacitance at the CSA is fixed at 0 .
032 pF, al-though, depending on the photon energy, it can be set to0 .
032 pF, 0 .
064 pF, 0 .
096 pF, and 0 .
128 pF. The feed-back resistor is implemented using an NMOS. Its re-sistance is controlled by the gate voltage VGG, whichis generated by the internally located DAC. Although itwas switched o ff in this paper, a leakage current com-pensation circuit is implemented which can deal withup to ∼ ∼ Ω for the slowshaper and ∼ . Ω for the fast shaper. The resistancecircuits used in both the fast shaper and the slow shaperare implemented using the same architecture shown inFigure 2, where two-stage current mirror scales downthe current flowing into the passive resistor. The bias current at the resistance circuits is controlled externallyby changing the reference current in a similar mannerto the drain current of the input PMOS at the CSA. Thereference current for the resistance circuits at the slowshaper is a key parameter in the paper, and is referredto hereafter as IBSLOW. Note that the two resistancecircuits at each shaper are biased in common to makethe poles degenerated, i.e., to keep track of the criticaldamping condition.The reference current determines the amount of out-put current. The maximum output current I SR fromthe resistance circuit at the slow shaper is I SR ∼ (1 / ff erence under which the resistancecircuit behaves as a linear resistor. The maximum volt-age di ff erence V res , max is expressed as V res , max = R res I SR where R res is its resistance, i.e., ∼ Ω for the slowshaper. When the voltage di ff erence is larger than V res , max , the resistance circuit switches to the slew-ratelimited mode, where it can only source or sink a max-imum amount of current given by I SR . Figure 3 showsthe DC performance of the resistance circuit at the slowshaper predicted by simulations where the output volt-age is fixed at 0 V, meaning the voltage di ff erence de-scribed in the figure represents the input voltage. It hasbeen implied that the slew-rate limited mode contributesto better noise performance[10, 11].According to simulations, the maximum signal tobe processed is expected to be ∼ ∼
170 mV / fC, while the noise performance is ex-pected to be ENC = . − + . − / pF and ENC = . − + . − / pF for the fast shaper and the slowshaper respectively.
3. Experimental Results
The ASIC performance was evaluated both without adetector and with Si and CdTe detectors. In the setupwithout a detector, an ASIC was placed in a QFP ce-ramic package on a test board and test pulses generatedinternally were used as the input signals. The analoginput pads of 56 readout channels are floated, whilefor 8 channels each pad is connected to a pin on thetest board. Due to the di ff erence between these twotypes of configurations, 56 channels were used for theperformance evaluation. In the setup with a detector,bare chips were connected to single-sided strip detec-tors characterized in Tables 2 and 3, where the inputsignals to ASICs have positive polarity. The interfacewith a computer was established using the SpaceWire3 able 2: Main characteristics of the CdTe detector.Parameter ValueManufacturer ACRORADOType Schottky CdTe diodeSize 4 mm × µ m pitchIn side 1 plain electrodeTable 3: Main characteristics of the Si detector.Parameter ValueManufacturer Hamamatsu PhotonicsType PN Si diodeSize 12 . × . µ mP side 32 strip electrodes400 µ m pitch IBSLOW ( A) E qu i v a l en t N o i s e C ha r ge ( e ) Figure 4: Noise performance at the slow shaper with respect to IB-SLOW. The amplitude of the test pulse is − .
93 fC. The error barsrepresent one-sigma among the 56 channels.
DIO2[12] which contains a reconfigurable FPGA. Thededicated software was written for the ASIC operationon the computer.
Figure 4 shows the noise performance with respectto the reference current for the resistance circuit at theslow shaper. It was measured by injecting 1000 testpulses and then examining distributions of ADC val-ues for 56 channels. The amplitude of the test pulsesis − .
93 fC and the hold timing with respect to the hittiming was kept as 3 . µ s for IBSLOW ≥ µ A, whilefor IBSLOW = ,
20 and 10 µ A it is set at 4 . , . . µ s because of the slew-rate limited mode in theslow shaper, respectively (see Figure 6). From the fig-ure, the noise performance is improved more sharply asIBSLOW becomes smaller for IBSLOW (cid:46) µ A than
VGG (mV) E qu i v a l en t N o i s e C ha r ge ( e ) IBSLOW=40 uAIBSLOW=10 uA
Figure 5: Noise performance at the slow shaper with respect to VGG.The amplitude of the test pulse is − .
93 fC. The error bars representone-sigma among the 56 channels. for IBSLOW (cid:38) µ A. We conjecture that the noise re-duction for IBSLOW (cid:46) µ A is related to the slew-ratelimited mode of the resistance circuit.Figure 5 shows the ENC versus the gate voltage of theNMOS used as the feedback resistor at the CSA whenIBSLOW =
10 and 40 µ A. The feedback resistance in-creases along with an increase in the absolute value ofthe VGG, which leads to better noise performance, butat the expense of longer decay constants. In Figure 5,the ENC settles down when the noise from the NMOSbecomes negligible compared to that from other com-ponents. The best noise performance with the smallestENC = . − ± . − (rms) is achieved at the lowestvalue of IBSLOW = µ A. Figure 6 shows the waveforms at the slow shaper forvarious input charge under various IBSLOW. The wave-forms extend for smaller IBSLOW. This peak distortionis due to the behavior of the resistance circuit at the slowshaper. For smaller IBSLOW, the resistance circuit isapt to work in the slew-rate limited mode and can pro-vide small current, which limits the speed of the voltageat the output of the slow shaper. It is also observed thatnegative pulses make the waveform more distorted thanthat of positive pulses. This asymmetry is also causedby the resistance circuit where the input NMOS shows adi ff erent behavior as a response to positive and negativeinputs.Figure 7 shows the relation between the input chargeand the ADC value representing the amplitude of thesample-and-hold voltage from the slow shaper for var-ious IBSLOW. The results from a typical channel areplotted. The hold timing with respect to the hit tim-ing was 3 . µ s for IBSLOW ≥ µ A and 5 . µ s forIBSLOW = µ A. The gain dispersion was 3-8 % in4 V o l t age ( m V ) IBSLOW=120 µAQin=0.99 fCQin=3.18 fCQin=5.37 fCQin=7.56 fC Qin=-1.20 fCQin=-3.39 fCQin=-5.58 fCQin=-7.77 fC V o l t age ( m V ) IBSLOW=40 µA
Time (µs) V o l t age ( m V ) IBSLOW=20 µA
Figure 6: Waveforms at the output of the slow shaper for various inputcharge under various IBSLOW. one-sigma among the 56 channels. The dynamic rangewas found to be ∼ . = µ A and be-came smaller following the decrease in IBSLOW, reach-ing ∼ . = µ A. This trend canbe well explained by the behavior of the resistance cir-cuit at the slow shaper and the sample-and-hold circuit.Since in the sample-and-hold circuit the voltage is sam-pled at a given time after the hit signal is issued, it isimpossible to correctly capture the peak if it moves withthe signal charge.
The spectra in Figure 8 were acquired using the CdTedetector with
Am, Co and
Ba sources, where thedetector was biased at 1000 V and cooled at − ◦ C. Theslow shaper was selected as the input of the ADC, andthe reference current was set at IBSLOW = µ A. Weconfirmed the detection of photons whose energy rangesfrom 6 . . . .
12 keV. We alsofound that energy resolution becomes worse as the peakenergy increases, which we will investigate further.Figure 9 shows the spectrum acquired using an
Amsource, where the Si detector was biased at 80 V andcooled at − ◦ C. The slow shaper was selected as theinput of the ADC, and the reference current was set atIBSLOW = µ A. The energy resolution was found tobe 1 . .
4. New low-noise readout architecture
According to the results reported in Section 3.2 and3.3, the slew-rate limited mode o ff ers better noise per-formance with some penalty in the dynamic range as A DC () IBSLOW=10 AIBSLOW=40 AIBSLOW=78 AIBSLOW=120 A0 1 2 3 4 5 6 7 8 9 10
Input charge (fC) R e s i dua l ( % ) Figure 7: The upper plot shows ADC values with the input from theslow shaper with respect to the input charge of a channel for di ff erentIBSLOW values. The data are fitted over the dynamic range for eachIBSLOW value. Residuals are defined as the di ff erence of the mea-surement divided by the saturated ADC value, and are shown in thelower plot. The signals with negative polarity are used. long as the sample-and-hold circuit is employed. Fig-ure 10 shows the peaking time and the peak amplitudewith respect to the negative input charge. The peak-ing time gets longer as the input charge increases whenthe slow shaper works in the slew-rate limited mode,while the peak voltage maintains the linearity regard-less of the mode for the input charge up to and above8 fC. This implies that the combination of the slew-ratelimited mode and the peak detector circuit should sat-isfy both the noise performance and the wide dynamicrange.On the other hand, it should be noted that there ex-ist some reservations to employ the peak detector cir-cuit with the slew-rate limited mode. This architecturemakes it hard to detect the common mode noise. Caremust be taken so that the AD conversion starts after thevoltage reaches its peak for the largest signal to be tar-geted. In addition, the peaking time reflects noise per-formance. These matters must be taken into account inemploying this architecture.
5. Summary
The KW04H64 ASIC has been designed for the read-out of CdTe DSD allowing for high spectroscopic imag-ing. Evaluating its performance experimentally, the lownoise performance, ENC of 54 . − ± . − (rms), hasbeen demonstrated without any detector. From the eval-uation of the spectroscopic performance using the CdTesingle-sided detector, the ASIC demonstrated the high5
10 20 30 40 50 60 70 80
Energy (keV) C oun t () hist_sh_ene036hist_sh_ene036 @59.5 keV1.12 keV @13.9 keV Am Energy (keV) C oun t () hist_sh_ene034hist_sh_ene034 @122.1 keV Co Energy (keV) C oun t () hist_sh_ene025hist_sh_ene025 @30.6, 31.0 keV2.42 keV @81.0 keV Ba Figure 8: Energy spectra acquired with various sources from one channel where only single hit events were extractred. C oun t hist_cmn026 hist_cmn_sh_026 C oun t hist_cmn026 C oun t hist_cmn026 FWHM 1.2 keV @59.5 keV13.9 keV14 keV6.4 keV Co Am Figure 9: Energy spectrum acquired using an
Am source from onechannel where only single hit events were extractred. The horizontalaxis represents the value of ADC subtracted by common mode noise. P ea k i ng t i m e ( µ s ) Input charge (fC) P ea k a m p li t ude ( m V ) IBSLOW=10 µAIBSLOW=20 µAIBSLOW=30 µAIBSLOW=40 µAIBSLOW=78 µAIBSLOW=120 µA
Figure 10: Peaking time and amplitude with respect to the test pulsenegative input charge for di ff erent IBSLOW values. The peaking timeis defined as the time when the waveform reaches its minimum value. energy resolution of 1 .
12 keV for the energy at 13 . . .
6. Acknowledgement
This work was supported by JSPS KAKENHI grantnumber 18H05463. The authors thank P. Caradonna forhis critical reading of the manuscript.
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