Development of a Predictive Process Design kit for15-nm FinFETs: FreePDK15
11 Development of a Predictive Process Design kit for15-nm FinFETs: FreePDK15
Kirti Bhanushali, Chinmay Tembe, and W. Rhett Davis
Abstract —FinFETs are predicted to advance semiconductorscaling for sub-20nm devices. In order to support their intro-duction into research and universities it is crucial to develop anopen source predictive process design kit. This paper discussesin detail the design process for such a kit for 15nm FinFETdevices, called the FreePDK15. The kit consists of a layerstack with thirteen-metal layers based on hierarchical-scalingused in ASIC architecture, Middle-of-Line local interconnectlayers and a set of Front-End-of-Line layers. The physical andgeometrical properties of these layers are defined and theseproperties determine the density and parasitics of the design. Thedesign rules are laid down considering additional guidelines forprocess variability, challenges involved in FinFET fabrication anda unique set of design rules are developed for critical dimensions.Layout extraction including modified rules for determining thegeometrical characteristics of FinFET layouts are implementedand discussed to obtain successful Layout Versus Schematicchecks for a set of layouts. Moreover, additional parasiticcomponents of a standard FinFET device are analyzed andthe parasitic extraction of sample layouts is performed. Theseextraction results are then compared and assessed against thevalidation models.
Index Terms —FreePDK, FinFET 15nm, Process Design Kit,Middle-of-Line layers, DRC, LVS, parasitic extraction.
I. I
NTRODUCTION
The International Technology Roadmap for Semiconductors(ITRS) forecasts the physical length of the transistors toscale down to 16nm by 2016 [1]. However, the scaling ofbulk MOS technology for sub-20nm transistors has facedmajor problems - these include high leakage power, randomdopant fluctuations, Drain-Induced-Barrier-Lowering (DIBL)and other short channel effects. An alternative device calleda FinFET has emerged, and it has been demonstrated toadvance scaling of seminconductor technology beyond 20-nmprocesses. FinFETs achieve lower sub-threshold leakage andimproved short channel characteristics due to an advancedthree dimensional multi-gate geometry. Further, due to animproved gate control and a depleted thin fin structure, theyachieve better short channel performance and have lowerrandom dopant fluctuation [2].The Process design kits (PDKs) for these technologies havealready been developed for commercial FinFET processes atthe 14 nm. However, these processes are not readily availablefor the university education purposes due to the critical natureof intellectual property. Additionally, a large investment isrequired for licensing these processes, which is beyond thescope of universities. Thus, there is an immediate need fordevelopment of an open source predictive process design kitto help students gain a detailed understanding of standard design processes. The development of FreePDK15, is thus astep towards achieving a complete predictive process design.In this paper, the development of an entire metal layerstack based on the ITRS [1] estimates has been presented.The standard FinFET layout is evaluated from the pointof view of fabrication and design rules. Additionally, dueto limitations of the standard photo-lithography processes,state-of-the-art techniques like double-patterning lithographyhave been assumed for critical dimensions. Moreover, cutmasks and Middle-of-Line (MOL) layers are facilitated toenhance cell density and thus require special design rules. Tovalidate these design rules, layouts of an Inverter, NAND4,and their cascaded cells have been designed and their densityis evaluated. A set of the formulae required to accuratelyidentify and calculate the source and drain dimensions of theFinFET layout are presented. Additionally, layout extractionrules for double patterning, metal stitching and gate cut layersare implemented and validated. The parasitic characteristicsof a standard FinFET device are studied and the extractionrules for parasitic capacitance and resistance are implemented.The extraction of a set of standard layouts is compared andassessed against first order capacitance and resistance modelsfor metal layers.This paper discusses the intermediate steps involved in thedevelopment of process design kit FreePDK15. In section II,the layers used for the PDK are discussed. In section III,a standard FinFET layout cell is presented and the designrules for these layouts are explained in section IV. SectionV discusses steps involved in layout extraction. In section VIparasitic extraction and validation is discussed and the paperis concluded in section VII.II. F
REE
PDK15 L
AYER STACK
The layer stack for FreePDK15 is developed consideringmultiple factors, including multi-pattern lithography, metalstitching, dense routing and improvement of contact resis-tances. The layer stack includes additional layers to ac-commodate for the three-dimensional nature of the FinFETdevice and the layer properties follow the predictions from theInternational Technology Roadmap for Semiconductors 2011for the 2016 node [3].The standard cross-section for a FinFET can be seen inFigure 1. The cross-section indicates the use of Middle-Of-Line (MOL) layers along with the standard Back-End-Of-Line(BEOL) layers, and Front-End-Of-Line(FEOL) layers. a r X i v : . [ c s . A R ] S e p Fig. 1: Cross Section of a FinFET device
A. BEOL Layers
The ITRS-2011 tables for the 2016 node predicts use of 13metal layers. The metal layer stack thus includes 13 layers andfollows hierarchical scaling used for standard ASIC architec-ture [3]. This is further divided into Metal1 layer, Intermediatemetal layers, Semi-Global metal layers and Global metallayers. Fig. 2: MOL layers used as interconnects
B. Middle-of-Line Layers
The MOL layers act as an interface between FEOL layerslike ACT and BEOL layers like Metal1. The MOL layers areimplemented for overcoming electrical resistance concerns andthe loss of performance between inter-connected layers [4]. Al-though the concept of MOL layers has been studied in the pastthe primary inspiration behind their use for FreePDK15 comesfrom [5]. In [5] 14nm bulk FinFET standard cells have beenimplemented and the impact of MOL layers, local interconnectlayers IM1 and IM2, on cell parasitics is analyzed. MOL layerscan be used for connecting internal nets as indicated in Figure2. Thus these layers help in achieving denser layouts with theprovision for connecting internal nets, internal devices as wellas providing connection to the power rails. This eliminatesthe use of Metal1 layer for internal routing and thus thatof additional contacts/vias.The function of all MOL layers islisted in Table I.
C. Double patterning and other techniques1) Double patterning:
Fabrication beyond 20nm involvesmultiple challenges, primarily from the standpoint of photo-lithography as the gate pitch is much smaller. It is verydifficult to fabricate devices using the standard 193nm ArgonFlouride (ArF) lasers. We also assume that Extreme Ultra-Violet (EUV) lithography is not used in this process because it has not been able to achieve the desired yield for volumeproduction. Instead, double patterning is the technique as-sumed for FreePDK15, since it achieves greater pitch densitycompared to standard single-patterning lithography. This isdue to superior contrast obtained from exposed and unexposedareas. In principle, the layout is decomposed into two masks,each with different colors each with half the pattern to beprinted. In FreePDK15 this is implemented by providing twodifferent colored layers for layers with critical dimensions, likelower metal layers and gate layer.For example, in FreePDK15, double patterning is assumedfor gate layers. GATEA and GATEB are two differentlycolored gate layers
2) Cut layers:
In addition to these layers, FreePDK15also consists of a Gate Cut mask/cut layer called GATECto remove unwanted features printed by its preceding mask.This helps in printing non-uniform device structures and inovercoming errors due to mask misalignment. It is used tobreak connectivity between gate layers that are continuous.It is very convenient to form long GATEA/GATEB/GATEABshapes and then create multiple individual gate shapes by usinga grid of GATEC layers, rather than patterning multiple gateshapes at specific places on the wafer.III. F IN FET L
AYOUT ABSTRACTIONS / APPROACHES
As the FinFET device has three-dimensional thin finsturcture, it requires additional fabrication steps compared toa standard planar MOSFET. These differences are primarilydue to width quantization and use of MOL Layers.Fig. 3: Basic transistor layouts (a) Planar MOS (b) FinFET(c) Physical Mask - FinFET
TABLE I: MOL layers and their functions
Layer PurposeActive Interconnect Layer-1 (AIL1) Connecting individual finsActive Interconnect Layer-2 (AIL2) Connecting AIL-1 to Metal-1 through a viaGate Interconnect Layer (GIL) Connecting Gate to Metal1
Fig. 4: Dummy gates for process uniformity and DPL
A. Single FinFET transistor
The layout of a single planar MOS transistor with width Wand gate length L is presented in Fig 3.a. The active layer has adirect contact to Metal1 layer for the planar MOS. But, in thelayout of a FinFET transistor, contact is established throughlocal interconnect layers. Figure 3.b shows the representationof the FinFET layout drawn in the design tool, however, dueto the quantization of the fin width the device structure on thephysical mask looks different and is illustrated in Fig.3In order to ensure process uniformity [6] in sub-20nmtransistors “dummy” gates are also printed at the end of theFins as seen in Figure 4. Moreover, GATEA and GATEB havedifferent patterns for double patterning lithographyIV. D
ESIGN RULE DEVELOPMENT
The design rules define the basic geometric and connectivityrestrictions for a device technology and are thus importantto its development. They ensure sufficient margins againstmanufacturing process variability. In addition to that theyhelp the designer in verification of the design before it issent for fabrication. Violations of these rules can result inundesirable operation of the circuits, thus they are criticalto the circuit reliability. Furthermore, these design rules arecrucial in defining the density of the integrated circuit asnon-optimum design rules would result in wastage of criticaldesign space. Also, with the use of emerging technologies likeFinFETs, it is necessary to introduce new sets of design rulesto efficiently achieve correct functionality.Typically, the number of design rules can vary from fewhundreds to thousands. The design rules for FreePDK15 areimplemented considering the geometric, electrical and litho-graphic constraints. They incorporate standard minimum widthand spacing rules, along with certain restrictive design rules.
A. Standard design rules
The standard design rules are listed in Table II TABLE II: Standard design rules and their functions
Rule FunctionMinimum width Defined by the resolution of the lithographicprocess used, prevents open-circuits.Minimum Spac-ing Ensure electrical isolation between two shapesEnclosure Prevent overlay errors due to misalignment oflayersOverlap Ensure reliability during misalignment of layersArea Ensure adhesion and prevent overlay errors
B. Advanced design rules
These rules are specific to FinFET layout and doublepatterning lithography.Fig. 5: Width quantization of the active layer
1) Incremental width rule: Active:
The incremental widthrule is introduced due to the discrete nature of the FinFETwidth. The total width of a FinFET device is defined by thenumber of fins in the device and thus can only increase indiscrete steps. As it can be seen in Figure 5 the active widthcan only increment in steps of 40nm, which is the pitch of theactive layer [7].Fig. 6: Different pitch rules for different layers
2) Multi-colored design rules:
A distinct feature of devicefabrication in the sub-20nm technology is implementation ofmulti-patterning lithography. In FreePDK15 double patterninglithography (DPL) is assumed. It is thus necessary to use
Fig. 7: Standard inverter cell-FreePDK15different rules for different colored metal layers. Figure 6shows that the required minimum pitch between two similarmetal layers, Metal1A layers in this case, is bigger than theminimum required pitch between metal layers of differentcolors, Metal1A and Metal1B.
3) Restrictive design rules:
Restrictive design rules areintroduced to maintain the conventional design methodologieswith introduction of a new set of restrictions. An example ofrestrictive design rule is allowing only discrete gate lengths.Another example is restriction of jogs and bends in gatelayers as it can result in pinching [8]. However, as this rulecauses an increase in the overall area of the layout, it is onlyimplemented for critical dimensions.
C. Design rule validation
The design rules for FreePDK15 are predictive at best andneed further validation. A set of layouts were drawn and adesign rule check was performed on them for validating theserules [ ? ], [9] .
1) Inverter cell:
A standard minimum sized FreePDK15Inverter cell is presented in Figure 7. It uses AIL-2 forconnecting the internal nets and power rails. Additionally,GATEA and GATEB are implemented for process uniformity[9], [10]. Fig. 8: Standard NAND4 cell-FreePDK15
2) NAND4 cell:
A standard NAND4 cell shown in Figure8 consists of double colored metal1 layer for layout density;the design rules were further validated by running design rulechecks. Fig. 9: Tiled Inverter layout-FreePDK15Fig. 10: Tiled NAND4 layout-FreePDK15Fig. 11: Minimum sized inverter for 45nm bulk CMOS tech-nology(FreePDK45)
3) Tiled cells:
Tiled Inverter and NAND4 layouts presentedin Figure 9 and Figure 10 resp. are also designed for validatingthe design rules of higher order metal layers.
4) Layout density comparison:
The area of minimum sizedFinFET inverter is compared with the standard bulk MOSinverter designed using 45nm bulk FreePDK45 [11] [9] pro-cess in order to evaluate the layout density of the FinFETprocess. The layout density in FinFETs does not scale as inbulk MOSFETs. In [12] the layout density for a FinFET designis found to be 1.3 times that for the bulk process at the sameprocess node of 65nm. The primary reason for this can beattributed to the area overhead and width quantization issue inFinFETs.The area of a standard CMOS bulk technology(FreePDK45)as shown in Figure 11 was compared with the FeePDKInverter. The area shrink factor of 45nm CMOS inverter to15nm FinFET inverter was found to be around 1/6.V. L
AYOUT EXTRACTION AND D EVICE RECOGNITION
A crucial element in the development of the process designkit is error-free layout extraction. Layout extraction involvesboth device recognition and connectivity extraction, and itsoutput is a netlist that contains connectivity informationof all the recognized devices. Thus, layout extraction rulesfor FreePDK15 have been developed for transistor devicesNFinFETs and PFinFETs, however, no passive structures aredefined yet [13].
A. Device recognition: Bulk MOS vs FinFET
The shift from traditional bulk planar CMOS devices toFinFETs cause problems in device recognition. In contrast tothe planar devices, FinFETs have a three dimensional foldingof gate layer over the fin which adds to the complexity ofcreating layouts. However, as indicated in section III, thelayout of a FinFET device is drawn similar to planar deviceswith a few exceptions. The comparison of a standard NMOSlayout in FreePDK45 and an NFinFET in FreePDK15 is shownin Figure 12. However, this doesn’t account for the multi-finnature of the FinFETs which results in modification of theformulae used for calculating source and drain dimensionsof the FinFET device. Additionally, the gate length is onlyrestricted to 14, 16 and 20 nm. In most cases a single lengthof 16nm would be enforced, but it is possible that the criticaldimensions of all devices may be lengthened to 20 nm orshortened to 14 nm across the entire wafer.It is also very important to correctly extract the drain andsource dimensions i.e. the area, and perimeter, as they definethe parasitic source and drain capacitances.
1) Source and Drain dimensions: Planar MOS:
The formu-lae used for estimating the areas ( A D , A S ) and the perimeters( P D , P S ) of source and drain for planar devices from [14] aregiven below. A D = A S = W ∗ L D/S (1) P D = P S = 2 ∗ L D/S + W (2)
2) Source and Drain dimensions: FinFET:
For bulk Fin-FET devices, the drain and source area is represented by
ADEJ , and
ASEJ respectively, while the perimeter of the drainand source is represented by
PDEJ , and
PSEJ . The formulaefor these parameters account for the number of fins and areas shown in following equations [15].
ADEJ = ASEJ = n fin ∗ W fin ∗ L fin ( D/S ) (3) P DEJ = P SEJ = 2 ∗ L fin ( D/S ) ∗ n fin + W fin ∗ n fin (4) B. Layout Extraction rules
In order to accurately extract a layout, a layout vs schematic(LVS) rule file is defined. Its accuracy depends on the accuracyof the rule file with regards to device definition and extraction,and connectivity extraction. These rules are validated bycreating sample layouts and performing LVS checks on samplelayouts.FreePDK15 primarily follows the same LVS rules as definedfor bulk MOS technology, however, due to the definition ofMOL layers and introduction of cut-layers some of these rulesare modified.
C. MOL connectivity rules
Due to the introduction of the MOL layers the devicecontact rules are modified. As indicated in section II-B AIL1acts as the first local interconnect to active while GIL acts asthe first local interconnect to Gate. However, AIL2 can act aslocal interconnect layer to AIL1 as well as GIL. This providesmultiple device contact options: AIL1 - AIL2 - M1, GIL -M1or GIL - AIL2 - M1.
D. Gate Cut rules
Gate cut layer act as a negative mask and additional rulesare defined to identify break in connectivity if a gate cut(GATEC) layer is present. As shown in Figure 13, use ofGATEC facilitates denser layouts in case of four tiled invertersby breaking GATE connectivity where required.
E. Double patterning rules
BEOL rules concern the way in which metal layers areconnected. The connection of various metal layers is throughthe alternating via layers, as can be seen in the metal layerstack. For multiple patterned layers, all layers at the samelevel in the hierarchy, even with different colors, are treatedas identical for layout extraction and can be connected toany of the multiple patterned layers of higher or lower levelsof the hierarchy using the corresponding via. For example,intermediate metal layer MINT3, MINT3A, MINT3B areconsidered same and either of them can be connected toeither of MINT4, MINT4A or MINT4B using via VINT3.Similarly, they can be connected to either of MINT2, MINT2Aor MINT2B using via VINT2.FreePDK15 has been developed to allow metal stitching,which is a means to connect multiple patterned layers to (a) NMOS Layout: FreePDK45 (b) NFinFET Layout: FreePDK15
Fig. 12: Comparison of NFinFET and NMOS layoutFig. 13: GATEC for breaking connectivity between Inverterseach other in order to save area. For example, MINT5 canconnect to both MINT5A and MINT5B and vice versa. Insituations where there are multiple violations to design rules,specifically spacing rules, instead of modifying the layout toincrease the area, multiple patterned layers can be used tocolor different nets and wherever required metal stitching canbe used to short two colors (two nets). This is illustrated inFigure 14. The metal stitched layout in figure 14(b) permitsa smaller spacing between the ZN, VDD, and VDD 2 netsthan would be possible if the ZN net were drawn with onecolor. The downside of metal-stitching, however, is reduced predictabilty of wire parasitics and possibly increased chancesof a manufacturing defect.VI. P
ARASITIC E XTRACTION
Another important component of the process design kit isthe capability to correctly extract the interconnect and deviceparasitics. Parasitic extraction is an essential step in analyzingthe performance of the design and parasitic capacitance andresistance of the layout are essentially defined by the followinglayer characteristics:1) Geometrical characteristics: Minimum-drawn widths,spacing and layer thickness, via enclosures, and trape-zoidal shapes for layers.2) Electrical properties: Resistivities (or sheet resistances),permittivities for various dielectric layers (dielectric con-stants), via and contact resistances.For FreePDK15, the layer definitions and the characteristicsare defined in a technology file or .mipt file and the MentorGrpahics’ Calibre xCalibrate and Calibre xRC tools are uti-lized for parasitic extraction.
A. Layer properties
The values for widths and pitches for various metal layerswere derived from the Interconnect tables from ITRS 2011predictions for the 2016 node [3] . However, ITRS-2011 pre-dictions are more aggressive for metal1 and intermediate metallayer scaling than existing 15 nm processes [5]. Therefore, theminimum width for the metal1 layer, which is often assumedto be roughly 1.5 times the minimum gate length, is assumedto be 28 nm, which is twice that of the minimum gate length.Similarly, the dimensions of the intermediate metal layers arebased on this assumption, while the semi-global and globallayer dimensions are derived from the ITRS-2011 tables. The (a) Spacing violations between VDD and VDD 2 preventingdenser layouts (b) Metal stitching permitting denser layouts due to use ofdifferent color of VDD, ZN and VDD 2 nets
Fig. 14: Metal stitching resolves spacing violations and facilitates denser layoutselectrical and geometrical characteristics of the layer stack arelisted in Table III and TableIV. This stack was chosen to follow[5] while filling in the gaps with materials that provide theapproximate resistivity and dielectric constants predicted byITRS. TABLE III: BEOL Layer propertiesTherefore, Tetraethyl Orthosilicate (TEOS) is selected as thedielectric surrounding the metal layers, while Silicon Nitride(SiN) is selected as the dielectric surrounding all the FEOL andMOL Layers, with the exception of AIL2 which uses silicondioxide SiO . Additionally, the top of GIL layer has sameTABLE IV: FEOL and MOL Layer properties dielectric as AIL2 i.e. SiO and bottom has the same dielectricas AIL1 i.e. SiN.The appropriate identification of the metal stack is validatedby the output of the XCalibrate’s stack-viewer tool shown inFigure 15, while that for the FEOL and MOL stack is shownin Figure 16. B. Capacitance extraction of FinFET
The modeling of internal parasitics is highly complex dueto the three-dimensional nature of the FinFET structure. How-ever, the BSIM-CMG (for common multi-gate devices) [16]spice model developed by the BSIM group at UC Berkeleyaccounts for most of the internal device capacitances. How-ever, the fin rises above the substrate resulting in additionalcapacitance with the external layers.Figure 17 illustrates various capacitances associated witha FinFET device. As indicated in Table V, internal devicecapacitances like C sd , C gc top are accounted for in the BSIM-CMG [16] spice model. The other capacitances like contact-to-contact, gate to contact, and gate-to-substrate are accuratelyextracted through parasitic extraction process.The comparison of this model with the FreePDK15 showsthat the capacitances C gf top , C f1 , C cc and C gct are extracted bythe rules developed for FreePDK15. The capacitance C gf top isthe fringing capacitance for gate over fins, C f1 is the capac-itance between GATE/GIL and AIL1. C gct and C cc are againGIL to AIL1 and GIL to M1 (in case of a direct connection)respectively. In FinFET layouts, fins are not represented asthin strips, however, the width of the active area is defined asthe sum of fin width, and fin pitch times number of fins asshown in equation 5 W = W fin + ( n fin − ∗ P itch fin (5)Thus, due to the way in which the width is defined,capacitance C g1 is not currently modeled in FreePDK15. Ad-ditionally, these extracted capacitances have not been validatedas that can only be achieved by comparing these results againstresults from a complex simulation using a 3D field solver.Thus, the current kit only represents an approximate value ofthe extracted FinFET capacitances. (a) Intermediate metal layers and layer M1 (b) Semi-Global metal layers (c) Global metal layers Fig. 15: BEOL layer stack in Mentor Graphics’ Stack Viewer (a) Stack with poly and GIL (b) Stack with AIL1 and AIL2
Fig. 16: FEOL and MOL layer stacks in Mentor Graphics’ Stack Viewer (a) Cross-section view FinFET capacitance(b) Top view FinFET capaciitance
Fig. 17: Capacitance components of FinFET divided between Spice model and extracted netlist [17]TABLE V: FinFET capacitances [17]
Capacitances DomainContact to contact (Ccc) ExtractionGate to contact(C gct ) ExtractionGate to top of fin(C gf top ) ExtractionGate to substrate between fins(C g1 ) ExtractionGate to diffusion between fins(C f1 ) ExtractionSource to drain(C sd ) Spice modelGate to channel(C g ) Spice modelFin to substrate(C f ) Spice modelGate to fin inside channel(C gc top , C gc side ) Spice modelDiffusion to substrate(C diff ) Spice model C. Validation of parasitic extraction
The parasitic extraction process involves capacitive andresistive extraction of a given layout. The validation processincludes design of simple layout and the comparison of theirparasitics with first order models and approximations. Capac-itance validations include validation of parallel plate capac-itance, fringing capacitance and coupling capacitance, whileresistance validation includes comparison of sheet resistance.
1) Parallel plate approximation:
Capacitance betweencombination of metal layers of varying dimensions are com-pared against their parallel plate approximation model. It isfound that for larger dimensions extracted capacitance forthese metal layers matches the parallel plate capacitance.However, for smaller dimensions, (1um*1um) the differencebetween the extracted value and the estimated value wasas high as 100%. This difference is due to the fringingcapacitance which is not included in the parallel plate model,and starts dominating at lower dimensions.
2) Fringing capacitance modification:
In order to accountfor the Fringing capacitance, the parasitic capacitances arecompared against the total capacitance values obtained fromSakurai’s [18] and Chang’s [19] approximation. It is found thatthe estimated parasitics have a significantly lower variation( <
3) Inclusion of coupling capacitance:
Coupling capaci-tance also significantly contributes to the overall parasiticcapacitance of the layout, and thus in order to thoroughlyvalidate it, the total extracted capacitance must be comparedwith the model that accounts for the coupling capacitance. Theprocess of validation thus involves modifying the dimensionsand spacing between the metal layers and comparing thatagainst Sakurai’s approximation. It is found that the differencesignificantly improves ( <
4) Resistance validation:
Simple sheet resistance formulawas used to validate resistance extraction. The process involvesvarying the lengths and widths of different metal layer shapesand observing their effects on the extractes parasitic resistance.Sheet resistance values were calculated from the layer prop-erties table and were used to validate the resistance values.However, in modern chips, the metal layer often is substitutedfor silicides or mixture of metals with varying quantitiesis used, which cannot give a simple value of resistivity.Moreover, with effects like skin effect at higher frequencies,resistance varies with distance from surface and hence parasiticresistance validation is kept to this simple sanity check.Fig. 18: Chain of FO1 Inverters
5) Inverter chain example:
To analyze and evaluate thevalidity of the kit, the propagation delay for a set of circuitswere calculated and the results were compared with theestimated propagation delay from ITRS tables. The delay analysis was performed for nine-stage FO1 andFO4 Inverters and the average propogation delay for eachsingle stage was calculated. Also, the technology modelsused for the HSPICE simulations were PTMs 14 nm HighPerformance nfet and pfet models [20], which are based onthe BSIM models for common multi-gate devices [16].In order to study the impact of additional parasitics on thesemodels the following the propagation delay was computed foreach of the following cases1) Basic circuit based on only the spice models2) Circuit with source and drain dimensions defined. Thisenables inclusion of parasitic capacitance in the spicemodel.3) Circuit with extracted parasitic netlist for the corre-sponding circuit layout.From the delay analysis performed for these cases, it isfound that the addition of spice model parasitics as wellas inclusion of the parasitic extraction results increases thepropagation delay of the circuit. This is in agreement withthe estimated behavior of the circuit. Furthermore, anotherobjective of the delay analysis is to evaluate whether theresults obtained from the simulations have the same order ofmagnitude and are within the neighborhood of the propagationdelay predicted by ITRS. The simulation result for FO1Inverter is 1.81 ps, while that predicted by ITRS is 3 ps.Similarly, the result obtained for FO4 Inverter is 4.39 ps, whilethat predicted by ITRS is 7.18 ps [1]. This indicates that resultsare close to the predicted values.VII. C
ONCLUSIONS
The introduction of integrated circuit design using Fin-FET devices in university education is currently constraineddue to high licensing cost of the commercial design flows.FreePDK15 attempts to remove this constraints by provid-ing an open source predictive process design flow platformwherein circuits for 15 nm FinFET devices can be designedand verified. In this paper, a PDK is described which consistsof a layer stack based on existing FinFET designs and ITRSpredictions. The design rules encompassing special rules fordouble patterning lithography, gate cut layers and MOL layersare implemented.Since the geometrical characteristics of a FinFET layoutdiffer from that of a planar MOSFET, the modificationsrequired for correctly extracting the source and drain dimen-sions (accounting for the number of fins) and FinFET devicerecognition are executed. Additional rules requiring layoutextraction of interconnects because of double patterning andmetal stitching are introduced and validated.A study of the parasitic capacitance components of theFinFET device indicates additional capacitances due to thefolding of gate over channel. However, due to the mannerin which the current layouts are drawn all the parasiticcomponents have not been accounted for and would requirefurtherl complex modeling of the 3D gate structure. However,the interconnect capacitances and resistances are validatedagainst standard models and are found to be closer to theestimated values. The complete design flow is proven by TABLE VI: Propogation delay for Inverter chains
Circuit tp - PTM a (ps) tp - S/D specified b (ps) tp - extracted c (ps)FO1 Inverter 1.28 1.75 1.80FO4 Inverter 3.94 4.30 4.39 Single stage propagation delay for circuit based on spice models. Single stage propagation delay for circuit with source and drain dimensions specified Single stage propagation delay for circuit with layout extracted netlist running simulations on extracted netlists of FO1 and FO4Inverters and the propagation delay results of these simulationswere found within the vicinity of the results predicted byITRS-2011 tables for 2016 node.A
CKNOWLEDGMENT
The authors would like to thank Paul Franzon at NC StateUniversity. The authors would like to thank Mentor Graphics,since this project would not have been possible without theirgenerous gift of supporting funds and Calibre licenses. Theauthors would also like to thank Tarek Ramadan, AhmedHammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, HendWagieh and the team at Mentor Graphics for developmentof the first set of design rules and their constant support.Inaddition, the authors would like to thank and acknowledgeAlexandre Toniolo at Nangate for clarifying the vision of MOLlayers. We would also like to thank Cadence designsystems foruse of the virtuoso software and Synopsys Inc.for use of Pycellstudio. The authors would also like to thanks Vikas Sharmafor P-Cells, Vidyanandgouda Patil for design rule fixes andNamrata Sampat for help cleaning up the distribution.R
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