Device Variability Analysis for Memristive Material Implication
11 Device Variability Analysis forMemristive Material Implication
Simon Michael Laube and Nima TaheriNejad
Abstract —Currently, memristor devices suffer from variabilitybetween devices and from cycle to cycle. In this work, westudy the impact of device variations on memristive MaterialImplication (IMPLY). New constraints for different parametersand variables are analytically derived and compared to extensivesimulation results, covering single gate and 1T1R crossbarstructures. We show that a static analysis based on switchingconditions is not sufficient for an overall assessment of robustnessagainst device variability. Furthermore, we outline parameterranges within which the IMPLY gate is predicted to producecorrect output values. Our study shows that threshold voltageis the most critical parameter. This work helps scientists andengineers to understand the pitfalls of designing reliable IMPLY-based calculation units better and design them with more ease.Moreover, these analyses can be used to determine whether acertain memristor technology is suitable for implementation ofIMPLY-based circuits and systems.
Index Terms —Memristor, ReRAM, Material Implication, IM-PLY, Logic, In-Memory Computation, Variation, Robustness,Analytical Studies, Simulations.
I. I
NTRODUCTION
Memristors are used for memory applications [1]–[5], whereeven storage of multiple bits per device is feasible [6]–[9].In addition, memristors have become increasingly popular forneural network and learning applications [10], [11], by exploit-ing their analog, synapses-like nature. Another application ofmemristors is implementing digital (in-memory) logic [12]–[14], such as IMPLY, for various computations [15]–[20].At the moment these applications – more often than not –are not verified by physical implementation and experimentaldata [21]. This imbalance leads to many problems when actualphysical implementation is desired. While material scienceshave certainly progressed in this field [22]–[24], the circuit-level interface to higher abstraction levels is not yet ready toprovide a reliable base for proposed applications [21]. Some ofthe fundamental problems, that need to be considered at designtime, are inter-device variability and cyclic variability. In largerstructures, usually implemented within crossbar arrays, sneakpaths and wire resistance are an even bigger issue [25], [26].While the two latter have received an acceptable level ofattention from the community, the two former have been lessexplored and addressed by the community. We hope that thiswork encourages and provides pointers to the community tomove in that direction.
S. M. Laube and N. TaheriNejad are with the TU Wien, 1040 Vienna,AustriaThis work has been submitted to the IEEE for possible publication.Copyright may be transferred without notice, after which this version mayno longer be accessible.
Here, we aim to provide a better insight into the operation ofa single memristive IMPLY logic gate by considering devicevariations. Similar works on that topic already exist, suchas [27]–[29], which mainly focus on other types of memristor-based logic. The most relevant work to ours is [29], where thefocus is set on the design of the IMPLY circuit itself, andan alternative operation “NOT IMPLY (NIMP)” is proposedto mitigate certain problems. In contrast, our work exploresregular IMPLY in more detail, particularly regarding the effectof device variations on the IMPLY operation, and leaves theNIMP approach for future works. We note that there is avariety of memristors based on different physical effects [22].From the perspective of this work, the internal mechanism isto a large extent inconsequential. Hence, we use the generalterm, memristor, to refer to resistive switching elements orResistive Random Access Memorys (ReRAMs) and, whenneeded, specify what may make the internal mechanismsimportant. The main contribution of this work to the field ofmemristor-based logic, is an in-depth mathematical analysisof memristive IMPLY regarding its constraints due to devicevariation. Plausibility of the proposed constraints is verifiedvia simulations using a popular model.The rest of this paper is organized as follows: Section II,particularly Section II-A, reviews memristive IMPLY logicand shows its limitations. An introduction to the crossbararchitecture is given in Section II-B and the device modelis described in Section III. In Section IV, we formulate newconstraints for the IMPLY gate, before comparing them to thesingle gate simulation results in Section V. The results of thecrossbar simulations are presented in Section VI and comparedagainst the single gate simulation and constraints. We concludethe paper in Section VII.II. M
ATERIAL IMPLICATION (IMPLY)The truth table of IMPLY, and its four different cases,are shown in Table I. It takes two input states p and q andoutputs q (cid:48) . Not every type of memristor is suitable for materialimplication. The devices have to exhibit voltage thresholdbehavior . Moreover, all devices used for an operation shallhave the same parameter values (resistance range, thresholdvoltages, switching speed). A. Gate structure and constraints
Two memristors and a resistor are necessary for a singlememristive IMPLY gate. Figure 1(b) shows such a gate, withabstracted drivers and sense circuitry. Each memristor can be set (forced to Low Resistance State (LRS)) by applying a a r X i v : . [ c s . ET ] J a n Table IT
RUTH TABLE OF MATERIAL IMPLICATION AND ITS FOUR CASES
Cases p q q (cid:48)
Case 1 0 0 1Case 2 0 1 1Case 3 1 0 0Case 4 1 1 1 voltage | V set | > | v on | with appropriate (in our case negative )polarity; and can be reset (forced to High Resistance State(HRS)) by applying | V reset | > | v off | with an opposite polarity .If a memristor is set, it represents logic state ‘1’; if it is reset,it represents logic state ‘0’ [12]. During initialization, thesevoltage amplitudes are applied to each device, while the otheris kept floating. For the actual logic operation both devices aredriven at the same time: V cond is applied to node R and V set to node T of Figure 1(b). For a correct operation | V set | > | v on | (1) | V set − V cond | < | v on | (2) | V reset | > | v off | (3)must hold. Moreover, the circuit designer needs to select avalid value for R G , as described in [30].It is important to note that only in Case 1 of Table I theoutput memristor Q is actually changing its state. However,during this process the voltage across each device changestoo. It is valid to ask if this has an effect on the resultof the operation, and the answer is yes. Using Kirchhoff’scircuit laws (KCL), Chen et al. [29] showed that there are twopossible final steady states of the operation:1) The normalized state variable s reaches the upper bound-ary of ( R Q = R on ) before the voltage across Q falls below the threshold v on . The final steady state is R Q = R on .2) V Q falls below the threshold v on before s reaches . Inthis case the steady state resistance can be expressed as : R min = − v on R G R off ( R G + R off )( V set + v on ) − R G V cond (4) This is true for bipolar switching mechanisms. Phase Change (PC) baseddevices, for example, may use the same voltage polarity for set and reset. Note that in our convention v on < . i + v − (a) R G P R Q T Driver & Sensing + V P − + V Q − + V G − (b)Figure 1. (a) Memristor symbol and defined voltage polarity used in thiswork. (b) A single IMPLY gate. An important point to mention is that this calculation is basedon the premise, that the driving voltages of P and Q are chosensuch that there is no state drift in P during operation. B. Crossbar principles
Crossbar architectures are a natural candidate for memristor-based logic, as high integration density can be reached. In socalled 1R (or 1M) crossbars, a memristor device is fabricatedat each intersection of bit- and word-lines, which act as theaccess medium for the cell. 1R crossbars are very difficult tohandle [31]–[33], even if parasitics are not considered. Manyworks have been carried out to study effects [25], [34]–[36],or solve them [14], [26], [34], but thus far 1T1R has been thepreferred implementation [31]–[33]. 1T1R (or 1T1M) cross-bars,consist of a transistor and a memristor in each cell. Thetransistor in each cell cost extra area but they prevent the cellsfrom switching state when a cell is not part of an operation (notselected). One possible, readout scheme is provided by [26],which we use in this work. The chosen readout scheme [26]provides a closed-form solution. Moreover, it introduces verylittle additional complexity, which enables this work to remainfocused on issues regarding IMPLY itself. In Section VI wecompare crossbar simulation results against single gate resultsand outline the differences.III. D
EVICE MODEL
There are a range of different simulation models for memris-tors [37]–[40]. For the simulations presented in this paper, theTU Wien LTSpice implementation [21], [41] of VTEAM [38]was used. An overview of the model is given in Equations (5)to (9), with a memristor polarity as shown in Figure 1(a).In VTEAM, w acts as the state variable and represents alength between the extrema w on and w off ( w ∈ [ w off , w on ] ).Here, we define the relation of these state variable boundaries w on > w off (5)and define the normalized state variable ( s ∈ [0 , ): s ( w ) = w (cid:48) = w − w off w on − w off (6)These definitions may be changed, as long as the modelequations are updated, too. The rate of change of the statevariable, w , is defined by d w d t = k off (cid:16) vv off − (cid:17) α off f off ( w ) 0 < v off < v v on < v < v off k on (cid:16) vv on − (cid:17) α on f on ( w ) v < v on < (7)which is the essential building block of the model [38]. Inthis equation k on , k off , v on , v off , α on and α off representfitting parameters, while f on ( w ) as well as f off ( w ) are windowfunctions that limit d w/ d t . I/V -characteristics and window functions are not definedin the model and thus can be freely chosen. We chose a linearcurrent/voltage dependency: R ( w ) = R off + ( R on − R off ) · s ( w ) (8) By rearranging the equation we can further express s ( R ) forany (measured) R : s ( R ) = R − R off R on − R off (9)The same expressions as for the Simmon’s Tunnel Barriermodel in [37] were chosen as window functions. In addition, w is bounded and thus cannot exceed w on or w off .The studies presented in this paper are kept as general aspossible, however, simulations need model parameters. Ratherthan introducing arbitrary parameter values, we experimentallyfitted [18] our VTEAM model to Knowm BS-AF-W [42]memristors we had at the time. Parameters shown in Table III,represent a best effort fitting we conducted previously [18].IV. F ORMULATING C ONSTRAINTS
This section marks the beginning of our new contributions.In this section, we mathematically extract device variabilityconstraints which govern and limit operations of IMPLY. Atfirst, we define the notation: Each parameter involved in theanalysis is written as ξ i,M , where ξ ∈ { R, v, k } , M ∈ { P, Q } and i ∈ { off , on } . For example, the off-resistance of memristor P in this notation would be denoted as R off ,P .Logic thresholds determine the logic state of a device. Theyare defined separately for input (I) and output (O), as wellas logic ‘1’ (H) and ‘0’ (L). Indices are used to denote therespective logic thresholds, e.g. R IL is the input threshold forlogic ‘0’. A. Static behavior
Each case in the truth table (Table I) imposes constraintsonto the voltage V Q across memristor Q , as certain switchingconditions must be met. They can be analyzed via KCL andrepresent a static view of the circuit. The constraints can beused to find limits for R on ,P , R off ,P , v on ,Q and v off ,Q . They donot provide limits for R on ,Q or R off ,Q , as R Q in this contextis the target output resistance state that Q must reach duringIMPLY. Therefore, R Q is later set according to the chosenoutput logic threshold: R Q ≤ R OH or R Q ≥ R OL .ApplyingKCL in Figure 1(b) gives us the voltage across Q as V Q = R Q ( R P + R G ) V set − R Q R G V cond R P R G + R P R Q + R Q R G . (10)First we solve Equation (10) with a generalized thresholdvoltage, v , and the solution is specialized for each caseafterwards. The first switching condition is: V Q > v. (11)Plugging Equation (10) into Equation (11) and isolating R P leads to R P · b > a, (12)where a = R Q R G ( v + V cond − V set ) , (13) b = R Q V set − v ( R G + R Q ) . (14) At this point the relation in 12, is divided by b . Therefore,depending on the value of b , we have R P > ab if b > R P < ab if b < R P → ±∞ if b = 0 (15)Next, the switching condition V Q < v (16)is examined. Following the same steps as before, we have R P < ab if b > R P > ab if b < R P → ±∞ if b = 0 (17)Since the third case ( b = 0 ) in Equations (15) and (17) yields ±∞ , it is of no interest for the rest of the analysis. The firsttwo cases in Equations (15) and (17) both provide limits for v and R P , respectively.Here, the resulting equations (constraints) are specialized foreach of the four cases of the truth table using the respectiveswitching conditions. R Q is set to the associated output logicthreshold ( R OH or R OL ). Only the first case ( b > ) ofEquations (15) and (17) is considered, since the second case( b < ) only provides negative limits, and R P > . For everycase of the truth table, according to our notations, v on < and v off > . Hence, we have Case 1 V Q > − v on ,Q v on ,Q > − V set R OH R G + R OH (18) R off ,P > R OH R G ( V cond − v on ,Q − V set ) R OH V set + v on ,Q ( R G + R OH ) (19) Case 3: V Q < − v on ,Q v on ,Q > − V set R OL R G + R OL (20) R on ,P < R OL R G ( V cond − v on ,Q − V set ) R OL V set + v on ,Q ( R G + R OL ) (21) Case 2/Case 4: V Q > − v off ,Q v off ,Q > − V set R OH R G + R OH (22) R off ,P > R OH R G ( V cond − v off ,Q − V set ) R OH V set + v off ,Q ( R G + R OH ) (23) R on ,P > R OH R G ( V cond − v off ,Q − V set ) R OH V set + v off ,Q ( R G + R OH ) (24)Equations (18), (20) and (22) directly result from b > ,whereas Equations (19), (21), (23) and (24) are the respectiverelations derived from R P > a/b in Equation (15) and R P < a/b in Equation (17). That is, as long as | a | is neither zero, nor ∞ . tV Q V Q i V Q f ∆ T (a) t ∆ w Q ∆ T (b)Figure 2. A symbolic voltage-time curve for V Q (a) an induced statechange ∆ w Q (b) during a single IMPLY operation of duration ∆ T . Theestimations for the formulation of constraints are drawn in orange, thesymbolic representations of the actual curves in black. Some additional static constraints are given by the choiceof logic thresholds. That is, R off ,P > R IL (25) R off ,Q > R IL (26) R on ,P < R IH (27) R on ,Q < R IH . (28)Similar to standard logic families, input and output thresholdsmay differ. From the point-of-view of these constraints, onlyinput thresholds need to be considered, as they determinewhether or not the device states fed to the operation are validin the first place. B. Dynamic behavior
With respect to the static analysis, the chosen timestep ofoperation can introduce much stricter constraints. For exact so-lutions, one would have to solve the differential state equationof the chosen model (in our case Equation (7) from VTEAM).This is not a trivial task and might not even be possible forall models. Thus, in this section we derive a lower boundaryfor v on ,Q , but not the infimum, which cannot be exceededby the exact (or numeric) solution. That way we take intoaccount the state change (dynamic behavior) of memristorsduring the operation, using an acceptable estimation. We notethat in doing such an analysis, the chosen model is assumed tobe accurate. However, in practice no existing model representsall the reality and physics involved.The main idea of our estimation is to look at how V Q changes over time in Case 1 of the truth table, while assumingnegligible state drift in P . As R Q changes from HRS to LRS, V Q decreases. Thus, the initial voltage V Q i is the highestoccurring value of V Q during that timestep, while the finalvoltage V Q f is the lowest – symbolically shown in Figure 2(a).If the device characteristics are such that the highest V Q corresponds to the maximum value of d w/ d t – in our casetrue due to Equation (7) – a hard limit can be expressed. KCLcan be used to describe the initial voltage V Q i = R off ,Q ( R off ,P + R G ) V set − R off ,Q R G V cond R off ,P R G + R off ,P R off ,Q + R off ,Q R G . (29) Plugging V Q i into Equation (7) gives the inital rate of statechange : d w Q d t (cid:12)(cid:12)(cid:12)(cid:12) initial = ∆ w Q ∆ T = k on ,Q (cid:18) − V Q i v on ,Q − (cid:19) α (30)Now we set the actual d w Q / d t equal to the initial rate for thewhole timestep ∆ T . Through this simplification a maximum ∆ w Q for the given timestep ∆ T can be found, which cannotbe exceeded: ∆ w Q = k on ,Q (cid:18) − V Q i v on ,Q − (cid:19) α ∆ T (31)This is because the estimation provides a better overall situ-ation towards the correct operation result, when compared tothe actual situation. That is, as we see in Figure 2(b), theestimated ∆ w Q is always larger than the actual value. Toobtain a correct result after the IMPLY operation, R Q mustat least reach the logic threshold R OH . Otherwise the resultwould not be interpreted as logic ‘1’. Via Equation (9) we canfind s ( R OH ) . In combination with Equation (6), the necessary ∆ w min can be expressed as ∆ w min = R OH − R off ,Q R on ,Q − R off ,Q ( w on − w off ) + w off , (32)and ∆ w Q ≥ ∆ w min (33)shall be true. Plugging the previous terms into Equation (33)gives v on ,Q ≥ − V Q i α (cid:113) ∆ w min k on ,Q ∆ T + 1 , (34)which is the newly found constraint. As this relation containsmultiple parameters of P and Q apart from v on ,Q , it providesboundaries for all of them. For example, a certain v on ,Q restricts R off ,P to a specific range, and in turn a certain R off ,P restricts v on ,Q to a specific range.Considering Equation (34), a question is whether the sameestimation could be used to find an upper limit for v on ,Q . Suchan analysis, however, is not meaningful for memristor Q . Both,a minimum value of d w/ d t and a maximum value ∆ w max ,must be specified. The later does not exist for Q since a high w Q (ideally w on ) is desired in Case 1.There is, however, a ∆ w max for memristor P , as a changeof R P is generally not desired. By definition the logic stateof P remains unchanged if R P > R IL . Only if this is true, itcan be used as an input for an operation. As R P drifts awayfrom R off ,P (ideal HRS), V P decreases. Thus, the minimumvalue of d w/ d t is the final value at the end of the operation,in contrast to V Q i being the initial value. The final value V P f cannot be expressed easily, as R P f and R Q f are unknown.Hence, another simplification must be made: We evaluate V P f using R P = R off ,P , as if there was no state drift in the firstplace: V P f ,j = R off ,P ( R Q,j + R G ) V cond − R off ,P R G V set R off ,P R G + R off ,P R Q,j + R Q,j R G (35) f on is missing in Equation (30) because f on ≈ for w Q < w on Due to this very rough estimation, we expect the constraint torepresent a fairly weak boundary. Therefore, R Q, = R min ,Q (36) R Q, = R off ,Q + R min ,Q (37) R Q, = (cid:112) R off ,Q · R min ,Q (38)are used to evaluate V P f in Equation (35) and obtain arange within which the circuit is less likely to fail. Thefirst value, Equation (36), is the theoretical minimum for R on ,Q , which is the ideal R Q f . However, the actual R Q, f cantake on any value between R off ,Q and R min ,Q . Hence, in asecond estimation, Equation (37), we assume that R Q f is thearithmetic mean of R off ,Q and R min ,Q . In other words, thefinal state is halfway between the initial state and the idealendstate ( R min ,Q ). However, if V P f is plotted over R Q on alinear scale, it reveals that the dependence is non-linear. Thus, R Q, might not be the best estimation either. The dependenceis, nevertheless, approximately linear on a semi-logarithmicscale; so our third estimation, Equation (38), assumes R Q f tobe the geometric mean of R off ,Q and R min ,Q . If the timestep ofIMPLY operation is limited, we do not expect R Q, to providean appropriate estimation, since this is the overall optimumscenario. R Q, and R Q, might both be of value to the circuitdesigner, because they represent a non-ideal scenario, chosenbased on design parameters.Following the same steps as before, we can formulate theconstraint for v on ,P : ∆ w P = k on ,P (cid:18) − V P f ,j v on ,P − (cid:19) α ∆ T (39) ∆ w P ≤ ∆ w max (40) v on ,P ≤ − V P f ,jα (cid:113) ∆ w max k on ,P ∆ T + 1 (41)Table II provides a summary of relevant constraints on memris-tor parameters, that were derived in this section. Most of theserelations depend on multiple parameters of both memristors.Thus, the permissible value range of one parameter is impactedby the values of other parameters, and vice versa. Once thevalue of a parameter is determined (either decided by thedesigner or given by the technology) respective equations inTable II determine the tolerable range of variation in others.This bidirectional view enables us to define an operating area,which, in turn, allows us to predict how the circuit will reactto variations in the concerned parameters.V. S IMULATION – S
INGLE G ATE
A. Circuit design
The simulated circuit corresponds to the circuit shown inFigure 1(b), with the addition that R G can be shorted by aparallel switch. The driver circuits are ideal voltage sourceswith serial switches for High-Z mode. Each switch is modeledwith an on-resistance of and an off-resistance of .Given the memristor properties, especially R on and R off , fivecircuit-level parameters have to be determined. These are R G , V set , V cond , V reset and V read . Choosing V reset is somewhat Table IIS
UMMARY OF RELATED CONSTRAINTS ON PARAMETERS OF P AND Q . Constraint Constrainedparameters v on ,Q > f ( R Q ≡ R OH ) v on ,Q Equation (18) R off ,P > f ( v on ,Q , R Q ≡ R OH ) R off ,P , v on ,Q Equation (19) v on ,Q > f ( R Q ≡ R OL ) v on ,Q Equation (20) R on ,P < f ( v on ,Q , R Q ≡ R OL ) R on ,P , v off ,Q Equation (21) v on ,Q > f ( R off ,P , R on ,Q , R off ,Q , k on ,Q ) R off ,P , R on ,Q , R off ,Q , Equation (34) v on ,Q , k on ,Q v on ,P < f ( R on ,P , R off ,P , R off ,Q , k on ,P ) R on ,P , R off ,P , R off ,Q , Equation (41) v on ,P , k on ,P R on ,P < R IH , Equation (27) R on ,P R off ,P > R IL , Equation (25) R off ,P R on ,Q < R IH , Equation (28) R on ,Q R off ,Q > R IL , Equation (26) R off ,Q Table IIIN
OMINAL VALUES OF MODEL AND CIRCUIT PARAMETERS . Parameter v on v off R on R off k on Value − . / s Parameter α on α off w on w off k off Value 3 3 − . / s Parameter a on a off w c Value . Parameter V set V cond V reset V read R G T Value . . − . . µ s straightforward, as it is only used for initialization and not theIMPLY operation per sé.For this work, this voltage was set to V reset = − . Next, V set and V cond are determined. We define V set = 1 V , V cond =0 . , based on the memristor’s properties and Equations (1)and (2). With the voltages set, the constraints on R G [30] canbe evaluated, which leads to: .
000 kΩ < R G < .
769 kΩ . R G = 40 kΩ was chosen as the value of this resistor,which is lower than the geometric mean (
100 kΩ ) proposedby [43]. A summary of model and circuit parameters is shownin Table III, where the former are based on experimentalresults from previous works [18], [44].Equations (4) and (9) are evaluated in order to get the op-eration constraints imposed by the circuit. Namely, R min ,Q =101 .
449 kΩ and s min ,Q = 0 . . We can see that, in Case 1and assuming no state drift in P , the output memristor Q cannever reach a state higher than s min ,Q or, equivalently, cannever have a resistance lower than R min ,Q . B. Methodology & Setup
Proper IMPLY operation results – with respect to theoutput logic thresholds – are used to determine reliability.Correct operation is ensured when state changes within thememristors are occurring (switching conditions met) and arefast enough to exceed the given logic thresholds. We applythree different logic threshold schemes (shown in Figure 3) toevaluate the operation results in relation to the chosen logicthreshold. Each scheme defines separate, normalized input( s IH , s IL ) and output ( s OH , s OL ) thresholds, as in conventional Scheme: 1/200.5 s OH ,s OL s IH ,s IL s OL ,s IL s OH ,s IH s OL s IL s IH s OH Logic ‘1’ Logic ‘0’ Undefined
Output
Undefined
Input & Output
Figure 3. Different logic thresholds used in this paper. P: v on P: v off Q: v on Q: v off result maxminnominalExample: Figure 4. Four squares show the state of each variable in a simulation setand the outline color (green or red) shows the simulation result (correct orfailed, respectively). digital logic. Whereas the “1/2” and “1/3” scheme werechosen arbitrarily, the “TTL” scheme is derived from standardTTL ( V CC = 5 V ) [45]. This is done by normalizing thethreshold voltages V IH , V IL , V OH and V OL to V CC – e.g. s IH = V IH /V CC . The range between high and low thresholds, [ s IL , s IH ] and [ s OL , s OH ] , is forbidden; in other words, thelogic values and states in those ranges are considered unde-fined. Reasons for failures are not separately determined inour setup. Hence, failures during initialization, which lead toerroneous operation results, are counted as regular failures andare not distinguished from errors during the operation itself.Further, our simulation setup utilizes constant timesteps, soactual switching time are not explicitly measured.To obtain a nominal timebase for the IMPLY gate, atransient analog simulation of the memristor model was con-ducted. Examining the resulting waveform of the normalizedstate s after the simulation showed that it takes µ s toswitch from to of the state boundaries. Thus, thetimestep of circuit operation is set to T = 15 µ s . Every action(initialization, IMPLY operation, readout) is executed usingthis fixed timestep.Analog transient simulations were conducted in LTSpice,making use of this setup. Two memristor parameters per device( R on , R off or v on , v off or k on , k off ) were varied simulatenouslywithin the ranges reported in measurements [21] and relativeto the nominal state with a maximum deviation of ± . C. Result Presentation Method
To display the numerous results, we have come up with apresentation method of our own, which we introduce here.Each parameter set is represented by a group of foursquares. The left two squares, as displayed in Figure 4, show parameter values of memristor P , and the right two show thatof memristor Q . The filling of each square represents the stateof the corresponding parameter: empty means minimum, half-filled nominal and fully filled maximum. Figure 4 shows thisconcept and provides an example, too. The outline color ofthe squares shows whether the simulation result for a set ofparameter variation ( ∆ ) was correct (highlighted by green) orincorrect (highlighted by red). In general, any combination offour parameters can be varied concurrently and displayed thisway. However, our approach was to use three parameter sets: { R on ,P , R off ,P , R on ,Q , R off ,Q } , { v on ,P , v off ,P , v on ,Q , v off ,Q } and { k on ,P , k off ,P , k on ,Q , k off ,Q } , as explained in Section V-B.Figure 5 shows a complete set of simulations for the parame-ters { v on ,P , v off ,P , v on ,Q , v off ,Q } . These resulting sets are thenused to quickly identify those parameters that are commonbetween different failed runs. For example, Figure 5 showsthat the IMPLY operation produces no correct output if either, v on ,Q or v on ,P , is at its maximum value for variations greaterthan or equal to . D. Results analysis
Combining the math provided in Section IV and the simula-tion results obtained in Section V-C into joint graphs gives usFigures 6 to 10. First, we take a closer look at Figures 6,9 and 10, because they represent the most relatable logicthreshold scheme, derived from traditional TTL thresholds.Figures 7 and 8 show the same equations as in Figure 6,plotted for the 1/2 and 1/3 threshold scheme, respectively.The other two graphs for these logic threshold schemes areomitted as they lead to the same conclusions as Figures 7and 8. Furthermore, the threshold voltages turned out to bethe most critical parameters, so special attention is given totheir results.
1) Graph structure:
Here, we explain how these graphsare composed. Parameters R on ,P and R off ,P of memristor P are always shown on the y-axis since R P is crucial forthe outcome of the operation. We can also see that from thefact that R off ,P or R on ,P are present in all of the constraintsdescribed in Section IV. Different parameters are used in eachgraph for the x-axes.Colored curves and areas are used to show constraints andimportant ranges:Black, dashed lines indicate nominal parameter valuesLight blue lines show input logic thresholds R IH (solid)and R IL (dashed) for memristor P .Colored curves show the constraints from Section IV.Dotted parts indicate invalid plotting ranges, which donot correspond to any real value in physical devices.Arrows indicate how the constraints restrict the operatingarea of a parameter, i.e., which side of the curve isacceptable due to the given constraint.Blue areas show valid ranges of R off ,P and the respectiveparameters on the x-axes. For example, in Figure 6, thisarea represents valid ranges of R off ,P versus v on ,Q , v off ,Q , v on ,P and v off ,P . Note that for v on ,P our recommendedrange was used to limit the valid area, as the threedifferent curves are only weak constraints. ∆
10% 20% 30% 40% 50% run02468101214161820222426 ∆
10% 20% 30% 40% 50% run28303234363840424446485052 ∆
10% 20% 30% 40% 50% run5456586062646668707274767880
Figure 5. Results summary for different degrees of variation in v on , v off of P and Q . The / logic thresholds scheme was used here. v on R off R on − . − . − . − . − . − . − . − . − . − . . v on ,Q / R P / Ω − . − . − . − . − . − . − . − . − . − . . v on ,P / Static R off ,P = f ( v on ,Q ,R OH ) [eq. (19)] v on ,Q = f ( R OH ) [eq. (18)] R on ,P = f ( v on ,Q ,R OL ) [eq. (21)] v on ,Q = f ( R OL ) [eq. (20)] Dynamic v on ,Q = f ( R off ,P ) [eq. (34)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] Logic thres. R off ,P = R IL [eq. (25)] R on ,P = R IH [eq. (27)] Operatingarea R off ,P /v range R on ,P /v range R off ,P R on ,P v off ,Q / R P / Ω v off v off ,P / Figure 6. Analytical constraints and logic thresholds for the TTL schemeplotted over a range of memristor parameters { R P , v P , v Q } . Purple areas show valid ranges of R on ,P and the respec-tive parameters on the x-axes. For example, in Figure 10,this area represents valid ranges of R on ,P versus k on ,Q , k off ,Q , k on ,P and k off ,P . Note that restrictions on x-axisparameters are inherited from the R off ,P operating area.The bars at each side of the graphs overlay our simulationresults. Red sections show incorrect IMPLY results, greensections show correct results and orange sections are usedfor ranges in between, which are not explicitly coveredby the simulations.
2) Variation in voltage threshold:
Figures 6 to 8 depictvoltage thresholds v on ,P , v off ,P , v on ,Q and v off ,Q of memristor P and Q , as well as resistance parameters R on ,P and R off ,P of P using different logic threshold schemes (Figure 3). For the analysis we concentrate on the TTL scheme, Figure 6.The logic thresholds ( R IH , R IL ) divide the plot into twoparts: The bottom part concerning R on ,P and the top part con-cerning R off ,P . Adding the static constraints, Equations (18)to (21), on top of the logic thresholds decreases the validrange of R off ,P , v on ,Q and in particular R on ,P . The latter isevident from the purple area in Figure 6, which is smallerthan the plotted range. However, regarding R off ,P and v on ,Q ,the dynamic constraint, Equation (34), is even stricter than thestatic constraint.There are no static constraints for v on ,P . A rough dynamicestimation is provided by Equation (41), which depends on V P f . As discussed in Section IV-B, Equation (41) is evaluatedthree times, using R Q, , R Q, and R Q, , respectively. Thethree curves are drawn in brown, dark green and light green.No constraint for v off has been found (Section IV). Hence, thevalid ranges of R P over { v off ,P , v off ,Q } are only limited bylogic thresholds, Equations (25) and (27). As a consequenceof the above constraints, the valid range for each parameteris decreased and thus the advisable operating area remains asshown by the colored areas.Simulation results for variation in v on ,Q show very goodagreement with the mathematical analysis, especially the dy-namic estimation in Equation (34), which depends on Equa-tions (29) and (32). At +10% variation of v on ,Q and nominal R off ,P , the simulation fails (indicated by the thin red line),as the analysis predicted. Figure 6 shows very clearly thatthis failure is not accurately predicted by the static constraintsfrom Section IV-A alone. Hence, the dynamic estimation(Section IV-B) is vital. Variation in v on ,P strengthens this pointfurther, since different methods of estimating the dynamic be-havior leads to important changes regarding the agreement ofthe simulations and the derived analytical constraints. On theupper end of the v on ,P range, Equation (41) (evaluated using R Q = R Q, for V P f , Equation (35)) provides good congruencewith our simulations, whereas Equation (41) (evaluated using R Q = R Q, for V P f , Equation (35)) represents a moreconservative estimation. In contrast, evaluating Equation (41) − . − . − . − . − . − . − . − . − . − . . v on ,Q / R P / Ω v on R off R on − . − . − . − . − . − . − . − . − . − . . v on ,P / Static R off ,P = f ( v on ,Q ,R OH ) [eq. (19)] v on ,Q = f ( R OH ) [eq. (18)] R on ,P = f ( v on ,Q ,R OL ) [eq. (21)] v on ,Q = f ( R OL ) [eq. (20)] Dynamic v on ,Q = f ( R off ,P ) [eq. (34)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] Logic thres. R off ,P = R IL [eq. (25)] R on ,P = R IH [eq. (27)] Operatingarea R off ,P /v range R on ,P /v range R off ,P R on ,P v off ,Q / R P / Ω v off v off ,P / Figure 7. Analytical constraints and logic thresholds for the 1/2 schemeplotted over a range of memristor parameters { R P , v P , v Q } . using the theoretical minimum R Q = R Q, = R min ,Q inEquation (35), does not yield a good estimation. On thelower end of the v on ,P range, simulation results indicate somefailures for v on ,P ≤ − .
84 V ( +20% ). This behavior cannotbe explained by any of the constraints from Section IV. Ac-cording to the simulation results (Section V-C, Figure 5), thesespecific failures only occur when v on ,Q ≥ − . ± ,which leads us to believe that the reason for failure is the mismatch between v on ,P and v on ,Q . Regarding both, v off ,P and v off ,Q , there are almost no failures as expected, except for a(minor) failure during initialization for v off ,Q at +50% .In terms of R P variation, the simulation results suggestthat R off ,P can lie within the uncertain range between logicthresholds while the IMPLY operation still outputs correctresults. This stands to reason since the thresholds are artificiallimits not governed by the circuit behavior. Further, R on ,P isfine up to the lowest simulated value of R off ,P , because at thatpoint R off ,P > R on ,P changes to R off ,P < R on ,P , and hencethe operation fails.Combining all the simulation results and their respectiveanalytical constraints, we can identify the areas in which thecircuit is most likely to operate correctly. These are the areashighlighted in Figures 6 to 8. Equations (34) and (41) andtheir respective dependencies, Equations (29), (32) and (35)(evaluated using R Q = R Q, ), are recommended for estimat-ing the valid ranges of R off ,P versus { v on ,P , v on ,Q } ; whereasthe static constraints Equations (18) to (21) are sufficient for R on ,P versus { v on ,P , v on ,Q } .
3) Variation in resistance limits:
There are no static con-straints limiting R on ,Q or R off ,Q . Therefore, only logic thresh-olds and the dynamic estimation of Equation (34) can beapplied. The latter depends on Equations (29) and (32) and isevaluated in two ways: First, varying R on ,Q , but not R off ,Q ;and second varying R off ,Q , but not R on ,Q . It is interesting to v on R off R on − . − . − . − . − . − . − . − . − . − . . v on ,Q / R P / Ω − . − . − . − . − . − . − . − . − . − . . v on ,P / Static R off ,P = f ( v on ,Q ,R OH ) [eq. (19)] v on ,Q = f ( R OH ) [eq. (18)] R on ,P = f ( v on ,Q ,R OL ) [eq. (21)] v on ,Q = f ( R OL ) [eq. (20)] Dynamic v on ,Q = f ( R off ,P ) [eq. (34)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] Logic thres. R off ,P = R IL [eq. (25)] R on ,P = R IH [eq. (27)] Operatingarea R off ,P /v range R on ,P /v range R off ,P R on ,P v off ,Q / R P / Ω v off v off ,P / Figure 8. Analytical constraints and logic thresholds for the 1/3 schemeplotted over a range of memristor parameters { R P , v P , v Q } . R on R off R off R on R on ,Q / R P / Ω R on R off R off R on R off ,Q / R P / Ω Dynamic R off ,P = f ( R on ,Q ) [eq. (34)] R off ,P = f ( R off ,Q ) [eq. (34)] Logic thres. R off ,P > R IL [eq. (25)] R on ,P < R IH [eq. (27)] R off ,Q > R IL [eq. (26)] R on ,Q < R IH [eq. (28)] Operatingarea R off ,P /R Q range R on ,P /R Q range R off ,P R on ,P Figure 9. Analytical constraints and logic thresholds for the TTL schemeplotted over a range of memristor parameters { R P , R Q } . see that – for any of the three schemes of Figure 3 – the logicthresholds limit the operating areas (blue and purple) muchmore than the actual analytical constraints. Simulation resultsfor R on ,P and R off ,P are identical to Figure 6, however, R off ,Q cannot reach as low as R off ,P without causing a failure. This issolely due to the chosen logic thresholds, as an IMPLY outputof R off ,Q < R OL is considered as failure.Overall, resistance variation does not seem to hold as muchpotential for failures as variation in threshold voltage(s) does.Equation (34) and its dependencies, Equations (29) and (32),can be used to identify valid parameter ranges, but – based onour simulation results – it is most likely not necessary. Thisis true for all three logic threshold schemes listed in Figure 3. k on R on R off . . . . . . . . . . . k on ,Q / mms R P / Ω . . . . . . . . . . . k on ,P / mms Dynamic k on ,Q = f ( R off ,P ) [eq. (34)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] v on ,P = f ( R off ,P ,R Q, ) [eq. (41)] Logic thres. R off ,P > R IL [eq. (25)] R on ,P < R IH [eq. (27)] Operating area R off ,P /k range R on ,P /k range k off − . − . . k off ,Q / nms R off ,P R on ,P − . − . . k off ,P / nms R P / Ω Figure 10. Analytical constraints and logic thresholds for the TTL schemeplotted over a range of memristor parameters { R P , k P , k Q } .
4) Variation in switching speed:
The dynamic constraintin Equation (34) can be used to extract limits of k on ,Q ,while Equation (41) provides the basis for the analysis of k on ,P . Figure 10 shows the plotted equations and logic thresh-olds. Equation (41) (evaluated using Equation (35), where R Q = R Q, ) is omitted, as well as all constraints containing k off ,P and k off ,Q , since they are far outside of the plottedrange. The graph in Figure 10 shows that k on ,P is hardlyrestricted by any constraint. Only at relatively high values,greater than +50% variation, Equation (41) (evaluated usingEquation (35) with R Q = R Q, ) comes into effect, but cannotbe compared to simulation results, as our simulated range endsat +50% , in compliance with our methodology (Section V-B).In contrast, Equation (34) provides a reasonable constraint for k on ,Q . Nonetheless, our simulated range only reaches down to − and thus results cannot be compared to the constraint.The other two logic threshold schemes show similar behavior.As before, the colored areas indicate the merged, predictedfunctional range of both, k on ,P and k on ,Q .In conclusion, switching speed k of both memristors canvary at least by ± without performance issues, accordingto our simulation. Analytical constraints suggest that there is alower boundary for k on ,Q at approximately / s ( − ).VI. S IMULATION – C
ROSSBAR
A. Setup
Analogous to the single IMPLY gate simulation setup (Sec-tion V-A), the circuit in Figure 1(b) is the basis for the crossbarsimulation. A complete × cell 1T1R crossbar circuitwas used. The IMPLY gate is formed by two memristorsarbitrarily located within the crossbar. Each memristor hasits own access device, in our case an ideal switch, andis connected to adjacent cells via resistors that model thenanowire resistances. The ideal switch is modeled using anon-resistance of µ Ω and an off-resistance of
100 MΩ . Lineresistances were chosen to be
10 Ω each, according to the worstcase in [26]. Figure 11 shows the structure of a single cell. . . .word y ... bit x . . . ... R xy/x ( y +1) R xy/ ( x +1) y M x y T x y Figure 11. Structure of a single cell within the 1T1R crossbar, including lineresistances.
Circuit parameters of the IMPLY gate are identical toSection V-A, Table III. Bit-line drivers are attached at the topand bottom for symmetry. The readout strategy described inSection II-B was implemented. Analog transient simulationswere conducted in Cadence Spectre. The method of param-eter variation is the same as defined for the single gate inSection V-B, except that only relative parameter variations( ± ) were conducted for the crossbar. B. Methodology
IMPLY gates can be formed by any two memristors in thecrossbar. Both, the worst case scenario in terms of parasiticresistance between the two memristors forming a gate, andthe worst case voltage drop, were considered. Hence, fourseparate simulations were conducted with P and Q at different { bit , word } positions.1) Memristor P at position { , } , Q at position { , }
2) Memristor P at position { , } , Q at position { , }
3) Memristor P at position { , } , Q at position { , }
4) Memristor P at position { , } , Q at position { , } Instead of using idealized ( s = 0 or s = 1 ) or manuallyfixed initial memristor states, each cell is assigned a differentinitial state during (automated) netlist generation. The statesare generated via Octave and follow a Gaussian distributionwhich has been cut in half as shown in Figure 12. Althoughthis approach requires a greater effort, it represents a morerealistic scenario than ideal initial states. C. Results analysis
In this section we compare the crossbar simulation resultsagainst the single gate results. As before, to be efficient, resultsare represented using our technique introduced in Section V-C.Figure 13 shows a complete set of crossbar simulations for theparameters { v on ,P , v off ,P , v on ,Q , v off ,Q } . Figure 14 depicts thecombined, i.e. worst case, results of all crossbar simulation .
25 0 . .
75 10200400600800 s n p e r b i n Figure 12. Histogram of initial (normalized) device states, s , within the × crossbar, plotted using 100 bins. ∆
10% 20% 30% 40% 50% run02468101214161820222426 ∆
10% 20% 30% 40% 50% run28303234363840424446485052 ∆
10% 20% 30% 40% 50% run5456586062646668707274767880
Figure 13. Crossbar results summary for different degrees of variation in v on , v off of P and Q . Logic thresholds for ‘1’ and ‘0’ were set according to theTTL threshold scheme (Figure 3). Memristor P was at position { , } , while Q was at the center, { , } . Single gate k off ,P / nms k on ,P / mms k off k on -1.0 0.0 4.0 8.0 12.0 16.0 20.0 24.0Crossbar k off ,P / nms k on ,P / mms Single gate k off ,Q / nms k on ,Q / mms Crossbar k off ,Q / nms k on ,Q / mms v on ,P / v off ,P / v on v off -1.0 -0.8 -0.6 -0.4 -0.2 0.0 10 20.0 v on ,P / v off ,P / v on ,Q / v off ,Q / v on ,Q / v off ,Q / Single gate R off ,P / R off
400 600 800 1000 1200 1400 1600Crossbar R off ,P / R on ,P / R on R on ,P / Single gate R off ,Q / Crossbar R off ,Q / R on ,Q / R on ,Q / Figure 14. Comparison of single gate and (combined) crossbar simulation results. A range of ± around the nominal value is plotted for each parameter.The results are color-coded: Green for correct IMPLY output, red for false output and orange for ranges inbetween, that are not covered by the simulation. setups explained in Section VI-B, and the results of the singlegate simulation, where the TTL threshold scheme was applied.The bars and color coding are identical to Figures 6 to 10,Section V-D. While the conclusions from Section V-D remaintrue, unless noted otherwise, here we highlight the differences.
1) Variation in voltage threshold:
Given that the circuit isin a crossbar architecture, an increased number of errors dueto threshold voltage variation can be expected in the crossbarsimulation, when compared to the single gate simulation.Surprisingly, however, it is not significantly worse.There are three main differences: First, the initializationfailure of v off ,Q (initially shown in Figure 6) does not arisein the crossbar simulation. However, there were initializationfailures in the crossbar for ≤ v off ,P ≤ ( − to − ). Having said that, as v off is of minor interestto the IMPLY operation, this can neither be considered animprovement, nor a degradation compared to the single gate.Second, results indicate failures if both v on ,P and v on ,Q areabove − .
63 V ( − at the same time. Based on the singlegate simulation results (Section V-D) and our recommendationto use Equation (41) – in combination with R Q = R Q, inEquation (35) – for device variability evaluation, this failureis predictable. As for the exact reason of this error, we assume that it is due to the increased state drift in P , as | v on ,P | is solow. In terms of operational range, the valid values for v on ,P and v on ,Q are drastically restricted to the nominal value v on ,as shown in Figure 14. It is only then that correct operationscan be guaranteed. However, if v on ,P < − .
63 V ( − is ensured, a much greater range for v on ,Q is admissible,similar to the case of the single gate in Section V-D. Finally,the third difference is that the IMPLY operation fails for v on ,P < − .
77 V (+10%) while v on ,Q = v on , as comparedto +20% in the single gate simulation. Thus, the tolerablemismatch between v on ,P and v on ,Q shrinks to within thecrossbar.Apart from these differences the results of both simulationsare identical, although Figure 14 might not reveal it at the firstlook. This means that the proposed constraints for v on and v off from Section IV can be applied to get a basic understandingof threshold voltage variability within crossbar architectures.
2) Variation in resistance limits:
Varying the resistancelimits of the memristors within the crossbar reveals someinteresting results, as we can see in Figure 14. While IMPLYoperations in the single gate simulation fail for R off ,Q ≤
800 kΩ ( − , the crossbar simulation shows correct resultsdown to R off ,Q = 700 kΩ ( − . We believe that this is due to the readout strategy applied to the crossbar, since themeasured R Q after executing Case 3 (Table I) is almost in a majority of the − simulation runs. Failures startoccuring below R off ,Q ≤
600 kΩ ( − . The range between − and − variation is not explicitly covered by oursimulation steps.Furthermore, false IMPLY results within the crossbar comeabout at the upper and lower end of our simulated R off ,Q range, as well as at the upper and lower end of the sim-ulated R off ,P range. This is a combined effect, since thoseerrors only occur if both, R off ,P ≤
500 kΩ ( − and R off ,Q ≥ . , or vice versa, are present at thesame time. Interpreting this scenario based on the 1/2 or TTLlogic thresholds from Figure 3, one can see that if either R off ,P or R off ,Q are below
500 kΩ , they are not interpreted as logic‘0’, but logic ‘1’. Thus, they do not fulfill Case 1 of the truthtable, where p = 0 and q = 0 must be true. Applying the 1/3logic threshold scheme, an off-resistance of
500 kΩ yields anundefined logic state. Therefore, none of the cases in the truthtable is fulfilled. Hence, such errors are predicted via logicthresholds alone and do not require further evaluation usingthe constraints defined in Section IV.Lastly, we should remark that simulation results for R on ,P and R on ,Q in the crossbar are identical to the the single gatesimulation results.
3) Variation in switching speed:
Swichting speed variationdoes not pose a threat to single IMPLY gates, as deducedin Section V-D. However, based on our simulation results(Figure 14), behavior within a crossbar is very different. Forvariations in k on ,P and k on ,Q larger than ± , the IMPLYoperation fails. Further analysis of those failures reveals thatit is the mismatch between P and Q which causes mosterrors. If either ∆ k on ,P ≤ − while ∆ k on ,Q ≥ +20% ,or ∆ k on ,P ≥ +20% while ∆ k on ,Q ≤ − , the operationresult is wrong. This mismatch cannot be predicted by our con-straints. Further, the simulation indicates failures for variationin k off ,P larger than ± , as well as for ∆ k off ,Q = ± .As k off ,P and k off ,Q are never relevant during IMPLY, weinfer that these are initialization errors. They can, however, beresolved by using a different initialization scheme than the onewe applied. For example, using an additional readout cycle toconfirm written initial states. Such a scheme provides feedbackto resolve initialization errors before IMPLY is executed.VII. C ONCLUSION
Device variability is one of the main challenges when imple-menting memristor-based logic. In this paper, we formulatednovel constraints based on static switching conditions andstate change dynamics. We note that the underlying causesof variation in device parameters are not differentiated by ourmethodology. Hence, environmental effects (such as tempera-ture) causing parameter variation are taken into account by ourconstraints, just as process variations are. IMPLY operationresults after a fixed timestep of execution were used as themetric to assess gate performance. In addition, different logicthreshold schemes were considered. The derived constraintswere put to the test in an extensive analysis for single gate and × v on ,Q , was identified as a major root ofconcern regarding correct operations. We conclude that themost dominant reasons for failure are predictable by ourtheoretical analysis for both the single gate and the crossbar.Therefore, our analysis and recommendations can be used fordesigning a reliable IMPLY gate. More specifically, we suggestto choose design parameters away from the borders of therecommended areas. Ideally, this distance should be chosensuch that the typical (or maximum) variations, do not leadto crossing the borders of recommended area. Nonetheless,accompanying studies or simulations should be conducted tounderstand the non-deterministic errors, especially regardingvoltage threshold- and switching speed mismatch within thecrossbar, as well as state drift phenomena.Lastly, we note that our analysis can be used to decidewhether a specific memristor technology and IMPLY logic arecompatible. To that end, technology parameters need to be as-sessed based on the constraints for reliable IMPLY operationswe extracted in this work. Further, considering technology-dependent parameter variation, an acceptable margin from theborders of the operating area must be ensured. Otherwise,chances for failures in IMPLY operations are increased. Hence,it would be better to use other technologies to implement theintended IMPLY-based circuits, or use other logics to imple-ment the intended functionalities on the given technology.R EFERENCES[1] D. Niu et al.
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Logic Guide
Simon Michael Laube is currently a B.Sc. studentof electrical engineering and information technologyat the TU Wien, 1040 Vienna, Austria. His B.Sc.thesis is on examining the robustness of memristor-based material implication at the circuit/gate level.