Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?
DDoes Cascading Schmitt-Trigger StagesImprove the Metastable Behavior?
Andreas Steininger and Robert Najvirt and J¨urgen Maier
Vienna University of Technology, 1040 Vienna, Austria { steininger, rnajvirt, jmaier } @ecs.tuwien.ac.at c (cid:13) Abstract —Schmitt-Trigger stages are the method of choice forrobust discretization of input voltages with excessive transitiontimes or significant noise. However, they may suffer frommetastability. Based on the experience that the cascading offlip-flop stages yields a dramatic improvement of their overallmetastability hardness, in this paper we elaborate on the questionwhether the cascading of Schmitt-Trigger stages can obtain asimilar gain.We perform a theoretic analysis that is backed up by an ex-isting metastability model for a single Schmitt-Trigger stage andelaborate some claims about the behavior of a Schmitt-Triggercascade. These claims suggest that the occurrence of metastabilityis indeed reduced from the first stage to the second which suggestsan improvement. On the downside, however, it becomes clear thatmetastability can still not be completely ruled out, and in somecases the behavior of the cascade may be less beneficial for a givenapplication, e.g. by introducing seemingly acausal transitions. Wevalidate our findings by extensive HSPICE simulations in whichwe directly cover our most important claims.
I. I
NTRODUCTION
In VLSI design two types of discretization are performed tomake real-world quantities “computable” in a digital domain.The values of originally analog quantities are transformedfrom their continuous space into a suitable digital (i.e. discrete)representation by analog-to-digital converters. In the timedomain a periodic clock signal performs a transformation froma continuous to a discrete time by sampling these digital logicstates at suitable instances, typically the clock edge. It hasbeen formally proven that every such transformation from acontinuous space to a discrete one inevitably introduces therisk of metastability [1], i.e. a prolonged state of indecisionbetween two discrete values. Consequently one either has toallow an unbounded decision time, or expect to occasionallyexperience undefined, also known as “metastable”, readings.In the time domain this question boils down to deciding aboutthe precedence of events; it has been extensively studied incontext with flip-flops [2], where a decision needs to be madewhether a transition on a data line occurred before or after agiven clock edge. Synchronizer circuits are used to reduce therisk of metastable upsets to a suitable level, albeit at the costof performance. In case of the waiting synchronizer [3] flip-flop stages are simply cascaded to that end, which generallyyields a dramatic improvement in reliability.
This research was partially supported by the SIC project (grantP26436-N30) of the Austrian Science Fund (FWF). V in V out V H V L HILO Fig. 1. S/T hysteresis
In the value domain the most fundamental task is thatof a discriminator which has to decide whether a giveninput voltage is higher or lower than a reference. To avoidoscillating behavior for inputs close to the reference, Schmitt-Trigger (S/T) stages [4] are employed instead whose hysteresisbehavior makes them ignore irrelevant voltage fluctuations.However, it has been shown that for certain input traces aS/T can become metastable as well [5], [6]. Following thelessons learned from synchronizers, one may ask whether thecascading of S/Ts is again effective in reducing the risk ofmetastable upsets. This is exactly the question we want toaddress in this paper.To this end we will, in the next section, revisit the behaviorof a single S/T stage. Based on this knowledge we will, inSection III, break down our key question into sub-questionswhose answer may finally allow the desired overall judgment.In Section IV we will briefly introduce the metastability modelfor a single S/T stage, as derived by Marino in [5] and use it toshed light on our related sub-questions. On the foundation ofthis analysis we will elaborate predictions for the behavior ofa two-stage S/T cascade in Section V which we will validateby extensive simulation experiments in Section VI. Finally, wewill conclude the paper with Section VII.II. B
EHAVIOR OF A SINGLE S CHMITT -T RIGGER STAGE
The key property of a S/T is its hysteresis behavior asshown in Fig. 1. Once an input voltage V in has crossedthe upper threshold V H from below, the S/T output flips a r X i v : . [ c s . OH ] J un in V out V DD M M M M M M Fig. 2. Conventional CMOS S/T implementation (from [4]) to LO and will not return to HI before the input crossesthe lower threshold V L . This behavior provides the S/T itsdesired robustness against fluctuations of V in which cause acomparator to oscillate when occurring close to its (single!)threshold voltage.Clearly, the hysteresis behavior is tantamount to makingthe reference voltage depend on the current output state,which, in turn, implies that there is some kind of feedbackof the output state to the input. Fig. 2 shows a typical CMOSimplementation of a S/T [4]. The feedback path via transistors M and M is clearly visible. It is exactly this (inevitable)existence of the positive feedback path that makes the S/Tprone to metastability. In case of an input trace that first causesthe S/T state to flip but then, before the feedback path hasfully stabilized, pulls the S/T back to the old state, undesiredbehavior can be observed at the output. As will be elaboratedin more detail in Section IV, the S/T can exhibit the followingbehaviors at its output:(B1) For strictly monotonic input traces the S/T will showclean (steep) and well timed output transitions. This isthe regular behavior.(B2) A monotonic input trace that brings the S/T right tothe tripping point and stays constant there can cause anindecision on whether to flip, which ultimately leads toa clean but (arbitrarily) late transition.(B3) Similarly, an input trace that goes slightly beyond thethreshold but then back again and stays constant, canmake the S/T assume a metastable state in which itoutputs a constant voltage that is determined by the finalconstant value of V in and may well be somewhere inbetween a clean HI and a clean LO. We will consider an inverting S/T throughout the paper, as virtually allpractical implementations are inverting. (B4) An input pulse of marginal width, i.e. one that doesnot give the S/T enough time to stabilize its state, cancreate a glitch at the output. Depending on whether thispulse reaches full height or not, we distinguish betweena glitch and a runt, respectively.(B5) In general, a non-monotonic input trace can, in principle,make the S/T output any desired voltage between cleanHI and clean LO for any desired time – in fact byappropriately controlling the input trace one can obtainany desired output voltage trace (within the S/T’s staticand dynamic voltage limits, of course).It very much depends on the application which of thesebehaviors are actually undesired, and as a consequence it ishard to quantify the improvement in signal quality obtainedby the S/T in general. In most cases marginal voltage levelsare problematic, as they could be interpreted differently bydifferent receivers. Unfortunately, in case (B3) one may stillencounter marginal output voltage levels that are not justtransient, but, as these cases are hard to trigger and hence canbe considered rare, the S/T provides a very good improvementin general. If output glitches are a concern, case (B4) becomesproblematic, and even in case (B2) a late transition may forma glitch in conjunction with a regular subsequent one. Again,these cases need very specific input traces and are hence rare.Finally, due to case (B5), no type of output behavior can becompletely ruled out by using the S/T, which means thereis only a quantitative improvement, albeit a substantial one.However, as there are infinite numbers of both, “good” and“bad” traces, it is not possible to quantify the improvement;and we are not aware of any such approaches in the literature.III. Q
UESTIONS TO BE ANSWERED
From the above analysis we have concluded that a single S/Tstage improves the signal quality. So in principle, a subsequentS/T stage should obtain a similar improvement, and thusoverall the cascade has a higher gain than the single stage.However, it remains to be investigated whether this is indeedthe case. In order to come to a conclusive answer, the followingquestions should be addressed:(Q1) In which cases does the second S/T stage improve thebehavior?(Q2) Are there cases in which the behavior is getting worse?Are there new types of (likely) behavior?(Q3) Is the second stage equally likely to become metastableas the first one?(Q4) Can metastability of the last stage be completelyavoided, possibly by forming a longer cascade?(Q5) How are the static properties of the cascade determined(is it still a S/T, and if so, which hysteresis)?(Q6) How are the dynamic properties determined (regulardelay, output slope, is there a performance penalty inusing a cascade?)(Q7) Are there any rules for optimal dimensioning of thecascade (combination of fast and slow stage, differenthystereses,...) + V in R C V out R A R B V R Fig. 3. Dynamic model of the S/T inspired by Marino [5]
To conclusively answer these questions we will in thefollowing elaborate a sufficiently detailed understanding of thebehavior of a (2-stage) S/T cascade. As a first step towardsthis end we will revisit an existing model for the metastablebehavior of a single S/T stage in the next section.IV. M
ETASTABILITY MODEL OF A S CHMITT -T RIGGERSTAGE
Marino has already proposed a dynamic model for the S/Tthat allows to investigate its metastable behavior [5]. Thismodel is based on a S/T implementation using an operationalamplifier (OpAmp) as shown in Fig. 3. The OpAmp isassumed to be ideal, but with a limited output voltage rangeof ± M . An RC low pass at its output defines its dynamicbehavior, and a resistive voltage divider by k ∈ { ... } feeds back part of the output voltage to the input (positivefeedback). For brevity we omit the derivation and solution ofthe associated differential equations here (for details pleaserefer to [5]) and just show the results:As the saturation requires separate treatment, the solutioncomprises three regions, as illustrated in Fig. 4: upper andlower saturation (Regions 1 and 3), as well as the “linearregion” 2 between them. The dashed lines represent theborders between the regions (the corresponding equations arealso given).The dynamic system represented by the S/T is then de-scribed by the following equations:Region 1: dV out dt = V (cid:48) out = − τ ( V out − γ ) (1)The resulting trajectory for V out is a decaying exponentialfunction with time constant τ ≈ R C that asymptoticallyapproaches the truly stable rest point γ ≈ M .Region 2: dV out dt = V (cid:48) out = 1 τ ( V out − γ ) (2)Here we have a growing exponential function with timeconstant τ ≈ R C kA − that moves away from the metastablerest point γ ≈ V in − (1 − k ) V R k − A . Note that we do not have asingle metastable point, as in case of a latch, but all points on V in V out V in = R A V R + R B V out R A + R B − MA V in = R A V R + R B V out R A + R B + MA V out = γ V out = γ V out = γ REGION 1REGION 2 REGION 3
Fig. 4. Phase diagram for the S/T from Marino [5] γ are metastable points and the actual rest point depends on V in (see Fig. 4).Region 3: dV out dt = V (cid:48) out = − τ ( V out − γ ) (3)Similar to Region 1 this yields a decaying exponential functionwith time constant τ = τ ≈ R C that asymptoticallyapproaches the truly stable rest point γ = − γ ≈ − M .At this point it is interesting to compare the S/T with alatch, as Veendrick derived a similar model for latches in [7]to investigate their metastability behavior. While both elementshave a positive feedback, the key difference is that in the latchthe input becomes decoupled when the storage loop is closed(i.e. when switching to hold mode). Mathematically this meansthat the input becomes irrelevant, and just the homogeneoussolution of the differential equation applies. In the S/T thisis not the case, and the input continuously influences the be-havior. This not only complicates the mathematical treatment(and is probably the key reason why there are no quantitativeimprovement values available for the S/T), it also results inthe S/T having more than one metastable point: depending onthe input voltage the S/T can rest in any metastable locationalong the γ line and hence produce any arbitrary metastableoutput voltage. Finally, this lack of decoupling between stagesalso complicates the analysis of the S/T cascade.As a physical analogy one might consider the metastablelatch as a stick that is vertically placed on a firm table suchthat it balances on its tip before it finally falls, while the S/Tis the same vertical stick but balancing on a finger that canstill be moved left and right (inverted pendulum).V. C LAIMS ABOUT THE BEHAVIOR OF A S CHMITT -T RIGGER CASCADE
In the following we want to investigate a two stage S/Tcascade as shown in Fig. 5. It was already argued in Section II in V m V out Fig. 5. Two stage S/T cascade V in V m V L, V H, V V HILO V L, V H, Fig. 6. Characteristic of a single S/T showing V and V that a single S/T stage can essentially exhibit any outputbehavior (case (B5)). This means that the first stage does notqualitatively restrict the second one’s input space, and, as aconsequence, stage 2 has unrestricted output behavior as well.So at this point we can already answer question (Q4) aboutcomplete avoidance of metastability through a S/T cascade:This is simply not possible.In continuation of the physical analogy given in Section IVwe can view the second stage as a second vertical stickbalancing on the upper tip of the first one. This analogynicely illustrates that it becomes much more unlikely to seemetastability in the second stage (i.e. actually find a balancefor the second stick) – thus giving an intuitive answer to (Q3)– , but it is physically possible.To get closer to a quantitative answer, let us analyze howthe different output behaviors of the first stage are handledby the second one. The internal signal connecting the S/T isnamed V m ( cf. Fig. 5).
A. Regular behavior
Let us start with the regular behavior (B1) and assume astarting point with V in < V L, (the case of V in > V H, isanalogous). Note that in V L,i and V H,i the index i correspondsto the stage number. Due to the inverting behavior of each ofour S/T stages, we have V m at HI and V out at LO again. As V in increases, V m and V out stay constant until V in reaches V H, . Beyond that point V m will switch to LO. With a strictlymonotonic V in this transition of V m will be rapid. Clearly,this transition of V m will also cause the second stage toswitch, namely when crossing its threshold V L, . Overall, weexperience a clean switching, with the threshold determinedby that of the first stage, while the second stage’s threshold V in V out V H, V L, V V HILO
Fig. 7. Theoretical hysteresis ( V in − V out ) of S/T cascade is irrelevant, as V m crosses the whole voltage range anyway.This answers question (Q5).Generally, in this mode of operation we can expect thesteepness of the transitions to increase as the first S/T tends toswitch fast when its threshold is reached, causing the secondone to change even faster. The signal is however delayed bythe propagation delay of the second S/T. B. Late transitions of stage 1
According to case (B2) a ramp input stopping at a constantvalue near the threshold will cause a late but clean transitionat stage 1. In that case the second stage perceives a cleaninput which it simply conveys (adding its nominal propagationdelay). So late transitions are essentially not modified by thesecond stage.
C. Hysteresis curve of the cascade
We know from Section II that for a single S/T to becomemetastable its input voltage must be between its thresholds.This means we can only make the second stage metastablewith a V m between V L, and V H, , which will (apart froma steep transition during switching as described above) onlyoccur when the first stage is metastable, and even then onlyin a specific range, as shown in Fig. 6. In the following wewill use V and V to denote those values of V in that, if thefirst S/T is metastable, will cause it to output V m = V L, and V H, respectively. This consideration allows us to draw thehysteresis curve for the overall behavior of the cascade shownin Fig. 7: Still the static switching points are determined bythe first stage, but the range of possible metastable behavior islimited to the range of V ≤ V in ≤ V , with V and V beingdetermined by the slope of the γ line of the first stage andthe thresholds of the second stage.The same hysteresis is achieved when using two non-inverting Schmitt-Triggers, while combining an inverting S/Twith a non inverting one, mirrors the hysteresis around the line V out = ( HI + LO ) / , independent of the ordering (assumingequal V L,i and V H,i values).For the case that the hystereses of the single S/Ts are notequal the ordering is important, as V H and V L of the cascadedystem are determined by the first S/T alone and V and V byboth of them. Let V Ni be ( V H,i + V L,i ) / . If V N = V N = V DD/ the order does not have an influence on V and V .In all other cases they might deviate, however the differencebetween them, i.e. V − V , is constant. This is very importantsince V − V < V H − V L . Therefore it is possible, if the firstS/T is held in metastability, to create a pulse train at the outputwith the reduced hysteresis V to V (cycling the dotted linesin Fig. 7). D. Moving into metastability
To move the second stage into metastability, stage 1 needsto be made metastable first. This can be attained by increasing V in from a value lower than V L, to V H, and then decreasingit appropriately, while stage 1 starts to switch (behavior (B3)).By staying close to the metastable restpoints ( γ in Fig. 4)until V m reaches V L, ( V in = V ) the second S/T will start toswitch and can be driven into metastability in the same way asthe first one. While keeping both S/Ts in metastability, whichis either possible with very precise or very fast control of V in (for a more detailed explanation see [6]), the output valuesbetween LO and HI shown in Fig. 7 are reachable. E. Emergence of glitches
An interesting behavior can be observed when, with bothstages in the metastable state, V in is increased to a valuebetween V and V H . This will bring V m to above V H andhence cause the second stage to flip to LO. A further (mono-tonic!) increase of V in beyond V H will then bring the firststage to saturation and make V m transition to LO, which, inturn, causes the second stage to flip back to HI. In this case wehave observed a glitch at V out that was caused by a monotonictransition of V in (however, a non-monotonic V in was initiallyrequired to bring both S/Ts into the metastable state in the firstplace). The root of this behavior lies in the positive slope ofthe γ line, which is somehow contradictory to the otherwiseinverting behavior of the S/T. This is also expressed by thedirection of the arrows in Fig. 7.While this definitely represents a new type of (often unde-sired) behavior not seen with a single stage – thus answering(Q2) positively – one should keep in mind that it takes an extremely precise control of V in to navigate into this case. Inthe physical analogy this would equal the case of bringingboth sticks in vertical balance and then having them fall downto opposite sides. F. Generalization of the analysis
The above scenarios only represent some selected possiblecases of output behavior. More generally, the shape of V out ( t ) is determined by (a) the shape of the input voltage V in ( t ) ,(b) the state of stage 1 (given by V m ( t ) ), and (c) the state ofstage 2 (given by V out ( t ) ). In this 3-dimensional space one canidentify 9 characteristic sub-spaces (for V in remaining constantat its initial value). Five of these are listed in Table I, theother 4 are symmetric and not treated here for brevity. Thesubtables ... apply for different values of V in . Table shows the case where V in is significantly lower than V L, ,such that V m is forced to HI and consequently V out to LOimmediately, irrespective of their initial state. The zeros denotethe final state of the cascade’s output. The arrows show whatevent could be observed at the output. 0 means the outputwas initialized to zero and remains there, 0 means the outputmakes a fast transition to 0 from wherever it was initializedto. The 0 shows that there is (very limited) glitch potential ifthe nominal propagation delays of the two S/Ts significantlyvary. TABLE IP
OSSIBLE OUTPUT BEHAVIORS WITH STATIC INPUT V in V L, V H, V V V out V m Table shows possible outputs when V in is so close to V L, that it causes an abnormal switching delay of the firstS/T (Region 2 in Fig. 4). Due to this delay, a late transition(0 ) or a glitch (0 ) can be observed at the output when V m is initialized to . That would correspond to the case of glitchemergence described above.In table , V in is between V L, and V – the first stage cannow also be initialized metastable resolving to 1 ( ), to 0 ( )or not resolving at all ( ). As can be seen, due to V in < V L, the metastable voltage must be below V L, for the next stage,which can therefore not distinguish this type of metastabilityfrom a clean LO. When metastability resolves to HI, the effecton the second stage will be identical to the late transitions inthe previous paragraph.Table shows the case when the metastable voltage outputof the first stage is very close to V L, . The difference to theprevious table is that during metastability of the first S/T, thesecond one can delay its output transition. The most interestingcase is 0 . It shows that the relationship of the delays(metastability/late transition) makes a qualitative difference atthe output: If V m reaches HI first, the output remains LO; if V out is faster, the output could be an arbitrarily delayed glitch.Table presents the behaviors for input voltages of V 10 20 30 40 500.00.20.40.60.81.01.2 V i n [ V ] V m [ V ] V o u t [ V ] Fig. 8. Time trace of V in , V m and V out for input slopes stopping at a constant value near V L, (second S/T resolves before first one), thus generating a glitch.So we can conclude that in addition to the 3-dimensionalspace described so far, the order of metastability resolutionis important as well, if both S/Ts are metastable.As a general trend we can observe in the table that, whilesome of the metastable cases of stage 1 are propagated, othersare turned into other behaviors like proper transitions, delayedtransitions, or glitches. In no case an intermediate voltage isgenerated from clean transitions. So in applications where thekey purpose of using a S/T lies in protecting the subsequentlogic from intermediate voltages, the cascade does a decentjob in reducing that risk. However, if glitches and badly timedtransitions are dangerous, then the use of the cascade may becounter-productive. This may be considered an answer to (Q1)... (Q3). G. Pulse propagation According to case (B4) a single S/T stage may or may notpropagate a glitch or runt. As the second stage may, of course,show the same behavior, glitches and runts may propagatethrough the whole cascade. As the second stage may turn someof these into stable transitions, however, the probability ofpropagation can be expected to become lower in the cascade.VI. V ALIDATION OF THE CLAIMS To validate our predictions about the behavior of the cascadefrom the previous section, we performed HSPICE simulationsof two S/Ts in series, each implemented using the circuitshown in Figure 2 with transistor parameters of an industrial65 nm process. Fig. 8 shows the behavior of the cascaded S/Ts when aramp resulting in a constant value is applied to the input (case(B2)). As one can see the first stage responds with late butclean transitions, i.e. ones that cross the intermediate voltagerange sufficiently fast. The second stage then increases thesteepness of the transitions even further. Please note that theinputs causing the different traces only deviate by a verysmall amount of their final, constant value. Therefore we canconfirm, that V H, respectively V L, has to be approached veryaccurately to observe late transitions at the output. However,this is due to the properties of the first stage alone, while thesecond stage does not yield any further improvement.When short pulses are applied to the cascaded S/Ts (case(B4)), these are preserved or suppressed depending on theirwidth, as can be seen in Fig. 9. A little bit misleading is thefact, that the pulses at the output seem to be longer than thoseat the input, since the time they spend below V L is longerthan for those at the input. This can, however, be explainedby the increased steepness of the transitions. When the pulsesare compared by their crossing times of V DD/ , for example,one can see that they stayed the same and are not stretched intime.Figures 10 and 11 show the cases when both S/Ts are intheir metastable region and the first respectively second oneresolves before the other. In the first case V out increases with V m until it reaches V H , where V out drops rapidly. If, however,the second S/T resolves first and afterwards the first one to thesame value, a glitch at the output is introduced. This exactlymatches our predictions from theory. .0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.00.40.81.2 V i n [ V ] V m [ V ] V o u t [ V ] Fig. 9. Time trace of V in , V m and V out for pulse inputs v o l t a g e [ V ] V in V m V out Fig. 10. First stage resolving earlier from metastability In the simulation we also observed a behavior that wasnot predicted, namely that transitions of stage 2 influencethe behavior of stage one. This coupling can be seen bestin Fig. 12. Initially the first Schmitt-Trigger resolves towardsVDD until V H, is reached, causing the second one to switch.This, however, also introduces a change at the output of stageone forcing it to drop.Fig. 13 shows how the S/T cascade can be driven intometastability and even forced to output arbitrary waveforms(in this example a sine wave). The beginning of the figure (first15 ns) shows regular transitions (case (B1)). The hysteresis isclearly observable and it also becomes clear why the cascade’sthresholds/hysteresis are determined by those of the first S/Tin the series – it applies its hysteresis to the input and outputsfast, full range transitions. With such transitions at its input,the second S/T’s hysteresis only marginally increases thepropagation delay through the cascade but does not alter the v o l t a g e [ V ] V in V m V out Fig. 11. Second stage resolving earlier from metastability v o l t a g e [ V ] V in V m V out Fig. 12. Interactions between switching S/T stages overall hysteresis.The next part of the figure (until 28 ns) shows how the firstS/T is driven into metastability by carefully reverting V in when V m begins to switch. The waveform that the metastable S/Toutputs is such that the second S/T becomes metastable in thesame manner (from 28 ns onward). With both S/Ts metastable,the cascade is driven to output a sine wave (case (B5))followed by a constant output voltage (case (B3)). Duringthe sine output the non-inverting behavior of the single S/Tstages and the amplification of V in toV m and then V out can beobserved very clearly. In the end (from 70 ns) the second S/Tis resolving to VDD after which the first S/T also resolvesto VDD, forcing V out to GND. The input is continuouslyincreased and eventually crosses V H, , causing one last outputtransition – again as predicted in theory.Finally, Fig. 14 depicts the measured stable (truly stableplus metastable) points in the ( V in , V m , V out )-space. The grayline at the back is the projection of the 3D-curve to the plane V m over V in and thus represents the hysteresis curve of the 10 20 30 40 50 60 70 80 90 10000 . . . . . time [ns] v o lt ag e [ V ] V in V m V out Fig. 13. “Arbitrary” waveform created by operating both S/Ts in metastability . . . . . . . . . . . . V in [V] V out [V] V m [ V ] Fig. 14. Characteristic of the cascade first stage. The projection to the left plane ( V m over V out )shows (a rotated version of) the hysteresis curve of the secondstage. The most interesting one is the projection of the curveto the ground plane, i.e. V out over V in . This represents theoverall hysteresis of the cascade. And indeed this curve exactlymatches our prediction from Fig. 7.The 3D view also gives a better understanding of thereachability of the metastable states with V out neither HInor LO. These are only the states on the line connecting ( V in , V m , V out ) = (0 . , . , . V and (0 . , . , V.This line segment has two noteworthy properties: 1) Both itsprojections to the first and second S/T characteristic coincidewith metastable states – the output can only be held at anintermediate voltage when both S/Ts are metastable. 2) Itdoes not start from any stable state. This is not apparentin the 2D overall cascade characteristic. To reach any pointfrom that segment in a controlled manner, the first S/T hasto be metastable for a considerable time to produce thenon-monotonic waveform required to make the second S/Tmetastable. Intuitively, both arguments lead to a substantially lower probability of the S/T cascade to output an intermediatevoltage compared to a single S/T.VII. C ONCLUSION We have addressed the question whether the cascadingof Schmitt-Trigger stages improves the metastable behavior.Our comprehensive theoretical and simulation-based analysisshowed that the risk of an intermediate output voltage is indeeddecreased, and generally the probability of metastable behavioris significantly reduced. This is due to the fact that the firststage must necessarily be metastable for the second stageto become metastable as well. However, there are cases inwhich the interaction of the two states of the two S/T stagescauses extra transitions, and also some cases of intermediatevoltage are converted to transitions by the second stage. If theresulting, potentially misplaced transitions are a problem, theusefulness of the cascade should be carefully reconsidered inthe given application context.Another result is that metastable output behavior cannot besafely ruled out, even with an arbitrarily long cascade. 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