Efficient Metastability Characterization for Schmitt-Triggers
EEfficient Metastability Characterization forSchmitt-Triggers
J¨urgen Maier and Andreas Steininger
TU Wien, 1040 Vienna, Austria { jmaier, steininger } @ecs.tuwien.ac.at c (cid:13) Abstract —Despite their attractiveness as metastability fil-ters, Schmitt-Triggers can suffer from metastability themselves.Therefore, in the selection or construction of a suitable Schmitt-Trigger implementation, it is a necessity to accurately determinethe metastable behavior. Only then one is able to comparedifferent designs and thus guide proper optimizations, and onlythen one can assess the potential for residual metastable upsets.However, while the state of the art provides a lot of researchand practical characterization approaches for flip-flops, compar-atively little is known about Schmitt-Trigger characterization.Unlike the flip-flop with its single metastable point, the Schmitt-Trigger exhibits a whole range of metastable points dependingon the input voltage. Thus the task of characterization gets muchmore challenging.In this paper we present different approaches to determinethe metastable behavior of Schmitt-Triggers using novel methodsand mechanisms. We compare their accuracy and runtime byapplying them to three common circuit implementations. Theachieved results are then used to reason about the metastablebehavior of the chosen designs which turns out to be problematicin some cases. Overall the approaches proposed in this paper aregeneric and can be extended beyond the Schmitt-Trigger, i.e., toefficiently characterize metastable states in other circuits as well.
Index Terms —Schmitt Trigger, Metastability Characterization,SPICE
I. I
NTRODUCTION
To use digital abstraction in electronic circuits we have to“digitize” an essentially analog input, i.e. either assign logic HIor LO depending on whether it is above or below a threshold.In order to prevent oscillation of the output due to noise incase of an input voltage close to the threshold – like in case ofa comparator circuit –, the Schmitt-Trigger (S/T) uses a higherthreshold for rising transitions than for falling ones, leadingto a hysteresis (blue lines in Fig. 1). This, however, directlytranslates into a dependence of the threshold on the currentoutput state, which, in turn, implies a positive feedback fromthe output to the input. As a consequence, the S/T must besusceptible to metastability. This intuitive argument has beenmore formally supported by Marino [1] already, and morerecently Steininger et al. [2] have detailed several practicallyrelevant scenarios where metastability may occur and whereit may not. While there exist analytic solutions to calculatecertain properties such as the threshold voltages [3], none havebeen presented so far regarding metastability.
This research was partially supported by the SIC project (grantP26436-N30) of the Austrian Science Fund (FWF). V L V H GNDV DD γ γ γ stable stablemetastable V in [ V ] V ou t [ V ] Fig. 1: Stable and metastable states of a latch (dots) and anS/T (lines) forming the characteristic z-shaped curve.Actually S/T metastability is detrimental to its popular usefor “cleaning” noisy input signals, or conditioning metastableoutputs produced by other elements. Therefore it is crucial tofully characterize the metastable behavior of an S/T and, in theideal case, estimate a mean time between (metastable) upsets(MTBU), as it is common with metastability in flip-flops. Thelatter has been well researched since the seminal work byKinniment et al. [4], Chaney et al. [5], and Veendrick [6].However, as it turns out, the S/T case substantially differsby the fact that its input remains connected to the positivefeedback loop all the time, which ultimately results in theS/T exhibiting a whole range of metastable voltages V M ( V in ) rather than just one as in the flip-flop case. This makesthe analysis and characterization way more complicated, and,unfortunately, hardly any results are available, apart from thementioned papers [1] and [2].Before it is possible to analyze the traces and probabilitiesto enter and leave these metastable states, and thus achieve asimilar expression like the MTBU of a flip-flop, we need anefficient and accurate approach to characterize a given imple-mentation. In [2] the authors used transient analog simulationsto search for the metastable values, a very time consumingprocedure which includes lots of manual steps yet. In additionthey solely showed their analysis on a single circuit, a six-transistor implementation for a
65 nm technology. Thereforeit is not clear whether the results are transferable to otherimplementations and technologies as well. a r X i v : . [ c s . OH ] J un − + V in R C C V out R A R B V R Fig. 2: Schmitt Trigger implementation studied in [1].
Contribution:
While we cannot solve all the open prob-lems mentioned above in this paper, we extend the work bySteininger et al. in [2] by presenting and critically analyz-ing different approaches to simulate/evaluate the metastablebehavior of an S/T. This not only includes the (meta-)stablestates but also the behavior in their surrounding. These dataare of interest when investigating more advanced features suchas the overall probability to enter metastability or how quicklyit is resolved. More specifically, we • derive a more fine grained map (compared to [2]) of theoutput derivative V (cid:48) out over the V in − V out plane, which weuse as basis for more accurate estimations and analysesabout the general behavior. • determine all stable states, which partly lie in the unde-fined voltage range for certain implementations makingmetastable behavior very easily reachable. • carry out a preliminary analysis on metastability resolu-tion, which turns out be shaped exponentially (compara-ble to the flip-flop) but with varying parameter τ ( V in ) . • introduce a novel method, which is not limited to S/Ts,that makes stable points metastable and vice versa. • exploit plain DC analyses to determine metastability. • evaluate the single approaches by characterizing threecommon implementations and comparing the resultsamong each other and with the analytic results from [1].This paper is organized as follows: In section II we brieflyreview metastability of S/Ts followed by a description of theproposed characterization methods in section III. Results anddiscussion for three common implementations are shown insection IV which is followed by a conclusion and an outlookto future research possibilities in section V.II. B ACKGROUND
Metastability has been well researched for latches, formedby cross-coupled inverters, since the seminal work by Kinni-ment et al. [4] and Veendrick [6]. For these elements thereis even an equation for the mean time between metastableupsets (MTBU) available which relies, besides others, on themetastable resolution constant τ C . The amount of stable (two) We call the voltage range above a well-defined LO and below a well-defined HI, according to the logic specification, undefined. In a properlyfunctioning (metastability-free) circuit this range is crossed by steep tran-sitions only. V in V out V in = R A V R + R B V out R A + R B − MA V in = R A V R + R B V out R A + R B + MA V out = γ V out = γ V out = γ REGION 1REGION 2 REGION 3
Fig. 3: Phase diagram of the S/T inspired by Marino [1]and metastable (one) states is very small which is a directconsequence of the decoupled input. Fig. 1 shows the singlestates (dots), where V in represents the value inside the loop. A. Schmitt-Trigger Metastability
Unfortunately the situation is much more complicated forthe S/T since the input remains connected continuously andhence has to be considered as well. For this purpose Marino [1]modeled the S/T by a properly wired OpAmp (shown in Fig. 2)and carried out analytic considerations. He used the phasediagram ( V (cid:48) out over the V in – V out plane, as shown in Fig. 3with A equal to the amplifier gain and M being the outputsaturation voltage) to divide the behavior in three differentregions, where the output in each is governed by the followingequations:Region 1: dV out dt = V (cid:48) out = − τ ( V out − γ ) (1)Region 2: dV out dt = V (cid:48) out = 1 τ ( V out − γ ) (2)Region 3: dV out dt = V (cid:48) out = − τ ( V out − γ ) (3)The functions γ and γ represent the stable states while γ ,which connects the former, the metastable ones. In contrast tothe latch there are now infinitely many (meta-)stable valuesranging from the lower ( GND ) continuously to the upper( V DD ) supply voltage. As was shown in [2] with the properinput signal (exceeding the threshold and then steering back)any of these values can be reached and held forever. B. Schmitt-Trigger Metastability Characterization
The phase diagram as proposed by Marino is like a fingerprint of a Schmitt-Trigger implementation and helps the de-signer to understand and optimize the circuit. Therefore, inthis paper we are searching for ways to determine the phaseiagram in a fast, simple and yet accurate fashion for state-of-the-art implementations. As analytic considerations are basedon certain abstractions, which are a good way to recognizedependencies however lack accuracy especially for moderntechnologies, we decided to base our analysis on
SPICE simulations.
1) Stable States ( hyst ): Let us first focus on γ and γ .These are very easy to achieve by starting two DC analyses,one sweeping V in from GND to V DD and one in the oppositedirection. The threshold voltages, V L and V H , are easilyrecognized, as a small change on V in leads to a major jump on V out . Please note that, in contrast to the analysis of Marino, γ and γ are neither constant functions, nor straight lines inreal circuits. Instead the stable values start to deviate from( GND / V DD ) when the threshold voltage is approached (cp.Fig. 1). For certain implementations this change is substantial,as we will show in Section IV, and thus has to be carefullyanalyzed. This is even more important as these states areactually stable and thus much easier to reach than metastableones on γ , i.e., simply by a rising input stopping at a specificvalue (cp. [2]).
2) Metastable States:
Far more interesting for us is how-ever γ . Simply connecting γ and γ by a straight line, asderived by Marino, yields a first approximation, for moreaccurate result we have to resort however to more advancedmethods. Luckily metastable states can be uniquely identifiedby checking for V (cid:48) out = 0 , a property that all points on γ , γ and γ share. This immediately follows from the fact that onecan stay infinitely long in perfect metastability and of coursestable states.Steiniger et al. [2] used transient analysis for this purpose.In detail they observed for a pair of ˆ V in and ˆ V out if V out ( t ) in-or decreased during a simulation run. Based on the result theyimplemented a binary search algorithm for the value of ˆ V out in the next simulation until the desired accuracy was achieved.This procedure was then repeated for numerous values of V in along γ . Since this is a very time consuming task wesearched for more ingenious solutions and even found severalalternatives, which we will describe in the following.III. M ETHODS FOR OBTAINING γ Efficient and precise ways to determine the (metastable)characteristics of a Schmitt-Trigger are key for reliabilitypredictions or comparisons between different implementations.In the following we will elaborate several approaches to deter-mine the metastable states ( γ ), as this is currently the biggestchallenge. For accurate simulations we resorted to HSPICE using a
28 nm
UMC technology library. Comparisons with anolder
65 nm technology showed no qualitative difference sowe restrict ourselves to presenting the former in this paper.Our circuit model is pre-layout, but we consider a capacitiveoutput load of C L = 2 fF in our AC analyses. A. Static Analysis of Grid Points ( map ) Recall from Section II-B2 that all (meta-)stable states sharethe property V (cid:48) out = 0 . As a first approach we can cover the . . . . . . . . . . transient staticdeviationtime [ ns ] V ou t Fig. 4: Output derivative for transient and static simulations.The deviation stays constant as the projection (opaque greendots) shows. V in - V out plane with a regular grid and determine V (cid:48) out for eachgrid point to find where it gets (close to) zero. Albeit thisinitially appears quite untargeted and laborious, it providesus with a map that will turn out valuable for analyzing theresolution behavior later on.Listing 1: deriving I out in V in - V out plane in SPICE .DC VIN 0 supp width SWEEP VOUT LIN c o u n t 0 supp. PROBE DC I (VOUT)
Our approach uses built-in commands from
SPICE only, asdetailed in Listing 1: We sweep V in from to V DD ( supp ) insteps ( width ) corresponding to the grid. In the same way V out is swept ( count = V (cid:48) out , this isconsiderably faster but serves the same purpose, albeit we get I out as a result instead. To compare the results of static andtransient simulation (see Section III-B) in Fig. 4 we can usethe transformation V (cid:48) out · C L = I out , which leads however to aconstant deviation. That discrepancy is a result of the internalcapacitance of the S/T which we determined to be .
854 fF and whose value stays constant even for varying values of C L .In the following we will therefore use ˆ C L = C L + 1 .
854 fF for transformations between V (cid:48) out and I out .Note that our proposed DC analysis does not reflect poten-tial dynamic effects: In real circuits V (cid:48) in most certainly has aneffect on V (cid:48) out through coupling capacitances. However, in ourview this only restricts the possible paths a metastable statecan be reached, but not the actual value itself, since all (meta-)stable states are per definition static, i.e., V (cid:48) out = 0 . Thereforewe consider it fundamental to determine the static, generalcase in the first place – and this is what the DC analysisproperly does.Obviously we won’t be lucky enough to hit I out = 0 (or V (cid:48) out = 0 ) exactly this way, but those pairs of grid pointsetween which I out changes its sign already confine γ . In afirst step contour plots can be used to draw an (interpolated)contour line at I out = 0 , i.e., at the (meta-)stable line.Furthermore the map may serve as starting point for moreprecise estimations. B. Transient Estimation ( expAC ) When starting transient simulations in the grid points con-fining γ (changing sign of I out ) one observes traces thatare nearly perfect exponentials (see Fig. 4), as predicted bytheory [1]. This has major implications. Firstly, it suggests thatthe resolution behavior is comparable to the flip-flop, with themain difference, however, that the resolution time constant τ isnow not unique but varies with V in . This will become apparentin Section IV.Secondly, it gives us the possibility to infer the metastablevoltage by recording just a short piece. Assume we start in anarbitrary point ( ˆ V in , ˆ V out ) and observe the output, i.e., V out ( t ) and V (cid:48) out ( t ) in the course of the simulation. Since we assumethe trace to be exponential we get the following relations: V out = V M ± V x · exp (cid:18) t − ˆ tτ (cid:19) (4) V (cid:48) out = ± τ · V x · exp (cid:18) t − ˆ tτ (cid:19) (5)where ˆ t denotes the unknown time shift between our measure-ment and the actual resolution curve and V x > the unknownscaling factor of the exponential. Let us now apply the naturallogarithm on | V (cid:48) out | leading to ln( | V (cid:48) out | ) = ln (cid:20) τ · V x · exp (cid:18) − ˆ tτ (cid:19)(cid:21) + tτ By applying a linear fit to our simulation results we caneasily determine the value of τ , which is inversely proportionalto the slope. Going back to Equation (4) and expressing theexponential term by V (cid:48) out finally yields: V M = V out ∓ τ · V (cid:48) out V M is obtained by plugging in a single pair of measuredvalues for V out and V (cid:48) out . Note that we actually do nothave to know the absolute time (or the parameters ˆ t and V x , respectively): We used the time and value differencebetween some measured values of V (cid:48) out to determine τ , whilea consistent pair of ( V out , V (cid:48) out ) sufficed to finally obtain V M .For valid results, two aspects have to be considered: • Initially, V (cid:48) out observed by the transient analysis changesdisproportionately (cp. Fig. 4) leading to a bad fitting. Asa consequence the first samples have to be removed. • At some point the waveform changes from “leavingmetastability” (increasing | V (cid:48) out | ) to “approaching stablevalue” (decreasing | V (cid:48) out | ). By choosing initial conditionsand simulation time it must assured that this point is neverreached by the simulation. .
25 0 . .
35 0 . .
45 0 . .
55 0 . . − std loopadjust V in [V] | V ↑ M − V ↓ M | [ µ V ] Fig. 5: Absolute deviation between V M predictions based onthe resolution direction for different circuit implementations(cp. Section IV). C. Static Estimation ( expDC ) In accordance to the transient measurements of V (cid:48) out we alsosee an exponential growth of the static I out as we follow aresolution trajectory, which is reasonable as they only differby a constant factor. Therefore it is quite natural to apply thesame estimations as before also on I out . One can rewrite theexpressions in Equation (5) to V (cid:48) out = I out ˆ C L = 1 τ · ( V out − V M ) (6) ˆ C L /τ can be achieved by the slope of I out over V out , i.e., byfitting the data from the I out map. Plugging an arbitrary V out ,the corresponding I out and the known ˆ C L /τ into Equation (6)finally yields the metastable voltage V M .Compared to the transient analysis the calculations on I out are far easier to execute and thus less prone to errors.Both provide however the possibility to improve the limitedaccuracy of tools (due to numerical issues).Please note that for both, expAC and expDC , τ and V M can be determined twice: either for traces resolving themetastability to GND or for such resolving to V DD . Ideallyboth would render the same results. In reality, however, weget slightly different values for τ (which may indeed have aphysical reason), and slight deviations in V M (most likely dueto numerical issues, which have an exponential effect). For thelatter Fig. 5 shows the difference between the predictions forthe curve resolving to V DD ( V ↑ M ) and GND ( V ↓ M ) for expDC ,whereat results for expAC are slightly worse. For betteraccuracy we therefore determine V M (using the corresponding τ ) as the point where the two resolution curves meet. D. Binary Search ( binary ) A more pragmatic approach is binary , where we sweep V in from V L to V H , and for each value a binary search isperformed to find a fitting value of V out , i.e., where I out isero. This is very similar to the approaches in [2], [7] with thedifference that we use the static current instead of the transientoutput derivative.To our advantage SPICE has a mechanism to run a binarysearch built-in (called “Bisection”) which simplifies the taska lot. The corresponding code is shown in Listing 2. The firstline states that we want to bisect, and at most steps shallbe carried out. Note that this narrows down the initial intervalby a factor of , so most of the time the algorithm quitsearlier, as the demanded accuracy is reached first.Listing 2: bisection in SPICE . model optMod1 OPT METHOD=BISECTION ITROPT=40. param o ut Va l = optFunc1 ( vdd / 2 , vout VL , vout VH ).DC VIN i n V a l i n V a l 1 SWEEP OPTIMIZE= optFunc1+ RESULTS= optMeasure MODEL=optMod1
The second line sets the parameter outVal which determinesthe output voltage and the range within which it shall be swept.We used here the value of V out at V in = { V L , V H } as we haveto be sure to avoid the stable states. The search itself alwaysstarts at V DD / . The last line finally launches the DC analysisfor the input voltage in the range [ inVal , inVal ], meaning thatwe execute this search for each value of V in separately, sincewe were not able to convince SPICE to do that automatically.
E. Metastability Inversion ( inversion ) The reason why metastable states are hard to characterizeis the fact that it is close to impossible to actually reachthem even in simulations, since, by definition, the systemconsistently works towards leaving them. A good physicalanalogy is the inverted pendulum. Stable states, in contrast,are naturally assumed by the system. This observation suggestsreduced characterization effort if the cases could be reverted,i.e., stable points are made metastable and vice versa.With this in mind, let us model the system in the metastablestate as an (output) current source that is controlled by theoutput voltage, namely I out = K · ( V out − V M ) A positive current charges the load capacitance, i.e., in-creases V out , which in turn increases the current even more.For the voltage gradient we get V (cid:48) out = I out ˆ C L = K ˆ C L · ( V out − V M ) which yields an exponential function for V out , more specif-ically, with K > an exponentially growing one. We can,however, invert the sign of K by connecting a current source I L to the output, whose current is controlled by I out , i.e. I L = p · I out . Mathematically, this changes the current into the capaci-tance from I out to (1 − p ) · I out , and we get V (cid:48) out = (1 − p ) · I out ˆ C L = (1 − p ) · K ˆ C L · ( V out − V M ) I p I n I out V out ...... C L ( − p ) · I out p · I out = I L Fig. 6: Circuit setup to invert (meta-)stable points.which, for p > , yields a decaying exponential function andhence a stable solution.Intuitively spoken, any positive I out is overcompensatedby I L , such that C L , instead of being loaded by I out , nowgets discharged through that portion of I L that exceeds I out .Therefore ultimately V out is reduced, and, as a consequence, I out as well. This naturally drives I out towards zero, whichrepresents exactly the state that is normally metastable. Fig. 6shows the resulting circuit for I out > .Overall the added current source serves as a proportionalcontroller (for the current) that stabilizes the “inverted pen-dulum”. Implementing such an element in SPICE , and simi-larly in other simulation suites, is straightforward. The onlychallenge left is to choose a proper value for p , which is avery delicate task: In essence, p contributes to the gain inthe control loop and is hence, according to control theory,crucial for stability. Choosing p too low (very close to 1) leadsto slow stabilization and consequently long simulation times.Choosing p too high, in contrast, causes oscillating behavior.In order to come up with a guideline for a reasonable choiceof p we have used the example of the implementation shownin Fig. 12b that employs the same inverter loop as the latch.Consequently we could build on the model from Veendrick [6].By extending the latter with our controlled current sourcewe can approximate the behavior of the dynamic systemcomprising S/T and controller. From that it turns out that theright choice for p is p = 2 A (cid:32) (cid:114) − A (cid:33) ≈ A (7)with A being the product of the ( DC ) gains of each of thetwo inverters in the model. Note, however, that the invertergain is not constant, so the “ideal” p will change as we movealong γ . In our experiments we chose the highest gain, i.e.the one in the middle of the inverter’s transfer curve, whichyielded very useful values for p . Luckily SPICE supports thedetermination of the loop gain, so A can be obtained bythe code piece shown in Listing 3, whereat we connected aconstant voltage source to the input and set the initial value . . . . . . . I n I p (2) I p ( V ) (3) V (1) V V out [ V ] I n , I p [ µ A ] . . . . . . . I n I p (2) I p ( V ) (3) V (1) V V out [ V ] I n , I p [ µ A ] Fig. 7: Application of the
Newton-Raphson algorithm to finda stable value (marked by black dot) of V out for fixed V in .of V out appropriately. For the complete code refer to the tooldescribed in Section IV.To get as close as possible to the DC case we measurethe gain at very low frequencies ( × − Hz ), which isshown in line in the listing. Please note that different S/Timplementations will lead to different feedback models, suchthat Eq. (7) cannot be applied directly in these cases.Listing 3: measuring loop gain in SPICE . ac dec ’ 10 ’ ’ 0 ’ ’ 10 ’. l s t b mode= s i n g l e v s o u r c e = v l s t b. measure l s t b g a i n l o o p g a i n a t m i n i f r e q
The method of metastability inversion is not restricted to S/Tbut can easily be extended to also determine the metastablepoint of other circuits. We verified this by introducing a currentsource into a “latch-style” inverter loop (i.e. with unconnectedinput) which then quickly approached its metastable value.
F. DC Analysis ( static ) With metastability inversion transforming metastable statesinto stable ones we could use DC analysis to collect the valueson γ . While this works well, we discovered in the courseof our research, that already DC simulations on the unmodi-fied implementation are capable of delivering the metastablevalues. The reason for that is the Newton-Raphson algorithmwhich
SPICE uses to determine the DC operating point [8].Let us take a closer look at this procedure: Assume that wefixed V in in the metastable region and want to determine astable V out (we already know that there are exactly threepossibilities). For a stable value the current coming from thep-stack ( I p ) and the one flowing into the n-stack ( I n ) at theoutput have to be equal. Determining those currents for variousvalues of V out gives us traces like those shown in Fig. 7. Thethree stable states marked by black dots are clearly visible. Tostart the algorithm we have to make a guess, say we pick V .The next task would be (1) to determine the derivative of I p inthis point, i.e, I (cid:48) p ( V ) , (2) find the crossing point of the latterwith I n and finally (3) restart the procedure with V out = V ,i.e., the value in the crossing point. If we start close enough V DD . . V in V out Fig. 8: Flip-flop half used for DC metastability analysis.to V M the algorithm will approach it automatically. It canbe seen that a deviation of several tens of millivolts can betolerated for the initial guess, an accuracy easily achievableby connecting the last stable values of γ and γ by a straightline.After the first metastable value was found others followquickly as the current value of V M serves as starting point forthe search on the next one, whose value does not differ muchand is thus found very rapidly.For that reason the most important task is to get a goodinitial guess for the first value. If we are too far off, we willfind the stable state and thus end up with part of the hysteresisthat we already know. Assume we start in the point on γ thatis closest to γ . Due to this close proximity we can infer thatfor that choice the metastable value will be close to the peakvalue for V out on γ . Therefore, if we choose a slightly highervalue for V out we end up with a very good initial guess, sinceour starting point is closer to γ than to γ . The amount ofincrease is uncritical and can actually be chosen rather big, inour experiments up to V DD / .We varified our approach also on a flip-flop half, i.e., a loopof asymmetric inverters (width ratio / ) with a transmissiongate (see Fig. 8) in a similar fashion. In detail the input valuesto the first and second inverter were set to V DD / .
45 V and then
SPICE was asked to calculate the operation point.As a result we got V in = 0 . and V out = 0 . .IV. E VALUATION
Provided that an appropriate
SPICE description of thecircuit is available, the complete characterization process canbe carried out fully autonomous. Thus we implemented allthe approaches presented in the previous section in a smalltool which is publicly available . For the simulations presentedin the following, we used a
28 nm
UMC technology library( V DD = 0 . ) and determined the (meta-)stable states for equally spaced values of V in .The aim of these simulations is twofold: • We want to evaluate and compare the presented methodsin a practical application. To this end we apply them forcharacterizing three different S/Ts: a) the standard 6Timplementation ( std ) b) an inverter loop [9] ( loop ) and https://github.com/jmaier0/meat a) map . .
35 0 . .
45 0 . .
55 0 . − − − − − − − − − expAC expDCinversionstatic V in [ V ] d e v i a ti on [ V ] (b) V M predictions vs. binary . .
35 0 . .
45 0 . .
55 0 . V in [ V ] ˆ C L / τ [ µ F / s ] (c) resolution constant ( expDC ) Fig. 9: Simulation results for std .c) an adjustable hysteresis one [10] ( adjust ), as othercircuits in literature are heavily based on these. • The analysis and comparison of the S/T implementationsis as such important. In particular it is interesting to seehow far the behaviors differ among each other and alsofrom the theoretical results [1].
A. General Remarks
In principle, the resolution of all presented methods canbe made as high as desired. In practice there exist howeverlimitations such as the finite simulator precision (numberformat), the required run time and the available output fileformats. The latter caused heavy problems as we only managedto export results with positions after the decimal point (solelyfor binary we achieved by using a different method).The accuracy of the results is somewhat limited by theachieved resolution and the assumption of a perfectly ex-ponential resolution trajectory for expDC and expAC , thesimulation time for inversion , and in general by theaccuracy of the circuit and transistor models underlying theSPICE simulations (which we will neglect from now on, asthis issue is immanent to all simulation approaches). To verifythat the metastable states obtained through the various methodsare indeed accurate, we started transient simulations in each of . .
35 0 . .
45 0 . .
55 0 . − − − − − − − − − − expAC expDCinversionstatic binary V in [ V ] d e v i a ti on [ V ] Fig. 10: Deviation of V out after
200 ps . them and measured the output deviation after
200 ps . Fig. 10shows the results for std . As one can see binary , whichpredicts V M with a resolution of ± , has clearly the lowestdeviation and thus is the most accurate. Therefore we will use binary as golden reference for all further analyses, ratherthan continuing with the computationally intensive transientsimulations for accuracy validation.Where the single methods differ, however, is the effort one needs to invest. To quantify that, we try to approachthe metastable value reasonably close ( ± µ V ) and thencompare the required run times. Table I gives an overviewof the achieved results. As the hysteresis differs among theimplementations, the number of grid points between V L and V H (metastable grid points), and thus the run time, varies.Nevertheless, for the same circuit a comparison among differ-ent methods is still valid.TABLE I: Overview of simulation times simulation time [ s ]method std loop adjust metastable grid points
282 378 125 hyst .
825 2 .
012 1 . binary .
279 349 .
224 104 . map .
826 318 .
153 362 . expAC .
149 806 .
603 233 . expDC .
047 2 .
481 1 . inversion .
588 1552 .
542 447 . static .
850 0 .
939 0 . Since the target of ± µ V was quite deliberately chosen,let us review the impact of target accuracy on the run time foreach method: binary The amount of binary steps has hardly any impacton the runtime. We experienced a reduction by only %when switching from to iterations with a accuracyloss of four orders of magnitude. map The run time scales linearly with the amount of pointswhich is quite natural as each one is determined by aseparate DC analysis. expAC & expDC The accuracy increases only with a moreaccurate map . Apart from that, their simulation time isconstant. a) map . .
35 0 . .
45 0 . .
55 0 . − − − − − − − − − − expACexpDCinversion static V in [ V ] d e v i a ti on [ V ] (b) V M predictions vs. binary . .
35 0 . .
45 0 . .
55 0 . , ,
200 downwards upwards V in [ V ] ˆ C L / τ [ µ F / s ] (c) resolution constant ( expDC ) Fig. 11: Simulation results for loop . inversion The chosen gain p of the current source has ahigh impact on the simulation time. Higher gain decreasesrun time but also yields more instabilities, e.g. oscilla-tions. Increasing the simulation period helps to resolvethese, however the run time increases almost by the samefactor. static The simulation time is constant, and always thehighest possible accuracy is delivered. In our setting,however, the output data format limited the attainable(exportable) accuracy.Clearly there is still room for optimizations such as • determining I out solely for grid points close to themetastable line for map • better choice of the gain p in inversion or evenimproving the whole control loop dynamics by an integralor differential part • non-uniform simulation time for inversion which we left for future research. For this reason the presentedrun times shall only be used to get an intuition how long thecharacterization approximately takes.Since we use both transient and DC analyses overall weexperienced that the former are much harder to handle, asmore parameters have to be defined, primarily the time periodof simulation. In addition further complications such as cuttingthe first part of the simulation in expAC or an appropriate gainfor the current source in inversion have to be overcome.In total DC analyses achieve better results in shorter time withsimpler methods. During our research we even realized thatmost methods, in particular static , are also applicable toother problems, such as determining the metastable value ofa flip-flop. We consider this more a lucky coincidence than adesigned feature as it is a side effect of the utilized Newton-Raphson algorithm.
B. Standard Implementation ( std ) To compare our results with those from Steininger et al.we first analyze the implementation used in [2]. The transistorlevel circuit is shown in Fig. 12a.The achieved (meta-)stable line (shown in Fig. 9a, γ and γ solid, γ dashed) fits very well to the results published in [2]. Thus we conclude that our tool works as expected. The samefigure also shows a heat map of the output current I out in the V in - V out plane. Please note that the I out -spacing of the contourlines is linear. This means that close to the metastable line I out changes only moderately, as expected from the exponentialresolution trajectories predicted by theory.In contrast to the calculations of Marino [1], however, whose V (cid:48) out only depends on the distance to the final, stable state, ourresults show additional dependencies of I out . This can be seenvery clearly by observing its maximum and minimum, whichboth are near V DD / .Fig. 9b shows the (absolute) deviation of the predictedmetastable voltages from the ones of binary . Please notethat with the finite export number format deviations below × − V were out of reach. From our result we thereforededuce that static and binary are capable of deliveringthe same accuracy.Finally 9c shows the (inverse of the) resolution constant ˆ C L /τ determined by expDC . It significantly varies with V in ,with the biggest (best) value in the middle and the lowestat points close to the stable states, meaning that the latterare left more slowly. The values achieved for the up- anddown-resolving waveform are shown separately, but the graphsnicely overlap.The significant change of τ raises the interesting question V in V out V DD V DD M n M n M p M p M n M p (a) std V in V out V DD M p M p M p M n M n M n (b) loop Fig. 12: Transistor level circuit implementations. a) map .
44 0 .
46 0 .
48 0 . .
52 0 .
54 0 . − − − − − − − expAC expDCinversionstatic V in [ V ] d e v i a ti on [ V ] (b) V M predictions vs. binary .
44 0 .
46 0 .
48 0 . .
52 0 .
54 0 . V in [ V ] ˆ C L / τ [ µ F / s ] (c) resolution constant ( expDC ) Fig. 13: Simulation results for adjust .whether the quick resolution from the middle will cross thefar distance to the saturation faster than the slow one from theborders that only has a short distance to cross. In consequenceone might determine a worst starting point from which reso-lution takes the longest. However, the answer heavily dependson what is considered the threshold for “resolved”, and, mostimportantly, on how deep the initial metastability was (recallthat resolution time is essentially unbounded). . .
35 0 . .
45 0 . .
55 0 . V in [ V ] l oopg a i n Fig. 14: Memory loop gain of loop . C. Inverter Loop ( loop ) The second circuit we investigate (transistor level imple-mentation see Fig. 12b) is essentially a latch whose inputcan not be decoupled any more, i.e., a plain inverter loop(preceded by an additional inverter). The hysteresis is definedby the relation between the driving strength of the first inverter(transistors M p and M n ) and the weak feed back one ( M p and M n ). For the latter we reduced the width to one tenth.The I out map (see Fig. 11a) significantly differs from theone of std . First of all the contour lines are horizontal, muchmore like the prediction made by Marino in [1]. Secondlythe current changes much more rapidly than before, whichalso leads to much higher values for ˆ C L /τ (three orders of magnitude, see Fig. 11c), i.e., metastability is resolved muchquicker. According to Eq. (7) p can be calculated using thememory loop gain shown in Fig. 14. Picking the highest value( A = 700 ) results in p = 1 . which was confirmedto be a suitable value by simulations. Increasing p howeverquickly leads to oscillations of V out , whereat metastable pointswith higher loop amplification become instable earlier. D. Adjustable Hysteresis ( adjust ) In some applications it is important to adjust the hysteresisof the S/T during operation. One circuit that can be used forthis purpose is shown in Fig. 15. The value V B on an additionalinput alters the position and width of the hysteresis. In oursimulations we used V B = V DD as in this case the hysteresisis the widest and thus the most stable one. Anyway, similarbehavior could be observed for other choices of V B as well.The first remarkable thing in Fig. 13a is the relatively largepeak value of V out on γ . It reaches up to about . whichis one third of the supply voltage and almost certainly inthe forbidden region. Please recall (see Section II-B1) thatthose states can be easily reached by a ramp stopping at adefined value, implying that resilience against metastability isweakened a lot. The map furthermore reveals nearly vertical V in V out V DD V B V DD M n M n M n M n M p M p M p M p Fig. 15: Circuit implementation of adjust .ontour lines in the left half of the plot. This suggests, thatin this region the output slope is constant, i.e., we get rampsat the output. Very surprisingly, I out does not seem to dependon the distance to the stable state at all, as it was calculatedby Marino [1].The values of ˆ C L /τ (Fig. 13c) are comparable to std .However, since the stable states from below reach far into themid-voltage region the graph is not symmetric any more.V. C ONCLUSION AND F UTURE W ORK
In this paper we have presented several ways to charac-terize the metastable behavior of a Schmitt-Trigger includingestimations that increase accuracy beyond numerical precision,a novel method to convert metastable states into stable ones,and plain DC analysis that turned out to be already sufficientto accurately determine metastability. By applying them tothree common CMOS implementations we not only verifiedthat they work properly but were also able to compare them,giving an edge to DC rather than transient methods regardingaccuracy and run time. At the same time simulation resultsrevealed that the metastable behavior only partially followsthe theoretical predictions made in the past.For future work we want to use the results of this paperas starting point to derive an expression for estimating thereliability impact of metastable upsets in S/Ts, comparable tothe MTBU formula in flip-flops.R EFERENCES[1] L. R. Marino, “The Effect of Asynchronous Inputs on SequentialNetwork Reliability,”
IEEE Transactions on Computers , vol. 26, no. 11,pp. 1082–1090, 1977.[2] A. Steininger, J. Maier, and R. Najvirt, “The metastable behavior ofa schmitt-trigger,” in , May 2016, pp. 57–64,arxiv:2006.08319.[3] B. L. Dokic, “Cmos and bicmos regenerative logic circuits,”in
Cutting Edge Research in New Technologies , C. Volosencu,Ed. Rijeka: IntechOpen, 2012, ch. 2. [Online]. Available: https://doi.org/10.5772/34934[4] D. Kinniment and D. Edwards, “Circuit technology in a large computersystem,” in
Conference on Computers - Systems and Technology , Oct1972, pp. 441–450.[5] T. J. Chaney and C. E. Molnar, “Anomalous behavior of synchronizerand arbiter circuits,”
IEEE Transactions on Computers , vol. C-22, no. 4,pp. 421–422, April 1973.[6] H. J. Veendrick, “The behaviour of flip-flops used as synchronizers andprediction of their failure rate,”
IEEE Journal of Solid-State Circuits ,vol. 15, no. 2, pp. 169–176, Apr 1980.[7] S. Yang and M. Greenstreet, “Computing synchronizer failure probabili-ties,” in ,April 2007, pp. 1–6.[8]
HSPICE R (cid:13) User Guide: Basic Simulation and Analysis , Synopsys R (cid:13) ,June 2016, version L-2016.06.[9] Z. V. Bundalo and B. L. Doki´c, “Non-inverting regenerative cmoslogic circuits,” Microelectronics Journal