eSampling: Energy Harvesting ADCs
Neha Jain, Nir Shlezinger, Bhawna Tiwari, Yonina C. Eldar, Anubha Gupta, Vivek Ashok Bohara, Pydi Ganga Bahubalindruni
ee Sampling: Energy Harvesting ADCs
Neha Jain, Nir Shlezinger, Bhawna Tiwari, Yonina C. Eldar,Anubha Gupta, Vivek Ashok Bohara and Pydi Ganga Bahubalindruni
Abstract
Analog-to-digital converters (ADCs) allow physical signals to be processed using digital hardware.The power consumed in conversion grows with the sampling rate and quantization resolution, imposinga major challenge in power-limited systems. A common ADC architecture is based on sample-and-hold(S/H) circuits, where the analog signal is being tracked only for a fraction of the sampling period. In thispaper, we propose the concept of eSampling ADCs , which extend the structure of S/H ADCs withoutaltering its conversion procedure, while harvesting energy from the analog signal during the time periodswhere the signal is not being tracked. This harvested energy can be used to supplement the ADC itself,paving the way to the possibility of zero-power consumption and power-saving ADCs. The amount ofenergy harvested can be increased by reducing the sampling rate. We analyze the tradeoff between theability to recover the sampled signal and the energy harvested, and provide guidelines for setting thesampling rate in the light of accuracy and energy constraints. Our analysis indicates that e SamplingADCs operating with up to bits per sample can acquire bandlimited analog signals such that they canbe perfectly recovered (up to the distortion induced in quantization) without requiring power from theexternal source. Furthermore, our theoretical results reveal that e Sampling ADCs can in fact save powerby harvesting more energy than they consume. Furthermore, we show how these results imply that an e Sampling ADC acquiring a bandlimited signal at Nyquist rate with bit ADCs can harvest over dBmore energy than it consumes in the conversion procedure. To verify the feasibility of e Sampling ADCs,we present a circuit-level design using standard complementary metal oxide semiconductor (CMOS) 65nm technology. An e Sampling 8-bit ADC which samples at 40 MHZ is designed on a Cadence Virtuoso
Parts of this work were accepted for presentation in the European Signal Processing Conference (EUSIPCO) 2020 as the paper[1]. This project has received funding from the Benoziyo Endowment Fund for the Advancement of Science, the Estate of OlgaKlein Astrachan, the European Unions Horizon 2020 research and innovation program under grant No. 646804-ERC-COG-BNYQ, and from the Israel Science Foundation under grant No. 0100101. N. Shlezinger and Y. C. Eldar are with the facultyof Mathematics and Computer Science, Weizmann Institute of Science, Rehovot, Israel (e-mail: [email protected];[email protected]). N. Jain, B. Tiwari, A. Gupta, and V. A. Bohara are with Dept. of Electronics and CommunicationEngineering, Indraprastha Institute of Information Technology-Delhi (IIIT-D), New Delhi, India (e-mail: { nehaj, bhawnat,anubha, vivek.b } @iiitd.ac.in). P. Ganga is with Indian Institute of Science Education and Research (IISER) Bhopal, India(e-mail:[email protected]). a r X i v : . [ ee ss . SP ] J u l latform. Our experimental study involving Nyquist rate sampling of bandlimited signals demonstratesthat such ADCs are indeed capable of harvesting more energy than that spent during analog-to-digitalconversion, without affecting the accuracy. Index Terms
Energy harvesting, analog-to-digital conversion, sample-and-hold circuits.
I. I
NTRODUCTION
Physical signals are analog in nature, taking values in continuous sets over a continuous time interval.In order to process and extract information from such signals using digital hardware, they must beaccurately represented in digital form. Analog-to-digital converters (ADCs) thus play an important rolein digital signal processing systems [2]. ADCs are typically a major source of energy consumption, as theirpower dissipation grows with the sampling rate and the quantization resolution, and thus their ability toaccurately represent the acquired signal is typically limited by the available power [3]. Nowadays, ADCsare utilized in a multitude of energy-limited systems, including communication devices [4], wirelesssensors [5], and medically implanted devices [6]. Therefore, there is a growing need for ADCs capableof reliably acquiring signals while consuming low power.The existing strategies proposed in the literature to facilitate energy efficient acquisition of analogsignal can be divided into those taking a signal processing approach, and techniques focusing on circuitlevel design. Signal processing approaches typically aim for allowing the ADC to operate at reducedsampling rate and quantization resolution by accounting for how the acquired signal is processed andprior information on the signal itself [5], [7]–[10]. Additionally, in scenarios where the signal is acquiredfor some task, i.e., to recover some underlying information, it was recently shown that the desiredinformation could be accurately recovered from the output of low-resolution ADCs by properly designingthe acquisition system [11]–[14]. An alternative signal processing oriented method which does not limitthe rate and resolution of ADC is based on acquiring a portion of the analog signal to be processedwhile utilizing the remaining part for energy harvesting. This strategy, typically studied in the context ofcommunication receivers as simultaneous wireless information and power transfer (SWIPT), considerstime or power splitting of the analog signal [15]–[18]. However, it induces some inevitable loss on thesystem performance as only a portion of the signal is converted into a digital representation. Theseaforementioned signal processing methods typically focus on the signal model and the task for which itis acquired, without accounting for the ADC circuitry.2ircuit level methods rely on the hardware architecture of ADC devices. The circuit level approachgenerally considers designing energy efficient ADC circuitry, which is capable of operating with reducedpower consumption. This can be achieved by reducing the circuit power supply [6] and/or limiting theoperating frequency [19] in order to reduce the overall power consumption. An alternative techniqueis to modify the circuit components in existing ADC architectures and combine various designs in theacquisition, such as sample-and-hold (S/H) ADCs, flash ADCs, sigma-delta ADCs, and time-interleavedADCs, to improve their energy efficiency, see, e.g., [20]–[23]. Such circuit-oriented designs which focuson the hardware aspects of acquisition, do not account for the model of the analog signal and the taskfor which it is acquired.A popular power efficient ADC is the S/H based successive approximation register (SAR) architecture,which is capable of operating at high resolution and a small form factor with relatively low powerconsumption [24]. The power consumption of SAR ADCs can be further reduced by incorporating energyefficient switching schemes, as proposed in [25], [26]. In S/H architectures, the circuit used to sample theinput analog signal consists of two phases, acquisition phase and hold phase in each sampling period.In the acquisition phase, the S/H circuit tracks the input analog signal. The sampled value captured inthe acquisition phase is then converted into digital form, i.e., a sequence of bits, during hold phase.Therefore, during the sampling process of S/H ADCs, the input signal is processed only for a fraction ofthe overall sampling period (acquisition phase) and is neglected/discarded for the remaining time interval(hold phase) [27], [28]. The fact that the signal is not accessed in a dominant portion of the samplingperiod, motivates the extension of S/H ADCs, and particularly S/H SAR ADCs, to continuously utilizethe analog signal in order to mitigate power consumption.In this work, we combine signal processing tools with circuit level methods to propose an eSamplingADC , which harvests energy from the acquired signal while converting it into a digital representation.The e Sampling ADC builds upon the S/H ADC architecture while introducing an additional energyharvesting circuit. In the resulting architecture, the signal is harvested during hold phase, i.e., when it isnot utilized in conventional S/H ADCs. This operation allows e Sampling ADCs to harvest energy from thesampled signal without altering the conversion procedure. Our analysis of e Sampling ADCs formulatesthe theoretical foundations for joint acquisition and energy harvesting, and generalizes the experimentalresults of our previous work [29], which demonstrated that energy harvesting can be combined withsensing circuits. As opposed to SWIPT systems, in which the overall operation of the system is modifiedto allow energy harvesting while conventional ideal ADCs are assumed [18], e Sampling exploits aninherent property of ADC devices to harvest energy as a natural byproduct of their hardware architecture.This makes e Sampling an attractive technology which can be easily incorporated into existing devices.3ur theoretical study of e Sampling ADCs analyzes its potential in terms of the ability to harvest energywhile maintaining a desired accuracy of signal reconstruction. To that aim, we focus on the acquisitionof stationary random processes and characterize the resulting tradeoff between the ability to accuratelyreconstruct the signal from its samples and the energy harvested from it, referred to henceforth as the energy-fidelity tradeoff . Our analysis identifies how to set the sampling rate to optimize this tradeoff whenoperating under energy constraints or fidelity restrictions on the reconstruction. The results allow us tonumerically characterize the maximal accuracy in which any signal can be e Sampled using only harvestedenergy, i.e., without requiring any energy from its power source. The energy consumed in acquisitionis determined by the specific components comprising the ADC circuit. We show that e Sampling ADCsoperating with a typical set of ADC parameters are capable of fully reconstructing signals of variouspower spectral density (PSD) profiles with negligible distortion, while harvesting at least as much energyas they consume. In particular, we show that an e Sampling ADC with bits quantization can acquirea bandlimited signal at the Nyquist rate while harvesting more energy than it consumes.We then proceed to illustrate the hardware feasibility of such a device. To that aim, we design thecircuitry of an e Sampling 8-bit SAR ADC which samples at 40 MHz on 65 nm complementary metaloxide semiconductor (CMOS) technology, and provide guidelines for setting its parameters to achieve adesired amount of harvested energy. The experimental evaluation of the e Sampling SAR ADC circuit,carried out on the Cadence Virtuoso platform, shows that the amount of energy harvested can be muchlarger than the amount of energy consumed during the conversion procedure. This is achieved withoutaffecting the signal reconstruction accuracy when acquiring a bandlimited signal while satisfying Nyquistcondition. Our experiment indicates that the theoretical potential of e Sampling can be translated intoan actual ADC circuit, which accurately acquires analog signals while harvesting more power than itconsumes.The rest of this paper is organized as follows: In Section II, we present our e Sampling system model.Section III analyzes the associated energy-fidelity tradeoff. The circuit-level design and its experimentalstudy are presented in Section IV. Finally, Section V provides concluding remarks.II. S
YSTEM M ODEL
In this section, we detail the proposed ADC model from a high-level perspective. We begin by brieflyreviewing S/H-based SAR ADCs and their associated energy consumption in Subsection II-A. Then, wepresent how S/H ADCs can be extended into e Sampling ADCs which harvest energy in addition to signalacquisition in Subsection II-B. 4 ogic '1'Logic '0'
Time
Clk
Logic '1'Logic '0'
Clk
Time
Clk
S/H S/H T aq T h V ref I ref (t) Signal V ref I ref (t) S Ch SAR logic
ComparatorDAC + - Ch SAR logic
ComparatorDAC + - S Signal + Clk (a) (b)
Figure 1. S/H SAR ADC illustration: (a) acquisition phase (b) hold phase.
A. Sample-and-Hold ADC Model1) High-level description:
S/H is a common ADC architecture. Such ADCs acquire each sample intwo phases, determined by a switch S , as illustrated in Fig. 1: In the acquisition phase, the signal isconnected to a capacitor C h , referred to as a holding capacitor, which is charged to the input analogvoltage, as depicted in Fig. 1(a). The time required by the holding capacitor to charge to the input voltage,which dictates the acquisition time, is given by [24] T aq = α τ R on C h , (1)where R on is the on-resistance of the switch S , and α τ is the number of time constants, i.e., R on C h required for the capacitor to be fully charged.Once the acquisition phase is over, the hold phase begins, in which the discrete sample, i.e., thevoltage stored in the holding capacitor, is quantized into digital bits. During hold phase, whose durationis denoted by T h , the input signal is disconnected from the S/H circuit and C h holds the acquired voltageto accomplish the successful conversion of the acquired sample into digital bits as illustrated in Fig. 1(b).Both T h and C h , must be set to allow the quantization circuit of the ADC to complete the conversion.When the quantizer is based on SAR logic, the overall architecture is referred to as a SAR ADC. An n -bit SAR ADC consists of a comparator, digital-to-analog converter (DAC), and a SAR logical circuitwhich successively refines the digital representation. To allow successful quantization into n bits, thehold time required to quantize each sample must satisfy [28] T h ≥ nα τ R q C h , (2)where R q is the equivalent resistance of the quantizer binary scale switches. Therefore, the samplingperiod, i.e., the duration of acquiring a single sample, is lower bounded by the following expression T s = T aq + T h ≥ ( R on + nR q ) α τ C h . (3)5n S/H SAR ADCs, the on-resistance of the switch R on is commonly not larger than the resistanceof the quantizer binary scale switches R q . Thus from (1) and (2), it is evident that T h is typically muchlarger than T aq , particularly when using high resolution quantizers, such as ADCs with n ≥ bits.Consequently, the input signal, which is tracked only during the acquisition phase, is discarded duringmost of the sampling period.
2) Energy consumption:
In general, the energy consumption of a circuit is typically a function of thetime duration it is active, and the amount of power drawn from the supply, denoted here by V ref . As T h is typically much larger than T aq , most of the energy required by S/H SAR ADCs is consumed duringhold phase [25], [28].In particular, the only energy consumed during acquisition phase, denoted E aq , is that needed totoggle the sampling switch S . In contrast, the energy consumption during hold phase, denoted E hold , iscomprised of the energy used by each of the components taking part in the quantization: E hold = E DAC + E c + E sl , (4)where E DAC , E c , and E sl are the energy consumption of the DAC array, comparator, and SAR logic,respectively. Consequently, E hold effectively represents the power consumed per sample by S/H SARADCs [25], [28]. We elaborate on the quantities in (4), which are dictated by the specific circuit parametersused, in Section IV where a concrete circuit-level design is discussed. Here, we note that E hold typicallytakes the form of a second-order polynomial in the reference voltage V ref [30], i.e., E hold = a ( n ) V ref + a ( n ) V . (5)The coefficients a ( n ) and a ( n ) in (5) are positive constants determined by the number of bits n andthe quantization circuit parameters, and can grow dramatically with n . This makes energy consumption amajor bottleneck of high resolution ADCs, motivating the proposed e Sampling architecture detailed next.
B. eSampling ADC Architecture
As mentioned above, during hold phase, the capacitor C h holds the acquired voltage sample, whichis converted into a set of digital bits. In this interval, the input signal is disconnected from the circuitby the switch S . In order to mitigate the energy consumption of S/H SAR ADCs without modifyingtheir sampling and quantization procedure, we propose to harvest the input signal energy by connectingit to an energy harvesting circuit during the hold phase, as illustrated in Fig. 2. Henceforth, the proposedarchitecture is referred to e Sampling ADC.As depicted in Fig. 2, the energy harvesting capability is enabled by passing the signal observed duringhold time through a conditioning circuit, whose output is used to charge an energy harvesting capacitor6 EH to a voltage level V EH . The energy harvesting circuit can be designed using passive elements, as wedo in our proposed design detailed in Section IV. Hence, no external power supply is required [31]. Thepurpose of the signal conditioning circuit used in energy harvesting devices is to facilitate the storageof the energy of the signal in the capacitor C EH [32]–[34]. For instance, a rectifier can act as a signalconditioning circuit, reducing fluctuations in the amount of energy harvested in the presence of alternatingsignals. Similarly, voltage regulator circuits and DC-DC step up converters can also be used to enhancethe overall efficiency of the energy harvesting system [35]. The common measure for the quality of anenergy harvesting circuit is the efficiency parameter, denoted by η ∈ [0 , , which represents the fractionof the energy of the input signal that is harvested. Finally, in order to connect the input signal to thequantization circuit during acquisition time and to the energy harvesting circuit during hold time, thesampling switch S is replaced by a two-way switch ˜ S . A possible circuit design such a two-way switchis detailed in Section IV.The amount of energy consumed in acquisition phase given in (5) is dictated by the design parametersof the circuitry, which also affect the sampling rate via (3). In particular, the sampling duration is thesum of the acquisition time T aq and the hold time T h . Further, the amount of time during which energyis harvested from the input signal per sampling period is at most T h . Recalling that typically T h (cid:29) T aq ,a significant portion of the sampling interval can be allocated for harvesting energy from the input signal.Since energy is only harvested during hold time, in which conventional S/H ADCs do not utilize theanalog signal, the ability to harvest energy in e Sampling ADCs does not affect the acquisition operation .Specifically, for a given sampling rate, e Sampling ADCs implement the same conversion mapping asstandard S/H ADCs operating at the same rate. Nonetheless, e Sampling provides the ability to tradeacquisition accuracy for harvesting more energy. This is due to the fact that increasing the samplinginterval allows e Sampling ADCs to dedicate more time to energy harvesting, possibly at the cost ofdegrading the accuracy in reconstructing the analog signal from its digital representation.The goal of our analysis of e Sampling ADCs presented in the following section is to quantify thetheoretical potential benefits of such an architecture, which is capable of simultaneously acquiring analogsignals into a digital form while harvesting their energy. Both the amount of energy consumed inconversion and that harvested in e Sampling are determined by the specific circuitry, encapsulated in(5) and the energy efficiency parameter η , respectively. Therefore, in our analysis we fix the circuitparameters, e.g., a ( n ) , a ( n ) , η , etc., and express how the accuracy in reconstruction and the amount ofenergy harvested vary as the sampling interval changes. We are particularly interested in characterizingthe amount of energy harvested in the regime in which the distortion induced by S/H conversion isnegligible, e.g., Nyquist rate sampling of bandlimited signals, and understanding when is it possible for7 Sampling ADCs to operate at this regime while harvesting at least as much energy as they consume.Our theoretical analysis detailed in the sequel reveals that such a regime of operation is indeed feasiblewith typical ADC circuit parameters when acquiring bandlimited signals while using up to bits persample. III. e S AMPLING
ADC A
NALYSIS
In this section, we analyze the capabilities of the proposed e Sampling ADC in terms of the amount ofenergy one can harvest while meeting a given level of reconstruction accuracy, as well as the achievableaccuracy for harvesting a desired amount of energy. The interplay between these key performancemeasures is determined by the selection of the sampling rate, as we show in the following. We begin byformulating the signal model under which our analysis is carried out, and the corresponding problem ofcharacterizing the associated energy-fidelity tradeoff, which arises from the e Sampling ADC paradigmin Subsection III-A. Then, we derive the achieved normalized mean-squared error (NMSE) under theconsidered model in Subsection III-B. The derived NMSE is used to characterize the energy-fidelitytradeoff in Subsection III-C, and to obtain as a special case the maximal amount of energy which can beharvested when sampling a bandlimited signal at a rate satisfying the Nyquist condition, i.e., allowingperfect recovery. We demonstrate a few examples of energy-fidelity tradeoff curves for signals withdifferent spectral profiles in Subsection III-D. Finally, we discuss the pros and cons of e Sampling ADCin light of our analysis in Subsection III-E.
A. Problem Formulation
The e Sampling ADC detailed in Subsection II-B harvests energy during hold phase. This impliesthat more energy can be harvested by increasing the hold time, which in turn increases the samplingperiod, potentially degrading the ability to reconstruct the signal from its samples. Therefore, to unveilthe potential of e Sampling ADCs, we first wish to analyze the fundamental tradeoff between the amountof energy harvested in e Sampling and the resulting fidelity in signal reconstruction. We are particularlyinterested in: Quantifying the maximum amount of energy that could be harvested when acquiringbandlimited signals at the Nyquist rate, i.e., without compromising the signal reconstruction accuracy; and Characterizing the achievable NMSE when the ADC harvests at least as much power as it consumes.In the analysis carried out in this section we consider a stochastic input signal x ( t ) modeled as a zero-mean wide sense stationary (WSS) process, with variance σ x , and PSD S x ( f ) . The signal x ( t ) is sampleduniformly with sampling interval T s , resulting in the discrete-time signal x ( kT s ) , k ∈ Z , where Z is theset of integers. The sampled series is quantized with n bits per sample into the digital sequence ˜ x ( kT s ) .8 ignal C EH
Clk
S/H
SAR logic
Comparator ˜ S ˜ S ˜ S Signal conditioning circuit V ref I ref (t) VEH + - Ch DAC
Logic '1'Logic '0'
Time
Clk T h Figure 2. Proposed e Sampling ADC system model.
The digital representation is utilized to recover the analog signal x ( t ) using a linear reconstruction filter G ( t ) , which is designed to minimize the NMSE between x ( t ) and the recovered signal ˆ x ( t ) as in [10],[36]. The reconstructed signal is ˆ x ( t ) = (cid:88) k ∈Z G ( t − kT s )˜ x ( kT s ) . (6)The overall system is illustrated in Fig. 3.The NMSE in reconstructing x ( t ) from ˆ x ( t ) is given by ζ = 1 σ x T s (cid:90) T s E {| x ( t ) − ˆ x ( t ) | } dt, (7)where E {·} is the stochastic expectation. The amount of expected energy harvested per sampling periodis given by E h = η R h (cid:90) T s T aq E {| x ( t ) | } dt = ηR h T h σ x , (8)where η and R h is the efficiency and the resistance of the energy harvesting circuit, respectively. Asmentioned above, the energy harvesting circuit is comprised of passive elements, and does not requirean external power source. Therefore, the overall energy consumption per sample using the proposed e Sampling ADC can be given as E aq + E hold − E h as illustrated in Fig. 3. Recall that the overall energyconsumption is typically dominated by the energy used during hold phase, i.e., E aq (cid:28) E hold , and hencethe ratio of the amount of energy harvested to the energy consumption per sample can be approximatedas E ratio = E h E hold . The value of E hold is dictated by the power supply voltage V ref and the number ofquantization bits n , as well as the SAR architecture and circuit parameters, as we show for our designdetailed in Section IV.In the following subsections, we study the fundamental tradeoff between the reconstruction accuracy,modelled as the NMSE, and the portion of the energy consumed in analog-to-digital conversion to that9 uantization Recosntruction Filter G(t) Analog signal Discrete samples Analog signalDigital representationEnergy consumed Energy harvested E aq + E hold E h eSampler Figure 3. Acquisition and reconstruction via e Sampling ADC illustration. harvested by e Sampling, referred to as the energy-fidelity tradeoff . To trade energy efficiency for fidelity,we modify the sampling rate for a fixed quantization resolution n and fixed acquisition time T aq . Thereconstruction accuracy can be improved by increasing the sampling rate, however e Sampling ADC willharvest less energy, and hence the inherent tradeoff between these parameters. In particular, we focus onADCs operating with relatively high resolution, where energy consumption constitutes a major challenge.The following analysis sheds light on the potential of joint acquisition and energy harvesting. For example,it quantifies the minimal recovery NMSE which allows a fixed n -bit ADC to operate at zero power, i.e., E ratio = 0 dB. Alternatively, it allows identifying the quantization resolution n for which the e SamplingADC can sample a bandlimited signal at Nyquist condition and operate at zero power. For instance, weuse our results to show that bandlimited signals can be e Sampled at Nyquist rate with up to bits persample while harvesting more energy than that consumed. Finally, the characterization of the energy-fidelity tradeoff allows computing the maximal amount of energy which can be harvested for an allowedlevel of reconstruction accuracy for both bandlimited and non-bandlimited signals, as a function of theADC circuitry parameters. B. Reconstruction NMSE
In general, the NMSE depends on both the sampling rate as well as the quantization resolution [37].Since we focus on relatively high rate quantization, the NMSE due to quantization is well-approximatedby the dB rule-of-thumb [38, Ch. 23], and is thus on the order of − . n [24], resulting in a negligiblecontribution to the overall NMSE of less than roughly − for n ≥ . Therefore, henceforth the focus ison the the NMSE between x ( t ) and ˆ x ( t ) due to the sampling procedure alone, expressed in the followingtheorem, derived in [36]: Theorem 1:
The minimal achievable NMSE in reconstructing a uniformly sampled WSS signal x ( t ) with sampling frequency f s = 1 /T s using a linear reconstruction filter, G ( t ) is ζ ( T s ) =1 − σ x (cid:88) k ∈Z (cid:90) fs − fs | S x ( f − kf s ) | (cid:80) k (cid:48) ∈Z S x ( f − k (cid:48) f s ) df. (9)10o achieve (9), the linear recovery filter G ( t ) in (6) is set according to [10], [36], i.e., its frequencyresponse F ( G )( f ) should be set to F ( G )( f ) = S x ( f ) (cid:80) k ∈Z S x ( f − kf s ) , where F ( · ) denotes the Fourier transform.This digital filter setting results in the minimal achievable NMSE between x ( t ) and ˆ x ( t ) . Theorem 1generalizes the celebrated Shannon-Nyquist theorem, as stated in the following corollary: Corollary 1:
When x ( t ) is bandlimited and the sampling frequency satisfies Nyquist condition, theresulting NMSE is zero. Proof: If x ( t ) is bandlimited, then there exists some finite f m such that S x ( f ) = 0 for all | f | > f m .When the sampling rate satisfies Nyquist condition, then f s ≥ f m . Consequently, the summands in (9)are non-zero only at k = k (cid:48) = 0 , and hence ζ (1 /f s ) = 1 − σ x (cid:90) fs − fs | S x ( f ) | S x ( f ) df = 1 − σ x (cid:90) f m − f m | S x ( f ) | S x ( f ) df = 0 , (10)proving the corollary.We next give an example of how Theorem 1 is computed: Example 1:
Consider a bandlimited signal whose spectral support is [ − f m , f m ] for some f m > withflat PSD. The obtained NMSE for such signals computed via Theorem 1 is given by ζ (1 /f s ) = − f s f m f s ≤ f m , . (11)Fig. 4 illustrates of the recovery NMSE result in Theorem 1, showing which spectral portions of a signalwith a flat PSD as in Example 1 are preserved by the NMSE minimizing reconstruction. In particular, Fig.4 demonstrates how the complete spectrum is preserved when sampling above Nyquist rate, while sub-Nyquist sampling yields some recovery error due to aliased components. Fig. 4 also depicts the amountof energy harvested from the signal based on (8), showing that reduction in the sampling rate allowsto harvest more energy in e Sampling at the cost of less accurate recovery, leading to the energy-fidelitytradeoff of e Sampling analyzed in the sequel.
C. Energy-Fidelity Tradeoff
In order to express the energy consumed in acquisition, we must first specify the voltage of the powersupply V ref . This value should be larger than the amplitude of the input signal with high probability toavoid overloading the ADC. Consequently, in the following we write the value of V ref as some multiple K > of the input standard deviation, i.e., the supply voltage is written as V ref = Kσ x . This generalformulation allows us to relate the reference voltage with the overload probability of the quantizer, since11 igure 4. Illustration of e Sampling of a signal with a flat PSD for: (a) Sampling at Nyquist rate, while harvesting an amount ofenergy proportional to T h = 1 /f s − T aq ; (b) Sampling at sub-Nyquist rate, thus trading recovery accuracy for harvesting moreenergy. the overload probability satisfies P ( | x ( t ) | ≥ V ref ) ≤ K − by Chebyshev’s inequality [11]. Therefore, theratio between the expected energy harvested (8) and consumed (5) for e Sampling of a WSS signal canbe written as E ratio = ηR h ( T s − T aq ) σ x a ( n ) K σ x + a ( n ) Kσ x . (12)Recall that for a fixed sampling interval, e Sampling ADCs implement the same conversion mappingas conventional S/H ADCs. Consequently, when one does not account for the distortion induced inquantization as we do here, WSS signals acquired by an e Sampling ADC operating with sampling interval T s can be recovered with the NMSE ζ ( T s ) stated in Theorem 1. We therefore use the expressions for theachievable NMSE (9) and the energy ratio (12) to characterize the energy-fidelity tradeoff of e Sampling.Under the considered setting, we formulate how the recovery accuracy and the energy ratio behave asthe sampling period T s varies. Recalling that the acquisition time T aq is determined by the ADC circuitparameters (1), modifying the sampling period is equivalent to tuning the hold time T h . The energy-fidelity tradeoff of e Sampling is thus encapsulated in two complementary optimization problems: The12rst aims at finding the minimal achievable NMSE under a given energy constraint δ > , i.e., ζ o ( δ ) = min T s >T aq ζ, (13)subject to E ratio ≥ δ. Setting δ = 0 dB, implies that E hold = E h . Therefore, solving (13) with δ = 0 dB reveals the minimalNMSE achievable by an e Sampling ADC which harvests at least as much energy as it consumes, i.e.,when operating at zero power. A positive value of δ (in dB) implies an energy saving ADC whichharvests more energy than its consumption per sample, namely, converting the signal only adds powerto the system.An alternative formulation seeks to maximize the energy harvested under a given fidelity constraint (cid:15) > , i.e., E oratio ( (cid:15) ) = max T s >T aq E ratio , (14)subject to ζ ≤ (cid:15). For instance, consider a bandlimited signal. In such a case, one can achieve ζ = 0 by e Sampling atNyquist rate, and harvest energy ratio E optratio (0) , i.e., the maximal ratio of the harvested to energy tothe consumed one when seeking ideal recovery. For non-bandlimited signals, approaching zero NMSEgenerally requires infinitesimally small sampling interval, which is not feasible due to the lower boundon T s dictated by the ADC circuity in (3). Consequently, when acquiring non-bandlimited signals (orextremely wideband signals), one would typically be more interested in evaluating (14) for some smallyet feasible NMSE bound (cid:15) > .Problems (13)-(14) allow to characterize the energy-fidelity tradeoff, stated in the following theorem: Theorem 2:
Let T h ( δ ) be given by T h ( δ ) := δR h ησ x (cid:0) a ( n ) K σ x + a ( n ) Kσ x (cid:1) . By setting f s ( δ ) = T aq + T h ( δ ) , the solution to (13) is ζ o ( δ ) = 1 − σ x (cid:88) k ∈Z (cid:90) fs ( δ )2 − fs ( δ )2 | S x ( f − kf s ( δ )) | (cid:80) k (cid:48) ∈Z S Hx ( f − k (cid:48) f s ( δ )) df. (15a)Similarly, by letting T s ( (cid:15) ) be the maximal sampling interval satisfying ζ ( T s ( (cid:15) )) = (cid:15) in (9), then thesolution to (14) is E oratio ( (cid:15) ) = ηR h ( T s ( (cid:15) ) − T aq ) σ x a ( n ) K σ x + a ( n ) Kσ x . (15b)13 roof: The theorem follows by noting that ζ ( T s ) in (9) is monotonically decreasing in T s , while E ratio in (12) is a monotonically increasing function of T s . Consequently, both (13) and (14) are obtainedby identifying the minimal/maximal value of T s for which the constraint holds with equality, henceproving the theorem.In the following subsection we provide a few examples of energy-fidelity tradeoffs which arise fromthe above analysis. D. Examples
The characterization of the energy-fidelity tradeoff in Theorem 2 identifies the achievable energy ratiofor a given recovery accuracy and vice versa. It also reveals the achievable energy ratio when e Sampling abandlimited signal of maximum frequency f m ≥ with zero reconstruction error. In particular, combiningCorollary 1 and Theorem 2 indicates that this energy ratio is given by E oratio (0) = ηR h ( f m − T aq ) σ x a ( n ) K σ x + a ( n ) Kσ x . (16)An example of how Theorem 2 is computed for arbitrary sampling rates is given in the following: Example 2 (Flat PSD):
Consider again the bandlimited signal with flat PSD of Example 1. In this case,by (11), an NMSE of ζ (1 /f s ) ≤ (cid:15) is guaranteed by using f s ≥ f m (1 − (cid:15) ) . Consequently, by Theorem2 the energy ratio under fidelity constraint (cid:15) for such signals is given by E oratio ( (cid:15) ) = ηR h ( f m (1 − (cid:15) ) − T aq ) σ x a ( n ) K σ x + a ( n ) Kσ x . (17)The resulting energy-fidelity tradeoff curve for different numbers of quantization bits is depicted in Fig. 5under the following settings: We use K = 20 , guaranteeing a probability of over 95% that | x ( t ) | ≤ V ref ,while the ADC circuit parameters are set to f m = 19 . MHz, T aq = 2 . ns, C u = 10 fF, C c = 5 fF, C s = 0 . fF, R h = 23 .
75 Ω , A k = 1 . , V e = 0 . V, α τ = 5 , V ref = 0 . V, g = 0 . , and η = 0 . .Finally, the signal power σ x is accordingly set to V K .The specific design parameters used in evaluating Fig. 5 correspond to the e Sampling ADC circuitdesign presented in Section IV, and are in the typical ranges provided in previous works on ADCcircuitry, e.g., [30], [39], [40]. The efficiency of the energy harvesting system η is in line with similarvalues reported for energy harvesting circuits in [41]–[43].As expected, the achievable energy ratio in Example 2 coincides with (16) when perfect recoveryis required, i.e., (cid:15) = 0 . The energy ratio characterized in (17) is increased by reducing the samplingrate, which in turn increases the reconstruction error, (cid:15) , as illustrated in Fig. 4. The fundamental balancebetween these measures follows from the structure of e Sampling ADCs, in which increasing the hold14 igure 5. NMSE ( ζ ) versus E ratio , flat PSD. time degrades the ability to recover the signal from its samples, while allowing to harvest more energy.This unique property of e Sampling can lead to ADCs which harvest more power than they consume, asobserved in Fig. 5.The results shown in Fig. 5 demonstrate that an e Sampling ADC with up to bits acquiring abandlimited signal can harvest more power than it consumes while sampling at Nyquist condition, andhence achieving zero-approaching reconstruction error. While the ability of e Sampling ADCs to sampleat Nyquist rate and zero-power is observed in Fig. 5 for signals with flat PSDs, it holds for arbitraryPSD shapes as long it is bandlimited to f m and the variance of the signal is σ x . This follows since by(12), the energy ratio for a given sampling rate and signal variance does not depend on the shape of thePSD. However, for the ADC to operate at zero power with higher resolution quantization, one has tosample below the Nyquist rate and hence compromise in reconstruction error. In particular, each of thecurves in Fig. 5 reaches zero NMSE for f s = 2 f m , while reducing the sampling rate allows achievingimproved energy ratio at the cost of reduced reconstruction accuracy, reaching poor recovery performanceof ζ = 0 . as f s is reduced to . f m . It is emphasized that for a given sampling rate, e Sampling ADCsimplement the same acquisition mapping as conventional S/H ADCs, and thus their the ability to harvestenergy using e Sampling ADCs does not come at the expense of conversion accuracy. However, e Samplingprovides to possibility to increase the amount of energy harvested by increasing the sampling interval,which in turn may degrade the ability to recover the analog signal.As discussed above, while the recovery NMSE depends not only on the sampling rate but also on the15 igure 6. NMSE ( ζ ) versus E ratio , unimodal PSD. shape of the PSD S x ( f ) (9), the energy ratio for a fixed sampling rate is affected only by the overallinput energy σ x = (cid:82) S x ( f ) df (12). This follows from the fundamental difference between the twoobjectives of e Sampling, i.e., acquisition and energy harvesting: The purpose of acquisition is to allowthe complete signal, whose profile depends on the shape of its PSD, to be recovered from its digitalrepresentation. However, energy harvesting aims at extracting energy from the signal without having tomaintain sufficiency or to avoid distorting the signal, and is invariant of the specific shape of its PSD.The dependency of the energy-fidelity tradeoff on the PSD profile is demonstrated in the following twoexamples which, unlike Example 2, consider non-purely-bandlimited signals:
Example 3 (Unimodal PSD):
Let x ( t ) be a WSS signal with a PSD given by S x ( f ) = αe − f σ ,where α = σ x √ πσ such that (cid:82) ∞−∞ S x ( f ) df = σ x . The parameter σ controls the PSD width, and is setto σ = f m / . The resulting energy-fidelity tradeoff computed via Theorem 2 under the ADC circuitparameters used in Example 2 is depicted in Fig. 6, along with an illustration of the PSD. Example 4 (Multimodal PSD):
Let x ( t ) be a WSS signal with a PSD S x ( f ) = α ( e − ( f − f m)22 σ + e − ( f + f m)22 σ ) .Here, σ is set to σ = f m / . This PSD profile and the energy-fidelity tradeoff evaluated using Theorem2 under the ADC circuit parameters used in Example 2 is depicted in Fig. 7.These examples illustrated in Figs. 6 and 7 demonstrate that e Sampling ADCs applied to signals withsuch spectral profiles can operate with zero power for up to n = 16 bits of quantization resolution, whileachieving approximately ideal reconstruction. Observing Figs. 6-7 and comparing them to Fig. 5, wenote that different PSD profiles lead to different energy-fidelity curves. This property is solely due to the16 igure 7. NMSE ( ζ ) versus E ratio , multimodal PSD. dependence of the achievable NMSE on the PSD, which follows from Theorem 1, since both the amountof energy harvested from a stationary signal as well as that consumed in e Sampling do not depend onthe spectral profile of the signal, but on the sampling rate and the variance σ x .In particular, the amount of energy harvested (8) when e Sampling at f s = 2 f m is numerically evaluatedas . pJ, while the corresponding amount of energy consumed (21) when using n = 8 bit quantizers is . pJ. This implies that the e Sampling ADC is able to harvest much more energy from the signal thanit consumes in converting it into a digital representation, as the energy ratio indicates an energy gainof . dB. In particular, it is observed that e Sampling ADCs operating with up tp bits per sampleare capable of saving power. However, this mode of operation comes at the cost of increased NMSE forhigher values of n . The examples presented in this subsection indicate that the power consumption ofhigh resolution ADCs can be notably reduced and even mitigated by properly combining acquisition andenergy harvesting via e Sampling. In Section IV we demonstrate that these results do not follow only froma numerical evaluation of our theoretical results, but also reflect the performance in terms of recoveryaccuracy and energy efficiency of a dedicated e Sampling ADC circuit design.
E. Discussion
Our characterization in the previous subsections focuses on the general family of stationary signals.When the signal obeys some structure, e.g., it is known to be sparse in the frequency domain, idealrecovery can be achieved at low sampling rates using generalized sampling methods [2], allowing17o harvest more energy without affecting the recovery NMSE. This indicates that the energy-fidelitytradeoff of e Sampling ADCs can be further improved by accounting for structured signals, as commonlyencountered in communication [8] and radar [9] systems. We leave the analysis of e Sampling of structuredsignals for future work.The fact that e Sampling gives rise to ADCs which operate with zero power and can even harvest moreenergy than they consume, makes it an attractive technology for low-power systems, such as internetof things devices, sensor networks, as well as wearable and implantable medical units. However, theapplicability of the proposed e Sampling ADC is limited in some scenarios since its architecture is basedon S/H ADCs. For example, S/H ADCs typically operate at sampling rates below GHz, and are notsuitable for operating at extremely high sampling rates, where flash ADCs are more commonly used.While we conjecture that the concept of e Sampling, namely, the integration of energy harvesting intosignal acquisition, can also be combined with alternative ADC technologies other than S/H, we leavethis study for future research.While our analysis focuses on WSS signals for analytical tractability, the proposed e Sampling ADCsapplies to a much broader family of acquired analog signals. For example the e Sampling ADC circuitrydetailed in the following section is experimented when acquiring a sinusoidal signal, demonstrating itsability to accurately reconstruct the signal in a power saving manner. Furthermore, our proposed analysisis based on linear recovery, being a common reconstruction framework in sampling theory. In particular,the reconstruction of Nyquist rate sampled bandlimited signals, shift-invariant signals, and various otherstructures studied in the literature, is based on linear filtering [2]. However, the architecture of the e Sampling ADC is invariant to the reconstruction mechanism, and alternative recovery schemes wouldresult in a different characterization of the energy-fidelity tradeoff.IV. e S AMPLING
ADC C
IRCUIT - LEVEL D ESIGN
In order to demonstrate the hardware feasibility of the concept of e Sampling, we present the circuit-level design of such a device. In particular, we design an e Sampling ADC circuit based on the modelshown in Fig. 2 using standard 65 nm CMOS technology, and carry out its experimental study using aCadence Virtuoso platform. In order to design the e Sampling ADC based on the high-level architectureillustrated in Fig. 2, one has to design its three main sub-blocks: The two-way switch ˜ S ; the quantizerlogic; and the energy harvesting circuit. We thus first elaborate on each of these sub-blocks, after whichwe present the experimental study. 18 ref V ref Clk' Clk' ClkC B M1 (b)Clk M2M3M4 M5 M6 I1I2
Clk' Mp (a) x(t) x(t) quantizerenergyharvestingcircuit Figure 8. Circuit diagram of (a) PMOS transistor switch, (b) NMOS bootstrapped switch.
A. Two-way switch
The two-way switch ˜ S allows the input signal to be connected to the hold capacitor during acquisitionphase and to the energy harvesting circuit during the hold phase. In our design, ˜ S is implemented usingtwo one-way switches, one for each operation phase, namely, when one switch is open, the other isclosed. Each of these switches is realized using a different topology. The switch designed to connectthe input signal to the energy harvesting circuit is implemented using a PMOS transistor, as illustratedin Fig. 8(a). The PMOS transistor turns ON when the clock signal Clk is at logic ’0’, indicating thathold phase is active. When
Clk is at logic ’1’, it turns OFF and isolates the input signal from the nextblock. In order to allow both switches of ˜ S to utilize the same single clock pulse, the switch designedto connect the input signal with the quantizer is implemented using an NMOS transistor, which turns onwhen Clk is at ’1’.The on-resistance of a MOS transistor, which determines the value of R on in (1), is sensitive tofluctuations in the input signal and may vary accordingly [24]. Such variations in R on may introducea non-linear distortion at the output of the ADC. To avoid such distortion, we use an NMOS bootstrapswitch to connect the input signal to the quantizer, which ensures a constant R on , as proposed in [44]. Thedesign of the NMOS transistor based bootstrapped switch used in this work is illustrated in Fig. 8(b). Toachieve nearly constant R on , the gate of the transistor M in Fig. 8(b) is bootstrapped using two PMOStransistors M and M , three NMOS transistors M , M and M , and one capacitor C B , following[44]. Two CMOS inverters I and I are also employed in the structure to generate the required clock The term ‘ implement ’ used here implies the design/simulation of the circuit in Cadence Virtuoso platform, in line with thesimilar usage of this terminology in [20]–[23], [26]. R on as well as the hold capacitor C h affect the setting of the acquisitiontime T aq , as follows from (1). To maximize the amount of energy harvested, small values of T aq arepreferable, so that more time could be allocated to harvesting the input signal energy. Reducing R on requires increasing the width of the transistors [24], which in turn increases the device capacitance, andthus reduces the operating speed of the ADC. In addition, wider devices may result in charge injection[45], which degrades the signal-to-noise-distortion ratio (SNDR) of the ADC, and hence the performanceof the ADC. Alternatively, employing small values for C h results in mismatch issues and sampling noise,which degrade the ADC conversion accuracy [46], [47]. These drawbacks require the acquisition time T aq to be large enough such that the ADC performance is not compromised, and is in fact the primaryreason S/H ADCs are typically limited to operate with sampling rates below 1 GHz, as discussed inSubsection III-E. B. Quantizer
The dedicated e Sampling ADC circuit design is based on S/H SAR ADC architectures [25], [30], [48]as illustrated in Figs. 1-2. Such quantizers generally consist of a DAC, a voltage comparator and a SARlogic, which map the voltage of the hold capacitor (also known as the total capacitance of DAC array) intoan n -bit value by successively refining the digital representation using a binary search algorithm. In our e Sampling ADC circuit we use a single-ended merge capacitor switching (MCS) based SAR ADC. Forsuch devices, the total capacitance of the DAC array is C h = 2 n − C u , where C u is the unit capacitanceof the DAC array, as illustrated in Fig. 9.In particular, during acquisition phase the input signal x ( t ) is connected to the top plate of the DACcapacitor array, while the bottom plate is connected to the common mode voltage, i.e., V cm = V ref . Oncethe acquisition phase is over, the voltage at the top plate of the DAC capacitor array is reduced bycommon mode voltage, and hence equals to x ( kT s ) − V ref / . The top plate of the DAC capacitor arrayis connected to the positive terminal of the comparator, while the negative terminal of the comparator isgrounded. The comparator then compares the voltage of its positive terminal with its negative terminal. Ifthe voltage at the positive terminal is higher than the negative terminal, the comparator yields an outputof logic ‘1’, else logic ‘0’. The output of the comparator is passed to the SAR logic, which resolves themost significant bit (MSB). The decision on the MSB is fed back to the DAC and the bottom plate of thelargest capacitor of DAC capacitor array is switched from V cm to ground (if MSB=1) or V ref (if MSB=0).This operation changes the voltage at the top plate of the DAC capacitor array, and a new decision ismade by the comparator, which is sent to the SAR logic to resolve the second MSB and so on. The20 n-2 C u u C h C u C u R q V ref V cm Figure 9. DAC capacitor array schematic diagram. process continues for all n bits. The overall resistance of the switches is determined by the binary scaleswitch resistance, R q , as illustrated in Fig. 9.As discussed in Subsection II-A, the energy consumption of S/H SAR ADCs is effectively dictatedby its quantization sub-blocks. Therefore in the following, we detail the circuitry used for the quantizeralong with its energy usage per sample.The voltage comparator is implemented using a dynamic latch. The energy consumed per sample of adynamic latch comparator is given by [30] E c = nC c V + 2 V ref γ n , (18)where γ n := V e C c (cid:0) n ln 1 /A k + n ( n +1)2 ln 2+ n (cid:1) , C c is the capacitive load of the comparator, A k is the gainduring regenerative phase, and V e is the ratio of the drain current of the device with its trans-conductance[39]. The SAR logic is realized using two arrays of shift registers that operate in serial-in-parallel-outand parallel-in-parallel-out modes [49]. Each register is implemented using a D flip-flop circuit, and theresulting energy consumption is given by [30] E sl = 16 n gC s V , (19)where C s is the input capacitance of the D flip-flop, and g ∈ [0 , is the total activity parameter of theSAR logic. Finally, the DAC is based on a binary-weighted capacitive DAC, designed using the MCS21cheme [25]. The energy consumption of the MCS DAC is given by [25] E DAC = ρ n nC u V , (20)where ρ n = (cid:80) n − i =1 n − − i (2 i − .To summarize, the total energy consumption during hold phase of our dedicated e Sampling ADC circuitdesign, which dictates the overall energy consumed per sample, is given by E hold = E DAC + E sl + E c( a ) = V (cid:0) ρ n C u + nC c + 16 n C s g (cid:1) + 2 V ref γ n , (21)where ( a ) follows from (18), (19), and (20). The energy term in (21) obeys the second-order polynomialmodel of (4), used in our analysis of e Sampling ADCs in Section III.
C. Energy Harvesting Circuit
The proposed e Sampling ADC harvests the input signal energy during hold phase and stores thisenergy in a capacitor, C EH . As detailed in Subsection II-B, energy harvesting circuits typically consistof a capacitor, in which the harvested energy is stored, and a signal conditioning circuit, whose purposeis to facilitate the charging of the capacitor. In our design, we do not include a signal conditioningcircuit and forward the input signal directly to C EH during hold time. This simplified design is sufficientfor our experimental purposes, where we use synthetic controlled input signals with strictly positivevoltage values. However, in order to achieve efficient energy harvesting of a low voltage complexrapidly alternating signals, one should also include signal conditioning devices, such as a rectifier, voltageregulator, and DC-DC converter.To quantify the maximum amount of energy that can be harvested in an analytically tractable manner,we consider the case where the input signal is approximately constant during the hold phase, i.e., x ( t ) ≈ x ( T s ) for each t ∈ [ T aq , T s ] . The purpose of this approximation is to facilitate characterizing the amountof energy harvested in a tractable manner. In addition, we focus on the scenario in which the capacitoris empty at the beginning at the hold phase, namely, the voltage on the capacitor C EH , denoted V EH (0) ,satisfies V EH ( T aq ) = 0 . In this setup, the capacitor voltage at the end of the hold phase, i.e., at timeinstance t = T s , is given by V EH ( T s ) ≈ x ( T s ) (cid:18) − e − T h R h C EH (cid:19) , (22)22here, as defined in Subsection III-A, R h is the resistance of the energy harvesting circuit. This resistanceis dictated here by the on-resistance of the PMOS transistor in the two-way switch. The amount of energyharvested in such a sampling interval is given by E h = 12 C EH V ( T s ) ( a ) ≈ C EH (cid:18) − e − T h R h C EH (cid:19) x ( T s ) ( b ) ≈ T h C EH (cid:18) − e − T h R h C EH (cid:19) T h (cid:90) T aq | x ( t ) | dt, (23)where ( a ) follows from (22), and ( b ) stems from the fact that the input is approximately constant duringthe hold phase. Comparing (23) and (8) reveals that the efficiency of this simple energy harvesting circuitcan be approximated as η ≈ R h C EH T h (cid:18) − e − T h R h C EH (cid:19) . (24)The expression for the energy harvesting efficiency in (24) can be used to provide guidelines fordetermining the capacitance C EH used in the circuit. In particular, it can be shown that (24) is maximizedwhen C EH ≈ . T h R h . However, the derivation of (24) is carried out assuming that the capacitor is emptyat the beginning of the hold phase. This implies that its stored energy is transferred to some externalstorage device, e.g., battery, after each sample. In practice, energy transfer typically takes much longerthan a single sampling interval, and thus it is preferable to carry out such a transfer only once everymultiple samples. This is achieved by using a capacitor with a larger value of C EH , which allows to storemore energy and provides a nearly constant voltage at the load, but requires more time to charge. Inparticular, in our experimental setup detailed in Subsection IV-D, we set C EH = 42 . T h R h , which results inthe capacitor taking approximately samples to charge up. Under such a setting, the period dedicatedto transferring its energy once it is fully charged, during which energy harvesting is inactive, has only aminor effect on the overall harvested energy. D. Experimental study
To validate that the energy saving potential of e Sampling ADC observed in Section III also reflectsits behavior in a real world environment, we next evaluate the e Sampler circuit design. To that aim, aschematic of the e Sampling ADC circuit has been created in Cadence Virtuoso platform based on thecircuit-level design detailed in the previous subsections. The proposed e Sampling ADC operates at asampling frequency of MHz with an n = 8 bit quantizer. For our experimental purpose, we use asinusoidal signal, being a common benchmark for evaluating the accuracy of ADC circuits [50, Ch. 2].23 − − − − − − Frequency (MHz) P o w er Sp ec t r a l D e n s i t y SNDR > 48 dB27 dB Fundamental frequencyRMS quantization noise levelFFT noise floor
Figure 10. FFT plot of reconstructed signal for 8 bit e Sampling ADC.
The maximum frequency of the input signal is . MHz, thus the sampling rate satisfies the Nyquistcondition. The amplitude of the signal varies from 0 to V ref . Here, we use an energy harvesting capacitorof C EH = 40 nF, while the remaining parameters are the same those detailed in Examples 2-4.We first assert that the e Sampling ADC is indeed capable of accurately reconstructing the signalsampled at the Nyquist rate. To that aim, we depict the fast Fourier transform (FFT) of the reconstructedsignal, computed using a 1024-point FFT, in Fig. 10. As expected, the FFT noise floor is determined bythe SNDR due to quantization, computed by the dB rule of thumb as approximately dB, with theadditional FFT processing gain of
10 log (1024 / ≈ dB [50, Ch. 2]. In particular, the gap betweenthe noise floor observed in Fig. 10 and the energy of the signal at its central frequency of . MHz, isroughly . dB, settling with the theoretical performance of ADCs satisfying Nyquist condition, andindicating that the designed e Sampling ADC accurately reconstructs the observed analog signal.Next, we focus on the energy harvesting circuit of the designed e Sampler, in order to identify howmany sampling rounds are required for the capacitor to charge up. To that aim, we plot in Fig. 11 thevoltage on the energy harvesting capacitor over time. Observing Fig. 11, we note that for the given inputsignal, the capacitor reaches a steady level of V EH = 481 . mV after . µ s, which correspond to samples at MHz. Based on Fig. 11, we design the e Sampling ADC to transfer the energy storedin its energy harvesting capacitor once every samples. We dedicate approximately . µ s for eachtransfer, during which the energy harvesting circuit is inactive, resulting in each cycle of harvesting andtransferring taking approximately samples. Consequently, the effective amount of energy harvested24 Time ( s) V o l t a g e ac r o ss C E H ( V ) V EH = 481.152 mV 8.423 s Figure 11. Voltage obtained across C EH for 8 bit e Sampling ADC. per sample of the e Sampling ADC is given by E h = 12 · C EH V (337 · T s ) = 9 . pJ. (25)The amount of energy harvested per sample, evaluated in (25) based on the experiment in Fig. 11, doesnot represent the overall energy balance of the e Sampling ADC, as it accounts only for the amount ofenergy harvested. Therefore, to demonstrate that the e Sampling ADC circuit design not only accuratelyrecovers the signal and harvests energy, but also saves more energy than it consumes, we next evaluateboth the energy harvested and the energy consumed by the ADC circuit. The average energy consumptionof our designed circuit is computed by evaluating the current drawn from its reference source V ref , denoted I ref ( t ) , and thus the energy consumed at each time instance can be obtained by E cons ( t ) = V ref (cid:90) t I ref ( τ ) dτ. (26)The resulting growth of both the energy consumed and the energy harvested are depicted in Fig. 12.Observing Fig. 12, we note that the e Sampling ADC harvests much more energy than it consumes,while still being able to accurately reconstruct its input signal as demonstrated in Fig. 10. In particular,the consumed energy is shown to grow in an approximately linear manner, with an average energyconsumption of . pJ per sample. The maximal amount of energy which can be obtained is dictatedby the external battery, to which the harvested power is periodically transferred. Comparing this to (25)reveals that the true energy ratio of the e Sampling ADC, which periodically transfers its harvested energyto an external battery, is approximately . dB, which is within a relatively small gap from the theoretical25 Time ( s) E n e r g y ( J ) Energy consmuedEnergy harvested
Charge transfer to batteryEnergy harvesting Energy harvesting
Figure 12. Total energy harvested and energy consumed versus time for an 8 bit e Sampling ADC. results observed in Subsection III-D. This gap can be further reduced by using more advanced energyharvesting circuitry, compared to the simplistic design detailed in Subsection IV-C. In particular, usingmore advanced harvesting architecture can increase the efficiency η , allowing to achieve improved energy-fidelity tradeoffs compared to those observed here. Nonetheless, despite its relatively simple architecture,the e Sampling ADC circuit design is still shown to be able to achieve accurate reconstruction whileharvesting substantially more energy than it consumes.V. C
ONCLUSION
In this paper, we proposed the e Sampling ADC architecture, which modifies the traditional conversionprocess of a S/H ADC to harvest energy from the discarded portion of the input signal. We analyzedthe amount of energy which can be harvested from stationary signals and characterized the underlyingfundamental tradeoff between energy harvested and reconstruction fidelity which arises from the jointacquisition and energy harvesting paradigm. Our theoretic characterization reveals that an e SamplingADC with up to 12 bits can harvest more power than it consumes, when sampling both bandlimitedsignals and non-bandlimited ones at a sampling rate allowing recovery with negligible error. Then, wepresented a circuit-level design of an e Sampling ADC using CMOS 65 nm technology demonstrating thefeasibility of this concept. Our experimental results validated the theoretical observations, showing thatan e Sampling 8-bit ADC circuit applied to a sinusoidal signal harvests more power than it consumeswhile recovering the analog signal in a nearly perfect manner.26
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