Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits
aa r X i v : . [ ee ss . SP ] J a n Impact of Sampler Offset on Jitter Transfer inClock and Data Recovery Circuits
Naveen Kadayinti, Maryam Shojaei Baghini and Dinesh K. Sharma
Abstract —This paper shows how the input offset of samplingflip-flops in the Alexander phase detector affects the jittertransfer from data to the recovered clock in a clock data recoverycircuit. The Alexander phase detector samples the data at boththe edges of the clock in order to recover the data, as well as theclock timing information. The timing information is used in aclock recovery circuit, which is basically a PLL or a DLL. Oncethe PLL (or DLL) is locked, the phase detector samples the dataat the center of the eye as well as at the data transitions. It isshown how the offset of the sampling flip-flop that samples thedata at its transitions influences the jitter transfer from data tothe recovered clock. Importantly, it is shown that zero offset isnot always the best case. The effect is studied for different levelsof data dependent jitter. The mechanism of this phenomenon isexplained and the predictions are supported with simulations.The paper also discusses a tracking circuit that keeps the offsetat the minimum jitter point.
Index Terms —Data dependent jitter, clock data recovery,comparator offset, phase detectors.
I. I
NTRODUCTION
Clock data recovery circuits, which are essential in receiversof high speed serial links, have stringent jitter performancerequirements. This is due to the fact that the jitter performanceof these circuits decides the overall timing margines and BitError Rates (BER) of the systems. With increasing data ratesthe available absolute timing margines are reducing. Designersspend a lot of effort in analyzing serial links to ensure theirjitter and BER performance is satisfactory [1]. A clock datarecovery circuit comprises of a phase detector, which sensesthe phase difference between the clock and the data. The erroroutput from the phase detector is used in a negative feedbackloop through a voltage controlled oscillator (or a phase rotator)to generate the correct sampling clock. In such a phase lockedsystem, there are two main sources of jitter, one being randomjitter due to thermal noise and the second being deterministicjitter due to inter-symbol-interference (ISI) [2]. The authorsof [3] have analyzed the jitter generation mechanism andproposed techniques of compensating it via equalization. Inthis paper, we show how the offsets in the sampling flip-flopsof the phase detectors determine the jitter transfer from datato recovered clock. We show that in the presence of ISI, theminimum jitter in the recovered clock is not when the samplingflip-flops have zero offset. We analyse the system to explain
Naveen Kadayinti is with the Dept. of Electrical Engineering at IndianInstitute of Technology Dharwad, Karnataka, India. Maryam Shojaei Baghiniand Dinesh K. Sharma are with the Dept. of Electrical Engineering at IndianInstitute of Technology Bombay, Mumbai, India.(emails : [email protected], [email protected], [email protected]) why this is the case and design a circuit that recovers theoptimum sampling threshold along with the clock phase.The paper is organized as follows. Section II discusses theworking of the bang-bang phase detector in the presence ofjitter in the data. Section III discusses the working of clock anddata recovery circuits for channels with different bandwidths.A circuit for recovering optimum sampling threshold is shownin Section IV and the conclusions are presented in Section V.II. W
ORKING OF THE A LEXANDER PHASE DETECTOR INTHE PRESENCE OF JITTER IN THE DATA
One of the most commonly used phase detector for sensingthe phase difference between clock and data is the Alexanderbang-bang phase detector [4], which is shown in Fig. 1. ThePSfrag replacements
DataClock DNUPDD DD QQ QQ F F F F Fig. 1: Circuit diagram of the Alexander phase detector. bang-bang phase detector samples the data at both the transi-tions of the clock to determine the relative timing between theclock and data. The output of the phase detector is then used ina phase locked loop to generate a clock which is synchronousto the data. Fig. 2 illustrates the sampling instants of the phasedetector for different possible phase differences between theclock and the data when the data signal has no jitter.PSfrag replacements
Clock Early Clock Late Clock LockedDataClock AAA BBB CCCFig. 2: Timing diagram of sampling instants of an Alexander phasedetector under different possible phase differences between the clockand the data.
Around every data transition, if the clock arrives early,sample ‘A’ and ‘B’ resolve to the same value and ‘C’ resolvesto a different value, and the clock is delayed for correction.Similarly, if the clock arrives late, sample ‘B’ and ‘C’ resolveto the same value and ‘A’ resolves to a different value and the clock is advanced for correction. When the clock recovery loopsettles, data is sampled at its transition on the falling edge ofthe clock (samples taken at instant ‘B’ in Fig. 2). Ideally, thissample results in the flip-flop ‘ F ’ becoming metastable andresolving to ‘ ’ and ‘ ’ with equal probability to keep the looplocked. It must be noted that in order to sample the data withthe right clock edge at the center of the data eye, the phasedetector aligns the opposite edge with the data transitions.In high speed systems, the phase detector operates overdata that has high rise and fall times and, more often thannot, over data that has ISI resulting in a finite horizontal eyeopening. Fig. 3 shows a sketch of an eye diagram illustratingsuch a case. In this case, for the loop to remain locked thePSfrag replacements A B C V th Fig. 3: Sketch of a timing diagram of sampling instants of anAlexander phase detector when used at the receivers of high speeddata links. sample taken at instance ‘B’ should resolve to ‘ ’ and ‘ ’ withequal likelihood. Note that the value that sample ‘B’ resolvesto depends on the jitter in the data and the input offset ofthe sampling flip-flop ‘ F ’. Since the clock phase correctionsdepend on the value of sample ‘B’, the jitter in the recoveredclock depends on the sequence of values that ‘B’ resolves to.III. A NALYSIS OF THE EFFECT OF SAMPLER OFFSET ONDATA DEPENDENT JITTER .The jitter in the data has two main components, whichare random jitter (RJ) and data dependent jitter (DDJ). TheDDJ comes from ISI, and is generally the dominant source ofjitter [1], [2]. The amount of DDJ depends on the bandwidthof the channel through which the data is being received.To analyze the effect of jitter in the data, we use VerilogAmodel of a simple clock recovery circuit as shown in Fig. 4. Tosimulate the effect of offset of flip-flop ‘ F ’, different amountsof offset V off is added to the ‘D’ input of ‘ F ’ as shown inFig. 4. In order to simulate different amounts of DDJ, a 20section RLC network with different time constants is used.PSfrag replacements DataClock DNDN UPUPDD DD QQ QQ F F Σ VCO ChargepumpV off
RCFig. 4: Circuit schematic of a clock data recovery system.
A. Case 1: High bandwidth channel
When the channel has reasonably good bandwidth, the DDJis low and Fig. 5(a) shows the data eye diagram for such acase. The inset plot in Fig. 5(a) shows the distribution of thePSfrag replacements D a t a ( m V ) time (UI)jitter pk-pk (%UI)V off (mV) (a) Eye diagram for a high bandwidth channel. Inset plot showshistogram of zero crossing locations. Region demarcated by thered dashed box is expanded in part (b). PSfrag replacements D a t a ( m V ) time (UI) jitter pk-pk (%UI) V o ff ( m V ) (b) Zoomed view of the zero crossing region of the data isshown on the plot to the left. The plot to the right is the peakto peak jitter of the recovered clock vs offset of the samplingflip-flop ‘ F ’. Note that the plot to the right has the independentvariable (offset V off ) on the y-axis because it is aligned to thevoltage corresponding to the data on the plot to the left. Fig. 5: Eye diagram at the receiver and the corresponging jitter inthe recovered clock vs offset voltage. zero crossing time instants of the data. It can be seen thatthe jitter histogram of the data is tightly distributed arounda single peak. This data is used in the clock recovery circuitshown in Fig. 4, and simulated for different values of offsetV off . The peak-to-peak jitter of the recovered clock is plotted asa function of the offset in Fig. 5(b). It is perhaps not surprisingthat the jitter is minimum when the input offset of the flip-flop‘ F ’ is zero. B. Case 2: Moderate bandwidth channel
When the channel bandwidth reduces the ISI in the dataincreases, resulting in higher DDJ, and such a case is shownin Fig. 6(a). The inset plot in Fig. 6(a) shows the distributionof the zero crossing time instants of the data. In this case,the jitter histogram has two peaks, indicating that the ISI isdominated by 1 previous bit [3]. When this data is used inthe clock recovery circuit of Fig. 4 and simulated for differentvalues of offset V off , it is seen that the minimum jitter inthe recovered clock is not when the offset is zero. The peak-to-peak jitter of the recovered clock is plotted in Fig. 6(b) Lower bandwidth cases can be approximated in a similar way with 2 ormore bits.
PSfrag replacements D a t a ( m V ) time (UI)jitter pk-pk (%UI)V off (mV) (a) Eye diagram for a channel which results in ISI. Inset plot showshistogram of zero crossing locations. Region demarcated by the reddashed box is expanded in part (b). PSfrag replacements D a t a ( m V ) time (UI) jitter pk-pk (%UI) V o ff ( m V ) (b) Zoomed view of the zero crossing region of the data isshown on the plot to the left. The plot to the right is the peakto peak jitter of the recovered clock vs offset of the samplingflip-flop ‘ F ’. Note that the plot to the right has the independentvariable (offset V off ) on the y-axis because it is aligned to thevoltage corresponding to the data on the plot to the left. Fig. 6: Eye diagram at the receiver for a channel with ISI and thecorresponding jitter in the recovered clock vs offset voltage. for different values of V off . In this case, the jitter in therecovered clock is minimum when the offset is ≈ ± mV.The sampling threshold for minimum jitter is not the voltageat which the spread in the transition times is the smallest. Notethat the spread in the data transition times in least at 0 mV. Tounderstand why this is the case, we need to analyze the datasequences which result in corrective actions of increasing andreducing the clock frequency. Since the ISI is dominated by 1previous bit, we can construct an approximate model of strictly1-bit ISI and use it for analysis [5]. Fig. 7 shows the sketch ofan eye diagram where the ISI is limited to exactly 1 previousbit. Here b [ − , b [ − and b [0] are three most recent bits.PSfrag replacements QPR ABC b [ − b [0] b [ − b m τ τ τ τ τ X X X X Fig. 7: Sketch of an eye diagram with strictly 1-bit ISI. b [ − , b [ − ,and b [0] are samples of the data taken on consecutive rising edges ofthe clock and b m is sample of data taken on the falling edge.Nominallocations are shown. The Alexander phase detector uses samples b [ − , b m (takenon the clock ) and b [0] for detecting the phase differencebetween the data and the clock. If the data comes from anequi-probable source, the data traces X , X , X and X inFig. 7 occur with an equal probability of / each [5]. Let usnow consider a few cases for the sampling threshold of ‘ F ’. • Sampling threshold at ‘R’ and clock is between τ and τ : In this case, the Alexander phase detectorproduces an ‘UP’ signal for every trace X and X anda ‘DN’ signal for every trace X and X . Thus, the fallingedge of the clock drifts around between τ and τ . • Sampling threshold at ‘Q’:
In this case, the phasedetectors decision depends on the location of the clock. – Clock between τ and τ : Here, traces X , X and X produce a ‘DN’ signal and only X producesan ‘UP’ signal, pushing the clock towards τ . – Clock between τ and τ : Here, traces X , X and X produce a ‘UP’ signal and only X producesan ‘DN’ signal, pulling the clock towards τ .Collectively these result in the clock’s trailing edge beingkept at τ , thus minimizing the jitter.One can similarly work out any other threshold value. Thethreshold levels ‘P’ and ‘Q’ are the levels where the jitterin the recovered clock is minimum. In the next section, wediscuss the design of a circuit that automatically tracks theoffset to keep it at the minimum jitter point.IV. A UTOMATIC TRACKING OF SAMPLING THRESHOLD
In the previous section we have seen that the jitter in therecovred clock is minimum when the sampling threshold is at‘P’ or at ‘Q’. By detecting the data sequence, it is possible togenerate a circuit that adjusts the offset to bring it to a desiredlevel. In this section, we will design a circuit that tunes thesampling threshold to keep it at ‘Q’.In order to adjust the sampling threshold and bring it to‘Q’, we need to identify the 4 traces X through X and thesampling threshold. This can easily be done by looking at thethree most recent bits received at the receiver, which are b [ − , b [ − and b [0] . The Alexander phase detector also samples thedata at the falling edge of the clock. let this bit be b m . Thissequence of 4 bits b [ − b [ − b m b [0] can be used to identifythe location of the sampling threshold. This is tabulated inTable I, wherein the threshold location and the action to betaken so as to bring the sampling threshold to ‘Q’ are alsotabulated. From Table I, we can find the logic condition fordetecting when the sampling threshold should be increasedand when it should be decreased. The expressions areUP V th = b [ − · b m · ( b [ − ⊕ b [0]) DN V th = b [ − · b m · ( b [ − ⊕ b [0]) The logic circuit implementation of above expressions isshown in Fig. 8. The parts drawn in gray in Fig. 8 form theAlexander phase detector.This circuit, which senses the phase error as well as thethreshold error, is used in a clock clock data recovery circuitas shown in Fig. 9. This circuit was simulated to verify
TABLE I: Possible sequences and threshold locations for data with1 bit ISI (refer Fig. 7) b [ − b [ − b m b [0] Thresholdregion Action0 0 0 0 X NA th > Q V th ↓ X NA th < Q V th ↑ th > P OR > Q V th ↓ X NA th < Q OR < P V th ↑ X NA X NA th > P OR > Q *1 0 1 0 X NA th < Q OR < P *1 1 0 0 V th > P *1 1 0 1 X NA th < P NA X NA NA : No action. X : No decision possible.*Decision possible, but not used in this implementation. PSfrag replacements UP V th DN V th DNUP ck ckckckckData D DDD D Q Q QQQ Σ Fig. 8: Circuit for detecting whether the sampling threshold should beincreased or decreased for reducing the jitter in the recovered clock.Part drawn in gray is the Alexander phase detector. its working for clock recovery and for sampling thresholdrecovery with data coming from a channel discussed in
Case 2 in Section III-B. Fig. 10 shows the time evolution of the VCOcontrol voltage and sampling threshold V fbth . As expected V fbth settles to ≈ − mV, which corresponds to ‘Q’.It can be shown that the same logic circuit recovers theoptimum sampling threshold even for high bandwidth channelsdiscussed in Case 1 in Section III-A. It may be noted that thisanalysis and the results can also be used to design low jitterclock recovery circuits for PAM4 signals. PSfrag replacements D D DNDN DNUPUP UPUP V th DN V th ClockData Σ PhasedetectorfromFig. 8 V fbth
ChargeChargepumppump
VCO
RR CCV c Fig. 9: Clock data recovery circuit that recovers sampling clock aswell as optimum sampling threshold.
PSfrag replacements V c ( m V ) V f b t h ( m V ) time ( µ s)Fig. 10: Time evolution of control voltage (V c ) for VCO and that ofsampling threshold (V fbth ). V. C
ONCLUSIONS
We have shown that input offset of the sampling flip-flops in the Alexander phase detector can influence the jitterin the recovered clock. We have shown that the effect ofsampler offset on the recovered clock jitter also depends onthe amount of ISI present in the data input. Using the factthat immediate previous bits are the highest contributors toISI, we have constructed an approximate model assuming 1-bit ISI. Using this model we have explained the dependence ofrecovered clock jitter on input offset and also used this analysisto construct a circuit that recovers the optimum samplingthreshold. The circuits are verified using simulations.R
IEEE Trans. Circuits Syst. I (TCAS-I) , vol. 51, no. 9, pp. 453–457,Sept 2004. [3] J. F. Buckwalter and A. Hajimiri, “Analysis and equalization of data-dependent jitter,”
IEEE J. Solid-State Circuits (JSSC) , vol. 41, no. 3, pp.607–620, March 2006.[4] J.D.H. Alexander, “Clock recovery from random binary signals,”
Elec-tronics Letters , vol. 11, no. 22, pp. 541–542, October 1975.[5] Naveen Kadayinti, Amitalok J. Budkuley, Maryam S. Baghini, andDinesh K. Sharma, “Effect of jitter on the settling time of mesochronousclock retiming circuits,”