Implications of Burn-In Stress on NBTI Degradation
Mohd Azman Abdul Latif, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Mark Zwolinski
IImplications of Burn-In Stress on NBTI Degradation
Mohd Azman Abdul Latif, Noohul Basheer Zain Ali,Fawnizu Azmadi Hussin, and Mark Zwolinski
Abstract
Burn-in is accepted as a way to evaluate ageing effects in an accelerated manner. It hasbeen suggested that burn-in stress may have a significant effect on the Negative Bias Tempera-ture Instability (NBTI) of subthreshold CMOS circuits. This paper analyses the effect of burn-inon NBTI in the context of a Digital to Analogue Converter (DAC) circuit. Analogue circuits re-quire matched device pairs; NBTI may cause mismatches and hence circuit failure. The NBTIdegradation observed in the simulation analysis indicates that under severe stress conditions, asignificant voltage threshold mismatch in the DAC beyond the design specification of 2 mV limitcan result. Experimental results confirm the sensitivity of the DAC circuit design to NBTI resultingfrom burn-in.
In the competitive environment of semiconductor manufacturing, accurate reliability prediction resultsin significant time-to-market and profitability improvements. Prediction quality depends on the man-ufacturer’s ability to characterize process-related instabilities and defects in a given design. Burn-instresses are commonly performed on products to accelerate the fabrication process failure mecha-nism and to screen out design flaws.At sub-micron process technology nodes, it has been suggested that burn-in stress is likely toaffect the Negative Bias Temperature Instability (NBTI) [1], which in turn will affect the operationalperformance of circuits.The objective of the work described in this paper is to evaluate the effect of burn-in stress onNBTI, with reference to the performance effect on analogue circuits. A Digital-to-Analogue Converter(DAC) module was selected as a case study. With device reliability models and circuit simulation, this1 a r X i v : . [ c s . OH ] O c t aper analyses the effect of burn-in stress on the shift of key DAC parameters such as the IntegralNon-Linearity (INL), Differential Non-Linearity (DNL) and gain error. Since the advent of 90nm CMOS technology, NBTI has become one of the top circuit reliability issuesfor both PMOS and NMOS devices, because it can severely impact product performance over time.Compared with previous process generations, NMOS hot electron degradation is no longer of suchconcern. At 45nm, Positive Bias Temperature Instability (PBTI) has an effect on NMOS devices thatis about half of that of NBTI on PMOS devices [2].Several studies have reported on the impact of NBTI on the performance of analogue and digitalcomponents. It was shown by Kang et al [3] that the degradation in maximum circuit delay closelyfollows the trend of threshold-voltage ( V t ) degradation in a single PMOS transistor. Their finding wasbased on a detailed analysis of circuit performance with respect to NBTI degradation, particularlyfocusing on the maximum delay degradation of random-logic circuits. Kumar et al [4] confirmedthe effect of NBTI degradation under AC conditions. In addition, Kufluoglu et al [5] addressed bothPMOS-level measurement delay effects and real-time degradation and recovery by simulation. Astudy performed by Bhardwaj et al [6] revealed that circuit-level NBTI models can be further improvedby considering various process technology-dependent parameters which lead to process variationeffects.Ball et al [7] have explored the burn-in implications for SRAM circuits. Their approach has demon-strated that the minimum operating voltage, V cc min , increases during burn-in as a result of NBTI andis of the order of the NBTI-induced V t shift. Schroder and Babcock [1] have thoroughly studied the Time To Failure (
T T F ) relationship to voltageand temperature effects. From their analysis,
T T F is affected as follows: • when the burn-in stress voltage, V stress increases, T T F decreases; • when the difference between the nominal voltage, V cc , and V t increases, T T F decreases; and2
T T F is inversely proportional to Temperature.The worst case situation is when the system is operated at a high voltage most of the time.However, NBTI degradation can also affect the minimum operating voltage,
V cc min , as noted above.NBTI degradation is less sensitive to
V cc than is NMOS Hot Carrier (NHC) degradation. However,it is more sensitive to temperature [8] and occurs even when the transistor is not switching, as longas it is in inversion.The following equation shows how the threshold voltage shift of a PMOS transistor, as a functionof the applied voltage and temperature, affects the
T T F [9].
T T F ( s ) = M T T F ∗ f ( V tp , L ) ∗ A (1) A = exp ( − γ ∗ E ) ∗ B (2) B = exp (cid:32) E a k ∗ (cid:34) T j + 273 − (cid:35) ∗ C (cid:33) (3) C = (cid:20) ∆ V tp F C (cid:21) β (4)where • T T F ( s ) is the scaled time to failure in seconds due to voltage and temperature scaling depen-dencies; • M T T F is the mean time to failure at the selected fail criterion (FC); • f ( V tp , L ) is the geometry scaling function for ageing; • γ is the electric field acceleration factor; • E is the electric field ( V /T ox ) across the gate oxide, of thickness T ox ; • T j is the junction temperature; • E a is the thermal activation energy; • F C is the V t shift, defined as the failure criterion for modelling; • β is a process-dependent variable. 3his effect can be simulated by applying a signal to the circuit of interest and summing the degra-dation from each time step. In this case, the effect of the shift in V t , the threshold voltage, for a timevarying waveform, can be calculated by using the quasi-static time integral with time in equation (5). T T F = 1 t (cid:48) ∗ (cid:82) dtT T F ( t ) = 1 Avg (1 /T T F ( t )) (5)Lee et al demonstrated the NBTI effect on product reliability degradation [10]. In addition, theirsimulator includes other reliability mechanisms such as hot carrier injection (HCI) and time-domain-dielectric-breakdown (TDDB) [10]. The simulation demonstrates the validity of using a TDDB degra-dation model to predict the failure rate of a complicated microprocessor. The model is derived usinglarge discrete capacitor/device TDDB data with various temperature, voltage and geometry consid-erations.It is noted that even though NBTI degradation occurs under elevated voltage and temperature,the NBTI phenomena show some relaxation. This occurs due to passivation of NBTI-induced silicondangling bonds by the hydrogen which has diffused from the gate oxide to the interface [5]. Thereare two types of relaxation that need to be seriously considered for circuit reliability modelling.1. Fast relaxation: This relaxation occurs as soon as the stress is removed. It is responsiblefor reduced AC degradation even after accounting for the transistor ‘ON’ time. However, thisrelaxation mode is not covered in our reliability simulations.2. Extended relaxation: This relaxation occurs as the device is kept unbiased. Our reliabilityanalysis accounts for this relaxation mode.Figure 1 illustrates the two relaxation modes. Because relaxation lessens the effects of NBTI, a deviceunder continuous usage may suffer a higher degradation than the reliability simulation predicts. We approximate a complex integrated circuit with a series failure model. We also assume eachfailure mechanism has an exponential lifetime distribution. In this way, the failure rate of each failuremechanism is treated as a constant. With these two assumptions, the reliability simulation models,which are often used to extrapolate failure rates, can be validated based on available data.4 egradation Recovery RecoveryDegradationFast DegradationVt/Id shift
Figure 1: NBTI periodic stress and relaxation
For this work, Intel’s internal tool, RELSIM (Reliability Simulation), is used to predict changes indevice and circuit performance over a product’s lifetime. It further allows simulation of post-degradedcircuits to ensure circuit designs meet reliability requirements at end-of-life (EOL) [11]. The reliabilitysimulation methodology used in this paper is shown in Figure 2. The simulation has two modes ofoperation. The first mode, the Stress Mode, calculates the transistor V t shift. The second mode,the Playback Mode, simulates degraded circuit performance based on Stress Mode results. Thesimulation is conducted to cover elevated ranges of Process, Voltage and Temperature (PVT).The DAC reliability simulation is run in a 3-step process in the design environment.1. Simulate the non-degraded behaviour at the typical circuit operating condition ( V cc and tem-perature).2. In Stress Mode, calculate the amount of degradation on each transistor. This is done at aslightly higher voltage and temperature to get a more conservative estimate of the degradation.3. In Playback Mode, simulate the degraded circuit, using the degradation calculated in the StressMode. 5 ime - days V o l t age Time - days V o l t age Time - years V o l t age Time - years V o l t age Stress Mode1) Burn In 2) Normal OperationStress file 1 Stress file 2Playback ModeStress file 1 + Stress file 2
Figure 2: Reliability Simulation flow6he Stress Mode is used to report the degradation of a circuit at future times chosen by theuser. The user provides the ageing time, the ageing method (e.g. none, fixed, uniform, bias andtemperature user parameters) and a reference degradation value. Also necessary is a degradationparameter file that contains parameters for MOS device stress calculations. During the stress simu-lation, a stress file is generated at each specified future time. The stress file contains the stressed(degraded) values of each MOS device in the circuit. The degraded circuit values from the initialstress mode can be subsequently used in playback mode. The playback mode produces outputsignal waveforms for an aged circuit. The information from a stress file is read and a perturbationfunction is applied to the MOS depending on the degradation model chosen in the stress mode.The reliability simulator has been used for transistor ageing modelling across major process tech-nologies from 250nm down to 14nm [12]. The models have been extensively calibrated against actualsilicon test chip data to ensure accuracy [12]. The simulator can be used to model the minimum
V cc ( V cc min ) degradation effects. It is able to find the worst case corners, and takes voltages on all nodesinto account. The AC NBTI modelling capability provides more accurate reliability performance pre-dictions than static DC worst-case models. Furthermore, it can be calibrated with the AC circuits toinclude NBTI recovery, similar to that in [5].Another key advantage of this reliability simulator is that the PMOS degradation is modelled withthreshold voltage shifts based on non-uniform I-V degradation. The simulator models the effect onthe MOS transistors I-V characteristics and the effect on the device parameters and applied voltages.Under the PMOS degradation model, it is suitable for both digital and analogue simulations.
For this case study a video DAC has been used. The performance of the DAC is critical for achievingexcellent video quality. The required accuracy of the DAC is based on the differential gain and phasedistortion specifications for TV [13]. The DAC is designed as a current steering architecture to achievehigh accuracy and low distortion of the analogue video signal. The signal range is between zerovolts to the maximum nominal analogue video signal swing of 1.3V. The digital input to each DACis latched on the rising edge of each clock and is converted to an analogue current. For a givendigital input, the current source outputs are summed together and directed to the output pin by thedifferential current switches. An analogue video voltage is created from the DAC output current7
RT DAC
VCCA = 3.3V R Load = 37.5 V out : 0V to 0.7V VCCA/2
Bias1 M1 M4M2M3
Package Ball
VCCA
Bias2
Switch Driver
All Transistors are Thick Gate PMOS
Current SourceDifferential Switch
Vout
CRT DAC
VCCA = 3.3V R Load = 37.5 V out : 0V to 0.7V VCCA/2
Bias1 M1 M4M2M3
Package Ball
VCCA
Bias2
Switch Driver
VCCA = 3.3V R Load = 37.5 R Load = 37.5 R Load = 37.5 V out : 0V to 0.7V VCCA/2
Bias1 M1 M4M2M3
Package Ball
VCCA
Bias2
Switch Driver
Current SourceDifferential Switch
Vout
Figure 3: Circuit diagram of the current source/differential switch for the CRT DACflowing into the termination resistors. To determine the required output current of the DAC circuit,the video level specifications for the various video formats along with the effective load terminationare measured. The LSB output voltage, which ranges between 684 µ V and 1.27 mV, is a function ofthe supported video format. Given the circuit mismatch sensitivity of this circuit, paired devices aredesigned accordingly; typically with greater lengths.The DAC is composed of parallel current switches. This so-called CRT DAC is widely used in highspeed applications specifically for its speed and linearity. The circuit is referenced to an analoguepower supply which consists of an array of PMOS current sources and differential current switches(Figure 3).This DAC operates at 3.3V nominal voltage and implemented in 90nm process technology. It hasbeen shown that the 90nm CRT DAC has sufficient headroom in terms of the circuit performancedegradation throughout a 7-year lifetime.The V t degradation is calculated by scaling the gate voltages to the typical analogue operating8oltages. The extrapolation is given by equation (6) [9]. ∆ V t = A ∗ exp ( β ∗ V gs ) ∗ exp (cid:18) E a KT (cid:19) ∗ t n (6)where: • A is the process related pre-factor; • V t is the threshold voltage; • E a is the activation energy in eV ( E a = 0.145 eV was chosen by experiment) • β is the transconductance parameter ( β = 0.75 was chosen by experiment); • V gs is the gate to source voltage; • K is the Boltzmann Constant; • T is the temperature in Kelvin; • t is the time in years; and • n is the voltage acceleration and exponent factor ( n = 0.181 was chosen by experiment). For our case study, NBTI analysis was performed on the DAC circuit shown in Figure 4. We simulatedthe NBTI behaviour of the DAC under normal and extreme conditions.The reliability simulation playback mode analysis was done under the typical corners, for pre-layout schematics with proper loading. For this analysis, the circuit was aged for a 7-year lifetime tocheck the DAC circuit functionality and the effect of NBTI degradation under burn-in conditions. Table1 shows a comparison between three different conditions.We analysed the matched devices in Figure 4 and observed slightly different degradation be-haviours. There are two key device parameters that are critical to degradation behaviours.1. Drain current, I d : The current reaches its maximum value and maintains that value for higherdrain-to-source voltages. A depletion layer located at the drain end of the gate accommodates9 SSA
MBIAS1
VSSA
MBIAS1
Rset = 1300 , 0.5%for 37.5 D/A Load
MBIAS2 TGVDNMOSOr TGNMOS
Rset = 1300 , 0.5%for 37.5 D/A Load
MBIAS2 TGVDNMOSOr TGNMOS
VCCA=3.3V
Master Reference CRT D/A Biasing (for 3 Channels)
BandgapVoltageReference +- ~ 0.762V~ 1.21V VCCA BIAS1BIAS2
1 : 1
I ~ 586 A I ~ 586 A CRTIREF8LSB (CRT)
VSSA fdbk BIASM
LevelShifter (3.3V)
V1BIASC~0.7VVCCA=3.3V
Master Reference CRT D/A Biasing (for 3 Channels)
BandgapVoltageReferenceBandgapVoltageReference +- ~ 0.762V~ 1.21V VCCA BIAS1BIAS2
1 : 1
I ~ 586 A I ~ 586 A CRTIREF8LSB (CRT)
VSSA fdbk BIASM
LevelShifter (3.3V)
V1BIASC~0.7V
Figure 4: Simplified circuit diagram of 8-bit CRT DACthe additional drain-to-source voltage. This behaviour is referred to as drain current saturation, I dsat . Drain current saturation therefore occurs when the drain-to-source voltage equals thegate-to-source voltage minus the threshold voltage.2. Threshold voltage, V t : A group of transistors has a Gaussian profile about a mean. Experi-mentally, it has been shown that the difference in threshold voltages between 2 identically sizedtransistors behaves as described in equation 7 [1]. σ ∆ = A V t √ W L (7)where A V t is a technology conversion constant (in mV µ m), and WL denotes the product of thetransistor’s active area.From the simulation results, it is observed that the I dsat and the V t degradations of both the10able 1: Reliability simulation parameters across three different conditionsParameters Fresh Burn In (Stressing Mode) Age (Playback Mode)Stress Skew Typical Corner Typical Corner Typical CornerStress Voltage 3.3V 4.6V 3.3VTemperature 100 ◦ C 110 ◦ C 110 ◦ CUse time Time 0 168 hrs 7 yearsTable 2: Reliability Simulation result comparing current source/differential pairs at 3.3V and 4.6VReliability Simulation - Burn In mode @ 3.3V (V nominal)Transistor Pair idsat (%) Vt mismatch (mV)M1 Current Source 2.157 0.902M2 Current Source 2.157 0.902M3 Differential 2.047 0.731M4 Differential 2.047 0.731Reliability Simulation - Burn In mode @ 4.6V (1.4X V nominal)Transistor Pair idsat (%) Vt mismatch (mV)M1 Current Source 1.905 5.239M2 Current Source 1.905 5.239M3 Differential 2.039 2.059M4 Differential 2.039 2.059matched devices M1 and M2 pairs and the differential switch M3 and M4 pairs at 3.3V nominalcondition of VCCA were comparable. The I dsat degradation at 3.3V for all transistors seems greaterthan that of the 4.6V burn-in. However, the delta of 3.3V and 4.6V is not enough to conclude thatdegradation happens even at 3.3V nominal. On the other hand, the V t degradation shows a significantdifference at the two voltage readings. At the 4.6V burn-in condition, the degradation of the matcheddevices in both M1 and M2 pairs gives a V t mismatch of 5.2 mV, compared with the DAC specificationof 2 mV, as shown in Table 2. These two current source pairs have a higher V t mismatch comparedto the differential pairs. This mismatch may cause the DAC to malfunction.For simulation purposes, the DAC performance data in Table 3 was simulated at 3.3V nominal aswell as at 4.6V at elevated voltage. The performance data focused on the critical parameters:1. Differential Non-Linearity (DNL)2. Integral Non-Linearity (INL)3. Gain Error4. Offset Error5. Output Current 11able 3: Simulation data of DAC parameters at 3.3V and 4.6VDAC Parameters Spec Sim For the burn-in experiment, the voltage supply of interest, the analogue CRT DAC power supply,VCCA, was elevated to a burn-in voltage of 4.6V. The nominal voltage for this power supply is 3.3V.Three hundred units from three fabrication lots were analysed.These units were subjected to burn-in stress for 30 minutes followed by post burn-in checkpoint(PBIC). All units completed a cumulative 168-hour burn-in. Of 300 experimental units, 30 good unitswere sampled for specific DAC burn-in characterization. From these 30 samples, 1 unit from eachof the three fabrication lots was marked as the control unit. These control units were tested firstand used for reference, while the rest of the units were tested after each of the burn-in phases at atemperature of 115 ◦ C.ATE testers were used to take a series of electrical measurements (timing and parametric shift) atdifferent phases: pre-burn-in, time zero, and follow-on (0.5 hours, 12 hours, and 168 hours burn-in).The same five critical performance parameters as in the simulation were measured. Two sets of datawere collected: at the nominal voltage of 3.3V; and at the elevated burn-in voltage of 4.6V.
We present in Figure 5 experimental data from stressing discrete transistors that illustrates the in-crease in V t with respect to the NBTI stress time. The graph was plotted by applying the power lawin equation (8). 12 = 5.1474x y = 2.4726x V t s h i ft ( % d e l t a ) Stress time (hr)
DAC Burn In data %Vt(4.6V, 95'C)%Vt(3.3V, 95'C)
Figure 5: DAC Burn In comparison: 3.3V (nominal) vs 4.6V (stress) supply voltage with respect tostress time ∆ V t = A ∗ t n (8)Figure 5 compares the results from time zero at 3.3V with those at 4.6V elevated voltage withrespect to the stress time. It is apparent that NBTI has a power-law time dependence. When plottedon a log-log scale, we see that a higher voltage difference between gate and source will result in ahigher degradation. This shows that ∆ V t has a power-law dependence with respect to time. As aresult, the curve for the 4.6V stress (black) after burn-in is shifted upwards compared to the curve inblue at 3.3V, which represents the time zero stress.The slope of this line is called the ‘power-law slope’, n . It is technology dependent and typicallyranges in value from 0.15 to 0.30 [1]. The low value of n (n <
1) gives rise to the ‘quasi-saturating’behaviour. It is important to note that NBTI degradation has been shown to follow a power law timedependence due to the physics of the electrochemical reaction/diffusion reaction underlying NBTI13able 4: The Vout data taken before and after Burn-In stressInput code Vout @ pre Burn-In Vout @ post Burn-In0 0.000 0.0001 0.167 0.2392 0.333 0.4783 0.500 0.7174 0.667 0.9565 0.833 1.1956 1.000 1.4347 1.167 1.6738 1.333 1.9129 1.500 2.15110 1.667 2.39011 1.833 2.62912 2.000 2.86813 2.167 3.10714 2.333 3.34615 2.500 3.585degradation [1]. Therefore, the functional form is not merely a curve-fitting exercise but rather anecessary consequence of the degradation physics.We measured the same five key DAC parameters as in the simulation. These measurementswere taken after the last burn-in readout of 168-hours under a severe stress condition at 4.6V. A168 hour burn-in at 95% is equivalent to 7 years of normal operating condition, as in the reliabilitysimulation. The key test results measured before and after burn-In stress are summarized in Table 5.The changes in the parameters after the burn-in are comparable to those resulting from the reliabilitysimulation, Table 3. We can therefore be reasonably confident that the ageing simulation and theemulation of ageing through burn-in are consistent. In other words, we have a strong correlation, butwe cannot prove causality.Based on the test results measured, the gain error measurement after the post burn-in stresswas the only parameter that has a significant spike as compared to the rest of the key parameters.A significant increase in the gain error of 43.5 % was observed. The ideal situation is that the DAC’sgain error has to be zero. The gain measurement was collected on the ATE tester. The pre burn-inis assumed to be an ideal case with zero gain error. Table 4 shows that as the DAC input codeincreases, the output voltage increases accordingly to 2.5V (V ref ).The post burn-in Vout was measured at the ATE tester and the Vout values increased by ∼ % compared to the typical gain error percentage of less than ∼ % . The gain was calculated as A v =14 AC OUTPUT vs CODE
DAC CODE V O U T Vout @ pre Burn-InVout @ post Burn-In
Gain Error = ~43.5%
Figure 6: DAC characteristic showing an excessive gain error of 43.5 % ≈ ≈ % . Figure 6 shows the DACtransfer functions of ideal (pre burn-in) vs actual DAC (post burn-in).In this specific case, the gain error has created a span greater than the desired ideal case. Thetransfer function is modelled as a typical straight line as commonly described by y = mx + c equation,where: • y is the output of the DAC • m is the slope of the transfer function • x is the input of the DAC • c is the offset voltage 15able 5: Summary of 168 hours Burn-In experiment of DACItems Pre Burn-In Post Burn-In Percent ChangeDNL mean 0.185 LSB 0.197 LSB 6.48%INL mean 0.235 LSB 0.246 LSB 4.68%Gain Error 2.500V 3.585V 43.50%Offset Error 0.000344V 0.000361V 4.90%Output Current 5.9 mA 6.02 mA 2%Typically, an ideal DAC has a gain, m , of 1 and an offset, c , of 0 and hence the output tracks theinput in a precise linear manner. However, for the real DAC, it has non-ideal gain and offset valueswhich normally can be compensated once the values are determined.For the data taken in this burn-in experiment, the design is based on an 8-bit DAC with a 0V to2.5V nominal output span. When the digital input is set to a full scale, a 3.585V output is measured.From this data, the actual gain error, measured in percentage, can be determined by multiplyingthe output voltage at post burn-in by the output voltage at pre burn-in, 3.585V/2.5V = ≈ % . In other words, the standardreliability simulation tool correctly predicts changes in key DAC parameters, including the effect ofNBTI, but appears to underestimate the change in the gain error. It is well-known that mismatchbetween current mirror paired devices will cause such gain errors [14]. Therefore, it is reasonableto conclude that the increase in gain error after burn-in has resulted from transistor pairs becomingmismatched, and such a mismatch is likely to be due to changes in the threshold voltages. As hasbeen shown, above, NBTI causes significant changes in V t . Therefore it is again reasonable toconclude that the change in gain error, as a result of burn-in, has been caused by NBTI. The NBTI degradation observed in the reliability simulation of a DAC circuit revealed that under asevere stress condition such as a 40% increase in the nominal voltage supply, a significant voltagethreshold mismatch, beyond the 2 mV limit, was recorded. A burn-in experiment on the DAC circuitwas performed to verify the simulation. A correlation between the simulation results and the burn-inbehaviour was observed, but the change in the gain error was significantly greater than predicted.16 eferences [1] D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: Road to cross in deepsubmicron silicon semiconductor manufacturing,”
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