aa r X i v : . [ qu a n t - ph ] J un Improved Quantum Ternary Arithmetics
Alex Bocharov a Quantum Architectures and Computations Group, Microsoft ResearchRedmond, Washington, 98052, USA
Shawn X. Cui b University of CaliforniaSanta Barbara, California, 93106, USA
Martin Roetteler c Quantum Architectures and Computations Group, Microsoft ResearchRedmond, Washington, 98052, USA
Krysta M. Svore d Quantum Architectures and Computations Group, Microsoft ResearchRedmond, Washington, 98052, USA
Qutrit (or ternary) structures arise naturally in many quantum systems, notably in certain non-abeliananyon systems. We present e ffi cient circuits for ternary reversible and quantum arithmetics. Our mainresult is the derivation of circuits for two families of ternary quantum adders. The main distinction fromthe binary adders is a richer ternary carry which leads potentially to higher resource counts in universalternary bases. Our ternary ripple adder circuit has a circuit depth of O ( n ) and uses only 1 ancilla,making it more e ffi cient in both, circuit depth and width, when compared with previous constructions.Our ternary carry lookahead circuit has a circuit depth of only O (log n ), while using O ( n ) ancillas.Our approach works on two levels of abstraction: at the first level, descriptions of arithmetic circuitsare given in terms of gates sequences that use various types of non-Cli ff ord reflections. At the secondlevel, we break down these reflections further by deriving them either from the two-qutrit Cli ff ord gatesand the non-Cli ff ord gate C ( X ) : | i , j i 7→ | i , j + δ i , mod 3 i or from the two-qutrit Cli ff ord gates andthe non-Cli ff ord gate P = diag( e − π i / , , e π i / ). The two choices of elementary gate sets correspondto two possible mappings onto two di ff erent prospective quantum computing architectures which wecall the metaplectic and the supermetaplectic basis, respectively. Finally, we develop a method tofactor diagonal unitaries using multi-variate polynomials over the ternary finite field which allows tocharacterize classes of gates that can be implemented exactly over the supermetaplectic basis. Keywords : Quantum circuits, ternary quantum systems, quantum adders a [email protected] b [email protected] c [email protected] d [email protected] 1 Improved Quantum Ternary Arithmetics
Quantum computation has seen vast progress over the years, both theoretically and experimentally.Computations on a programmable and scalable fault-tolerant quantum computer will consist of fullycontrolled sequences of primitive operations such as unitary gates, measurements and state prepara-tions. Such sequences are called quantum circuits . In the most commonly used circuit model, quantuminformation is stored in a collection of qubits , where each qubit has a two-dimensional Hilbert statespace with the computational basis {| i , | i} . A standard universal gate set consists of Cli ff ord gatesand one non-Cli ff ord gate such as the π -gate [1] or V -gate [2]. By design, circuits over a universal setcan be used to approximate arbitrary quantum gates. Thus any quantum algorithm can be processedgiven a quantum computer with a universal gate set.It has been noted by several researchers that architecture of certain quantum registers and gatesis more naturally described by multi-valued logic as opposed to binary logic. History of experimentswith ternary superconducting registers, in particular goes back to 1989 [3],[4]. More recently, inquantum computation domain, multi-valued logic has been proposed for linear ion traps [5], coldatoms [6], entangled photons [7]. It remains to be seen, at what scale it would be possible to balanceout quantum universality and fault-tolerance in these and other similar architectures.The research presented here is motivated in part by recent progress in circuit synthesis over uni-versal quantum bases arising in topological quantum computing, where multi-qubit encoding is notnecessarily the most natural choice. Several physical systems capable of performing topologically-protected quantum computations have a natural structure of a qutrit instead of a qubit, where a qutrithas a three-dimensional Hilbert space with the computational basis {| i , | i , | i} . For instance, in theSU(2) anyon system, anyons with quantum dimension √ anyon system can be made univer-sal through braiding and projective measurement of anyons. This anyonic structure is quite far fromphysical realization at the moment, yet, it o ff ers a promise of comparatively simple quantum uni-versality combined with native topological protection, which, in our opinion, makes it a worthwhilesubject of forward-looking research.In [9], an algorithm is given for approximation of any multi-qutrit gate with an asymptoticallyoptimal circuit over the gate set Cli ff ord + diag(1 , , − Householder reflections for synthesis of e ffi cient circuits. Even though the gate set turned out tobe powerful enough for such synthesis, it had certain conceptual and practical limitations. Thus, itis quite unlikely that all the reversible classical permutation gates can be implemented exactly overCli ff ord + diag(1 , , − ff ect on implementation of arithmetic-heavy algorithmssuch as Shor’s Factorization Algorithm, since the integer modular arithmetic is naturally described byreversible classical circuits. As a matter of principle such circuits may be represented exactly incommonly used multi-qubit circuit models. e When compared to [9], the present paper aims at a more abstract level. Here we assume thatthe entire group of multi-qutrit classical permutations is representable at some cost, explore di ff erentscenarios of its representation and focus on synthesizing e ffi cient circuits for ternary base arithmeticin these scenarios. Our thinking at this level remains reflection-centric. Previous research on non-binary reversible circuits [11] mostly focused on proving the universality of the local classical Cli ff ordgates in combination with the controlled-increment gate | j , k i 7→ | j , k + δ j , d − mod d i , where d is thedimension of the qudit and δ is the Kronecker delta. Reversible circuits available in literature tend to e To the extent the three-qubit To ff oli gate may be assumed exactly representable. . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore use ancillary qudits fairly liberally.This paper di ff erentiates itself from previous work in two ways. First, we explore several alternatemethods for synthesizing classical reversible circuits. Second, we strive to minimize both the depthand the width of arithmetic circuits specifically. For example, we show in Section 3.1 that implement-ing of a faithful CARRY gate is not necessary in a correct ternary adder. By using a modified carrywe eliminate the use of ancillary qutrits and reduce the cost of the gate when compared to a faithfulCARRY as used in previous approaches to implement ternary carry ripple adders [12, 13, 14].Our focus is mainly on two types of ternary quantum adders, a modified ripple-carry adder and acarry look-ahead adder. Both adders are generalized from their binary counterparts, but the general-izations are somewhat non-trivial. To add two n -qutrit numbers, the modified ripple-carry adder uses1 ancilla and has a circuit depth of O ( n ), while the carry look-ahead adder requires O ( n ) ancillas andhas a circuit depth of O (log n ). Each of the two adders has an overall circuit size of O ( n ) elementarygates. We also study various extensions of quantum adders including adder modulo 3 n , comparison,and subtraction.We show these arithmetic circuits can be realized exactly using classical Cli ff ord gates and oneadditional gate C ( X ), the controlled-increment gate, whose matrix is given in Equation 1. C ( X ) isa two-qutrit non-Cli ff ord gate and it is universal for reversible classical computation. This sets theternary reversible circuits apart from their binary analogs, where at least one three-qubit gate, e.g., theTo ff oli gate, is required for universality. C ( X ) = (1)We also introduce a qutrit universal gate set Cli ff ord + diag( e − π i , , e π i ), called the supermeta-plectic basis, which resembles the single-qubit π -gate. Some techniques are developed to constructnew quantum gates from old ones. As an application, it will be shown that all ternary arithmeticstudied in this paper can be implemented exactly over the supermetaplectic basis.We note that the reflection-centric synthesis of our adder circuits is a ternary counterpart of To ff oli-centric binary adder circuits as developed, for example, in [17] and [18]. This analogy is explained inmore detail in corresponding sections throughout the paper. The exact representation of the C ( X ) gatein supermetaplectic basis parallels the exact representation of the three-qubit To ff oli in the Cli ff ord + π basis. Quantitative comparison of the ternary and binary adders would be beyond the scope ofthis work. A major step towards comprehensive comparison of this kind was made in the upcomingpaper [10] that demonstrates the advantages of emulating Shor’s period funding function on ternaryquantum computer and especially on the metaplectic topological quantum framework.The paper is organized as follows. In Section 2, some preliminaries and notations used throughoutthe paper are given. In Section 3, we separately discuss the modified ripple-carry adder and carrylook-ahead adder. Section 4 gives some extensions of quantum adders, including addition modulo 3 n , Improved Quantum Ternary Arithmetics comparison, and subtraction. Lastly in Section 5, we introduce the supermetaplectic basis and developtechniques for the construction of new gates.
We denote the standard computational basis in a qutrit by {| i , | i , | i} . The terminology “qutrit”and “ternary” are sometimes used interchangeably. We call a quantum gate reversible or a classical permutation gate if it acts as some permutation of the standard basis elements. Unless otherwisenoted, the arithmetic, e.g., addition, multiplication, etc., within a ket is assumed to be taken modulo3. Also by default circuits are read from left to right, while compositions of gates when written asexpressions follow the rule of matrix multiplications, i.e., they are read from right to left. Throughoutthe paper, the following ternary quantum gates are frequently used:1. X = , namely, X | i i = | i + i .2. S , = , namely, S , swaps | i with | i and fixes | i . Similarly, one can define S , , S , . This notation is also generalized to multi-qutrit gates. For instance, S , is a 2-qutrit gate, which swaps | i with | i , and fixes all other basis elements.3. Given an n -qutrit gate U , there are two versions of “controlled- U ”. The first version is called“soft-controlled- U ,” denoted by V ( U ), and is defined as the ( n + | i , j , · · · j n i 7→ ( I ⊗ U i ) | i , j , · · · j n i , where the first qutrit is called the control qutrit. The second version isthe “hard-controlled-U” denoted by C c ( U ), where c ∈ { , , } . The gate C c ( U ) is also an( n + U , it maps | i , j , · · · j n i to ( I ⊗ U δ i , c ) | i , j , · · · j n i . It is direct to see that the C c ( U ) ′ s for di ff erent c ′ s are equivalent to eachother up to some 1-qutrit reversible gates. Thus we also use C ( U ) to denote a general C c ( U ).Moreover, the equality V ( U ) = C ( U )( C ( U )) holds.4. The following is a list of some important controlled gates: • SUM = V ( X ) : | i , j i 7→ | i , i + j i , • C ( X ) = C c ( X ) : | i , j i 7→ | i , j + δ i , c i , • Horner = V ( V ( X )) : | i , j , k i 7→ | i , j , i j + k i , • C ( SUM ) = C c ( SUM ) : | i , j , k i 7→ | i , j , j δ i , c + k i .The Horner gate is a qutrit generalization of the qubit To ff oli gate. See also [15] for additionalbackground on the Horner gate.5. SWAP : | i , j i 7→ | j , i i .For graphical representations of the gates defined above, see Figure 1.The qutrit Cli ff ord group C [16] is generated by SUM , X , H , and Q , where H and Q are defined asfollows: H = √ ζ ζ ζ ζ , Q = ζ , . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore V ( U ) U C c ( U ) U c X SUM C ( X ) c C ( SUM ) c Fig. 1. Graphical representations of some ternary gates where we use the notation ζ n = e π in for n ≥ SUM , all the reversible 1-qutrit gates and
SWAP are alsocontained in C . Moreover, SUM and all the 1-qutrit reversible gates generate the subgroup of allreversible gates in C . Some other Cli ff ord gates are Z and V ( Z ), where Z = diag(1 , ζ , ζ ), and V ( Z ) = ( I ⊗ H ) SUM ( I ⊗ H − ) : | i , j i 7→ ζ i j | i , j i . However, C ( X ) , Horner , C ( SUM ) and S , arenon-Cli ff ord gates.Consider two pairs of standard basis vectors | j i , | k i and | j i , | k i . It would be useful to notethat the two-way classical reflection S | j i , | k i that swaps the | j i , | k i and fixes everything else can bereduced to the corresponding reflection S | j i , | k i by applications of O ( n ) SUM and
SWAP gates (thatare Cli ff ord gates: see [9], Lemma 16). In particular, the two-way swap S , is Cli ff ord-equivalentto any other two-qutrit two-way swap.We think of Cli ff ord gates as being cheap in the quantum sense. General rationale for this assump-tion is that such gates can be simulated classically. (Additional motivation coming from topologicalcomputing: in the context of non-abelian anyons such as SU(2) anyon system [8], Cli ff ord gates canbe obtained by anyon braiding alone.) Thus we define the complexity (resp. depth) of a circuit as thenumber (resp. depth) of non-Cli ff ord gates.The following two identities will be used, where ω ( n ) is the number of 1 ′ s in the binary expansionof n , and ⌊ x ⌋ means the maximal integer less than or equal to x : ∞ X i = (cid:22) n i (cid:23) = n − ω ( n ) , (2) ⌊ log n ⌋ + X i = $ n i − % = n − (cid:4) log n (cid:5) − . (3)See also [17] for similar identities. Given two n -trit numbers a = a n − · · · a a , b = b n − · · · b b , an adder computes their sum s = s n s n − · · · s = a + b . The elementary method of adding two n -trit numbers is illustrated in Figure 2.Let c = ≤ i ≤ n , let c i be the carry trit arising from a i − , b i − , c i − ,namely, c i = a i − + b i − + c i − ≤ c i = ≤ i ≤ n − s i = a i + b i + c i mod 3and s n = c n .In Section 3.1 and Section 3.2, we present two methods to implement reversible ternary quantumadder: a ripple-carry adder and a carry look-ahead adder. The two adders are generalized from theirbinary counterparts [17, 18], but the generalizations are somewhat nontrivial, as seen later. On onehand, the modified ripple-carry adder uses only 1 ancilla for the whole process and has the circuit depthin O ( n ). On the other hand, the carry look-ahead adder requires O ( n ) ancillas with the advantage of Improved Quantum Ternary Arithmetics a n − · · · a a b n − · · · b b c n c n − · · · c c = s n s n − · · · s s Fig. 2. Addition of two n -trit numbers having circuit depth in O (log n ). We will also compare the two adders to other ternary adders knownin literature and show that our adders are more e ffi cient both space-wise and depth-wise.To implement the adders, we utilize C ( X ), C ( SUM ), C ( S , ) and S , as the basic building units.As shown in Section 5.1, C ( SUM ), C ( S , ) and S , can all be constructed exactly from C ( X ) andCli ff ord operations. Therefore, the circuit of adders can be designed from Cli ff ord operations and C ( X ) alone. The reason that we still treat C ( SUM ), C ( S , ) and S , as basic units is that it mightbe more e ffi cient to synthesize them directly in some basis rather than breaking them up into C ( X ) ′ s.An example is the metaplectic basis [9], where S , has an e ffi cient approximation by a metaplecticcircuit. The binary quantum ripple-carry adder was considered in [19], where O ( n ) ancillas are required toadd two n -qubit numbers. In [17], the method was improved so that only 1 ancilla is necessary. Herewe give a ternary generalization of the improved ripple-carry adder.Note that in contrast to the binary case, the ternary carry is more complicated: if the inputs to abinary full adder are denoted by a , b , c ∈ F , then the outgoing carry is given by c out = ab + ac + bc ,where all operations are computed modulo 2. In case of a ternary full adder with inputs a , b , c ∈ F ,the outgoing carry is given by c out = + a + b + c )( ab + ac + bc ) + abc , where all operations arecomputed modulo 3. Though directly implementing this polynomial using the presented universalgates is possible, it leads to a relatively large number of elementary gates. A simple observationallows to reduce this cost significantly as it turns out that c out does not have to be implemented for all27 input triples but rather only 18 of them. Indeed, it can be shown inductively that—provided thereis no initial incoming carry—for ternary adders, every carry trit c i can only be either 0 or 1, but cannever be 2. This is indicated also in Figure 3 where the crossed out case indicates that this can neveroccur in an actual addition: the case c i + = c i =
2, which inductively we assumecannot happen. With this definition, c i + becomes a balanced function, i.e., there are the same numberof inputs corresponding to each outcome c i + .We sketch the idea of constructing the circuit to compute c i + from a i , b i and c i based on thisobservation. As illustrated in Figure 3, c i + equals c i for all but six inputs, the last three inputs inthe column c i + = c i + =
1. For each of these six inputs, c i + equals 1 − c i . If the gate S , is applied to qutrits a i , b i , then the six inputs are turned into six newtriples. See Figure 4 for the transition. Moreover, the new six triples are exactly equal to the set { ( a , b , c ) ∈ { , , } : a + b = c , c , } . In light of these observations, a reversible circuit, called Carry,is constructed, which takes c i , a i , b i as input, and outputs c i + in the last qutrit. See Figure 5, where f and g are some functions of a i , b i , c i . The exact shape of f and g is not important since they will bereversed at the appropriate step of the adder.As illustrated in Figure 5, the circuit Carry is ancilla free, in contrast to the carry circuit consideredin [13] where 1 ancilla is required for each round of carry. See Figure 6 for the comparison. The circuit . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore c i + = c i + = ✘✘✘✘ c i + = a i b i c i Fig. 3. Ternary carry table c i + = c i + = a i b i c i c i + = c i + = a i b i c i S , = ⇒ Fig. 4. Transition of inputs due to S , utilizes one S , , one C ( S , ), two SUM , and two
SWAP gates. The
SUM and
SWAP are bothCli ff ord gates, so only 2 non-Cli ff ord gates are needed. The depth of Carry in terms of non-Cli ff ordgates is also 2. Moreover, unlike the binary ripple-carry circuit MAJ [17] where the two qubits otherthan c i + end up with a i + b i , c i + b i , in our circuit the two qutrits other than c i + have the final values f ( a i , b i , c i ) and g ( a i , b i , c i ). This is the reason we call our carry circuit modified . However, as will beseen below, the modified carry circuit works in the same way as the regular one.Let C : | c i , a i , b i i → | f ( a i , b i , c i ) , g ( a i , b i , c i ) , c i + i be the Carry gate represented by the circuit inFigure 5. Similar to the adder circuit in [17], the modified ripple-carry adder circuit is designed inFigure 7, which, as an illustration, shows the addition of two 3-qutrit numbers.In Figure 7, the qutrit c , initialized with 0, is the only ancilla required. The qutrit on the bottomholds the overflow trit, i.e., the highest trit in the sum. Therefore, to add two n -qutrit numbers, exactly1 ancilla, n Carry gates, n inverse Carry gates and 2 n SUM gates are required, and the depth of thecircuit is 4 n . In contrast, the adder in [13] uses n ancillas and has the complexity in O ( n ). In the ripple-carry adder, the carry c i + is computed only after the value of c i has been obtained, andthus the overall depth of the circuit is in O ( n ). One protocol to reduce the depth is the carry look-aheadadder studied in [18] for the binary addition. Here we generalize it to give a ternary carry look-aheadadder, which computes all the carry trits in depth O (log n ) by introducing extra O ( n ) ancillas.The main idea is that there are relations between c i and c i + , and more generally between c i and c j for i , j . For instance, if a i + b i =
2, then c i + = c i . If a i + b i =
1, then c i + = c i . See Figure 8 for a summary of the relation between c i + and c i . Note that c =
0, thus when i =
0, the column c i + = c i in Figure 8 becomes c = c =
0. Motivated by their relations, we define,for 0 ≤ i < j ≤ n , the carry status indicator C [ i , j ] : cibiai S , † S , SWAP SWAP ci + g ( ai , bi , ci ) f ( ai , bi , ci ) Fig. 5. the circuit Carry
Improved Quantum Ternary Arithmetics cibiai ci + g ( ai , bi , ci ) f ( ai , bi , ci )Carry 0 cibiai ci + cibiai Carry
Fig. 6. (Left) ripple carry in the present paper; (Right) ripple carry studied in [13] b a b a b a c C C C C − C − C − s s a s a s a c Fig. 7. Circuit for ripple-carry adder C [ i , j ] = c j = c i c j = c i c j = c i Since we already know c =
0, the case c j = c is then the same as the first case c j =
0. Thus wecan treat these two cases as one, and design C [0 , j ] so that it will never take the value 2, namely, wewill have C [0 , j ] = c j .Explicitly, for 0 < i < n , the circuit, AdjC , shown in Figure 9 computes C [ i , i +
1] from a i and b i . Itrequires 1 non-Cli ff ord gate S , , and no ancilla. However, to compute C [0 , ff ord gates S , , C ( X ). See Figure 10 for the circuit, which we call AdjC .Having computed the carry status indicators for any two adjacent indices, we furthermore compute C [ i , j ] for arbitrary i , j . For 0 ≤ i < k < j ≤ n , C [ i , j ] can be obtained from C [ i , k ] and C [ k , j ] by the merging formula in Figure 11.Note that when i =
0, the row corresponding to C [0 , k ] = C [0 , k ] takes values in { , } , so will C [0 , j ]. A circuit, M , realizing the merging formula isillustrated in Figure 12, where M takes C [ i , k ] , C [ k , j ], and an ancilla initialized to 0 as inputs, andoutputs C [ i , j ] to the ancilla. The circuit requires 1 non-Cli ff ord gate C ( SUM ).The circuits
AdjC and
Ad jC both only depend on a i and b i , thus we can compute all the C [ i , i + ′ sin one time slice. The nature of the merging formula enables us to obtain all the C [0 , j ] ′ s in O (log n ) c i + = c i + = c i + = c i a i b i Fig. 8. Relation between c i + and c i . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore biai S , S , C [ i , i + Fig. 9. Circuit
AdjC computing C [ i , i + < i < n biai S ,
22 0
SWAP SWAP C [0 , Fig. 10. Circuit
AdjC computing C [0 , time slices. We elaborate this below.For i = , , · · · , n −
1, let B i be the working register configured to be C [ i , i +
1] at the beginning,and let Z i + be the working registers initialized to | i , which will end up with C [0 , i + n − ω ( n ) − (cid:4) log n (cid:5) ancillas X i initialized to | i . The circuit consists of three processes, namely, P -process, C -process, and P − -process. Each process roughly contains (cid:4) log n (cid:5) rounds.In P -process, we compute all the carry status indicators of the form C [2 t m , t ( m + C [0 , k ] which are written to Z [2 k ]. There are (cid:4) log n (cid:5) rounds, each t = , · · · , (cid:4) log n (cid:5) corresponding to one round. In the t -th round, which we call the P [ t ]-round, the status indicators C [2 t m , t ( m + m = , · · · , j n t k − merging formula, C [2 t m , t ( m + C [2 t − (2 m ) , t − (2 m + t − (2 m + , t − (2 m + P [ t − M producing C [2 t m , t ( m + ff erent m ′ s in the P [ t ]-round takes di ff erent carry status indicatorsin P [ t − P [1]-round requires the carry status indicators C [ i , i + ′ s inthe registers B i . Therefore, in the P [ t ]-round, all the circuits M computing C [2 t m , t ( m + P [ t − P -process is (cid:4) log n (cid:5) , the number of ancillas needed is n − ω ( n ) − (cid:4) log n (cid:5) ,and the complexity is n − ω ( n ).In C -process, we compute C [0 , j ] into the register Z j , j = , · · · , n . This is performed in j log n k + C [0 , k ] ′ s have already been obtained in P -process, and are located in the desiredpositions. For t = j log n k , · · · ,
0, the C [ t ]-round consists of computing the carry status indicators C [0 , t (2 m + , m = , · · · , j n t + − k . Again, by the merging formula, we can get C [0 , t (2 m + C [0 , t + m ] and C [2 t (2 m ) , t (2 m + C [0 , t + m ] has been obtained in earlier C -rounds if m is not a power of 2, and in the P [ t + + log m ]-round otherwise. Also C [2 t (2 m ) , t (2 m + P [ t ]-round. Therefore, we can run all the M circuits in the C [ t ]-round in aparallel way. These circuits depend on the carry status indicators in the P [ t ]-round and C [ k ]-rounds, k ≥ t +
1. If m is a power of 2, then the corresponding M circuit also depends on C [0 , t + m ] from the J C [ k , j ]0 1 2 C [ i , k ] 0 0 1 01 0 1 12 0 1 2 Fig. 11. The merging formula C [ i , j ] = C [ i , k ] J C [ k , j ]0 Improved Quantum Ternary Arithmetics C [ k , j ] C [ i , k ] † C [ i , j ] C [ k , j ] C [ i , k ] Fig. 12. Circuit M realizing the merging formula C [ j log n k ] · · · C [ (cid:4) log n (cid:5) − · · · C [0] P − [ (cid:4) log n (cid:5) − · · · P − [2] P − [1] Fig. 13. Parallelism between C - and P − -process P [ t + + log m ]-round. Thus the circuit in C -process has a depth of j log n k +
1, and the complexityis n − (cid:4) log n (cid:5) − P − -process, we set the ancillas back to | i , thus we need to reverse all the M circuits in P -process, except for those computing C [0 , k ] ′ s which are not stored in the ancillas. The P − -processconsists of (cid:4) log n (cid:5) − t = (cid:4) log n (cid:5) − , · · · ,
1, the P − [ t ]-round uncomputes C [2 t m , t ( m + m = , · · · , j n t k − M . Note that in this process, all the C [0 , k ] ′ s will notbe touched. The process has a depth of (cid:4) log n (cid:5) −
1, and the complexity of the circuit is n − ω ( n ) − (cid:4) log n (cid:5) .We note that most parts of C -process and P − -process can actually be parallelized. The argumentis as follows. All the inputs to the C [ t ]-round which are not of the form C [0 , m ] only depend on C [ k ]-rounds, k ≥ t +
1, and the P [ t ]-round. The inputs that are of the form C [0 , m ] were computed in P [ m ]-round, but they will not be touched in P − -process. The P − [ t + P [ t + P [ t + C [ t ]-round and the P − [ t + C -process and P − -process is illustratedin Figure 13.To summarize, the whole circuit uses n − ω ( n ) − (cid:4) log n (cid:5) ancillas, and has a depth of (cid:4) log n (cid:5) + j log n k +
2. The total complexity of the circuit is 3 n − ω ( n ) − (cid:4) log n (cid:5) − We give two implementations of carry look-ahead adder, namely, the out-of-place adder and the in-place adder. Recall that the circuits in Figure 9, 10, and 12 are denoted by
AdjC , AdjC , and M ,respectively. The complexity of both AdjC and M is 1, and the complexity of AdjC is 2. The depthof these circuits is equal to their complexity. Let A i , B i be the registers with initial value a i , b i , respectively, i = , · · · , n −
1. Let Z i , i = , · · · , n be the registers initialized to be 0, which will hold the sum a + b at the end of the computation. Weneed n − ω ( n ) − (cid:4) log n (cid:5) ancillas X i to store intermediate carry status indicators. The following is adescription of the circuit of our out-of-place adder. Out-of-place Procedure:
1. For 0 < i ≤ n −
1, run the circuit
AdjC on A i , B i , which outputs C [ i , i +
1] to B i . Run AdjC on A , B , and Z with Z as the ancilla, which outputs C [0 ,
1] to B . Copy C [0 ,
1] to Z with the SUM gate. The circuit has a depth of 2, and it consist of n − AdjC , 1
AdjC , and 1 SUM gates. . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore AdjC AdjC M Fig. 14. Circuit glyphs for
AdjC , AdjC and M . The inverse gates AdjC − , AdjC − and M − are represented bymirror images of these glyphs.
2. As discussed in Section 3.2, compute all the C [0 , i ] ′ s with the ancillas X i ′ s and the circuit M ± . At the end of this process, the ancillas are returned to 0, and Z i = C [0 , i ] , i = , · · · , n . f This requires 3 n − ω ( n ) − (cid:4) log n (cid:5) − M ± , and has a circuit depth of (cid:4) log n (cid:5) + j log n k + AdjC ′ s and AdjC . At the end of this step, we have B i = b i , Z i = C [0 , i ] = c i . Thecircuit has a depth of 2, and it consist of n − AdjC − , 1 AdjC − , and 1 SUM − .4. Set Z i = Z i ⊕ A i ⊕ B i , 0 ≤ i ≤ n −
1. This requires 2 n SUM gates.In summary, the out-of-place adder uses n − ω ( n ) − (cid:4) log n (cid:5) ancillas, and has a circuit depth of (cid:4) log n (cid:5) + j log n k +
6, with the complexity of 5 n − ω ( n ) − (cid:4) log n (cid:5) − AdjC , AdjC and M as shown in Figure 14. Their inverses are represented by thesame circuit with replaced by . Also a black rectangle means the content will be changed afterthe application of the relevant gate, while a blank rectangle means the content remains the same. Anan illustration, we give a complete out-of-place circuit for adding two 10-qutrit numbers in Figure 15,where we use x to stand for 10, and c i j is the carry status indicator C [ i , j ]. From Figure 15, it is clearthat the C [0]-round and P − [2]-round can be parallelized since the gates in these two rounds act ondi ff erent wires. One can also verify the cost: the number of ancillas is n − ω ( n ) − (cid:4) log n (cid:5) =
5, thedepth of the circuit is (cid:4) log n (cid:5) + j log n k + =
10, and the complexity is 5 n − ω ( n ) − (cid:4) log n (cid:5) − = The idea of in-place adder is also generalized from that in [18]. Let ¯2 be the n -trit number with all2 ′ s, namely ¯2 = n −
1. When no confusion arises, we make no distinction between a number andits trit representation. For two n -trit numbers a , b , denote by a ⊕ b the number obtained by trit-wisesummation modulo 3, and denote by a ′ the number obtained by replacing every trit a i by 2 − a i . Thus,the following equations hold: a ⊕ a ′ = ¯2 and a + a ′ = n − . Let c = c · · · c n − be the sequence of the n low carry trits for a and b , and let s be the n low tritsof a + b . Then we have s = a + b (mod 3 n ) and s = a ⊕ b ⊕ c . Also note that s ′ + a = n − − s + a = n − − b = b ′ (mod 3 n ).Let d = d · · · d n − be the n low carry trits resulting from adding s ′ and a . Then, s ′ ⊕ a ⊕ d = b ′ ,and thus we have, f Z = C [0 ,
1] was obtained in the previous step.2
Improved Quantum Ternary Arithmetics b a b a b a b a b a b a b a b a b a b a c xc c c c c c c c c P [1] P [2] P [3] c xc c c c c c c C [1] C [0] c xc c c c c c P − [2] P − [1] b b b b b b b b b b sx b a s b a s b a s b a s b a s b a s b a s b a s b a s b a s Step 1 Step 2 Step 3 Step 4
Fig. 15. Out-of-place carry look-ahead adder . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore ¯2 ⊕ a ⊕ b ⊕ d = s ⊕ s ′ ⊕ a ⊕ b ⊕ d = s ⊕ b ′ ⊕ b = ¯2 ⊕ a ⊕ b ⊕ c . Therefore, c = d , i.e., the n low carry trits for a , b are the same as those for s ′ , a . We will use thisproperty to implement the in-place adder.For 0 ≤ i ≤ n −
1, let A i , B i be the working registers initialized with a i , b i , respectively. We willneed 2 n − ω ( n ) − (cid:4) log n (cid:5) ancillas, n of which are denoted by Z , Z , · · · , Z n − and the rest are X i ′ s. Let Z n be the working register which will store the high trit of a + b . All ancillas start with 0. In-place Procedure:
1. As described in Out-of-place Procedure Step 1 through 3, compute all the carry trits C [0 , j ] into Z j , j = , · · · , n . The ancillas X i ′ s and working registers A i , B i are all returned to their initialconfiguration at the end of the process. This has a circuit depth of (cid:4) log n (cid:5) + j log n k +
6, withthe complexity of 5 n − ω ( n ) − (cid:4) log n (cid:5) + ≤ i ≤ n −
1, let B i = B i ⊕ A i ⊕ Z i , namely, the register B i ′ s will store the n low trits of thesum a + b . This can be done by 2 n SUM gates.3. Now we want to erase the n carry trits C [0 , i ] = c i , i = , · · · , n −
1. For 0 ≤ i ≤ n −
2, let B i = − B i . This can be achieved by n − S , gates.4. Apply the inverse of the Out-of-place Procedure Step 1 through 3 on the registers A i , B i for0 ≤ i ≤ n − c j stored in Z j , j = , · · · , n − ≤ i ≤ n −
2, let B i = − B i . Again this can be done by n − S , gates.Tracing the cost of the circuit above, we see that the in-place adder has a depth of (cid:4) log n (cid:5) + j log n k + (cid:4) log ( n − (cid:5) + j log n − k +
12, and its complexity is 10 n − ω ( n ) − (cid:4) log n (cid:5) − ω ( n − − (cid:4) log ( n − (cid:5) − n − ω ( n ) − (cid:4) log n (cid:5) .Figure 16 gives a complete circuit of in-place adder for n =
10. See Figure 14 and the lastparagraph in Section 3.3.1 for the explanations of notations used in the circuit.
In this section, we give various extensions based on the modified ripple-carry adder and the carrylook-ahead adder, including addition modulo 3 n , subtraction, and comparison. n To add two n -qutrit numbers modulo 3 n , we simply do not compute the the high carry trit c n .In the ripple-carry adder (see Figure 7), it su ffi ces to remove the circuit C , SUM , C − in the middle,and the last qutrit on the bottom. Thus in total we need 1 ancilla, 2( n −
1) Carry gates, and 2 n − SUM gates, and the depth of the circuit is 4( n − Improved Quantum Ternary Arithmetics b a b a b a b a b a b a b a b a b a b a sx s a c s a c s a c s a c s a c s a c s a c s a c s a c s a c S S S S S S S S S s ′ s ′ s ′ s ′ s ′ s ′ s ′ s ′ s ′ † s ′ s ′ s ′ s ′ s ′ s ′ s ′ s ′ s ′ S S S S S S S S S sx s a s a s a s a s a s a s a s a s a s a Step 1 Step 2 Step 3 Step 4 Step 5
Fig. 16. In-place carry look-ahead adder . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore In the out-of-place carry look-ahead adder, we run the circuit as described in Out-of-place Proce-dure in Section 3.3.1. However, in the first three steps of the procedure, we restrict the inputs to the n − a and b , namely, a , · · · , a n − , b , · · · , b n − , since there is no need to compute c n . Ofcourse, in the last step we still need to compute the modulo summation a i ⊕ b i ⊕ c i for all 0 ≤ i ≤ n − n − − ω ( n − − (cid:4) log ( n − (cid:5) ancillas, and has a circuitdepth of (cid:4) log ( n − (cid:5) + j log n − k +
6, with complexity 5( n − − ω ( n − − (cid:4) log ( n − (cid:5) + n adder, we run exactly the same circuit asthe In-place Procedure in Section 3.3.2, except in Step 1 where we again restrict the inputs only to the n − a and b . It is direct to total the cost of the circuit. It has a depth of 2( (cid:4) log( n − (cid:5) + j log n − k + n − − ω ( n − − (cid:4) log ( n − (cid:5) + n − − ω ( n − − (cid:4) log ( n − (cid:5) . To compute a − b for two n -trit numbers a , b , first convert a to a ′ , then compute a ′ + b , and eventuallyconvert a ′ + b to ( a ′ + b ) ′ . Note that a ′ is the n -trit number obtained by replacing each a i by 2 − a i ,namely, a ′ = n − − a . Thus we have,( a ′ + b ) ′ = (3 n − − a + b ) ′ = n − − (3 n − − a + b ) = a − b . Changing a to a ′ costs n Cli ff ord gate S , . Therefore, the circuit for subtraction has the samedepth and complexity as the regular the adder. Given the circuit for subtraction, it is straightforward to compare two numbers a and b . Actually, thereis a circuit for the comparison of a , b with smaller complexity than that of subtraction since we onlyneed to know the high trit of a − b . Let a ′ = n − − a , then a − b ≥ a ′ + b is 0.In the ripple-carry adder, we convert a to a ′ and use the Carry gate C to compute all the carry trits c , · · · , c n for a ′ + b . After copying c n to the register storing the result of the comparison, we undo allthe C ′ s and convert a ′ back to a . The circuit thus requires 1 ancilla, 2 n Carry gate C , 1 SUM gate, 2 nS , , and has a depth of 4 n .In the carry look-ahead adder, again we first convert a to a ′ . To compute a ′ + b , the circuitsequentially generates all the carry status indicators C [ i , j ] ′ s. However, since we only care about thehigh trit c n = C [0 , n ], we can design a more e ffi cient circuit to implement the comparison.Recall from Section 3.2 that in P process we have obtained all the carry status indicators of theform C [2 t m , t ( m + C [0 , k ] is of this form. Therefore, if n = k for some k , then c n is obtained at the end of P process. At this moment, there is no need to go through the C process. Instead, we copy c n into the register storing the result, and undo the P process. In general, let k = (cid:6) log n (cid:7) , then we can just pad a and b by adding zeros in the front to make them 2 k -trit numbers,and use the circuit described above to compare a and b . We still call the 2 k -trit numbers a and b . For0 ≤ i ≤ n −
1, let A i = a i , B i = b i be the working registers, and let R the register which will store theresult of the comparison. We also need 2 k + k − n ) ancillas, among which 2(2 k − n ) are used to holdthe extra zeros in from of a and b , one is denoted by Z as the ancilla to the AdjC circuit, and the restare denoted by X i ′ s.Note that after padding a and b with zeros, the carry status indicators C [ i , j ] ′ s, n ≤ i < j ≤ k , are Improved Quantum Ternary Arithmetics known before the compilation, thus we can store their values in the registers and there is no need torecompute them later.
Carry Look-ahead Comparison:
1. Convert a to a ′ . This requires 2 k S , gates.2. For 0 < i ≤ n −
1, run the circuit
AdjC on A i , B i , which outputs C [ i , i +
1] to B i . Run AdjC on A , B , and Z with Z as the ancilla, which outputs C [0 ,
1] to B . The circuit has a depth of 2,and it consist of n − AdjC and 1
AdjC .3. Perform the P process in Section 3.2 to compute all the C [2 t m , t ( m + X i . Note that here since we don’t have the Z i registers, all the C [0 , m ] ′ s are also written to the X i registers. The depth of the circuit is k , andthe complexity is 2 k − ω (2 k ) − (2 k − n − ω (2 k − n )) = n + ω (2 k − n ) − c k to the result register R .5. Undo Step 3.6. Undo Step 2.7. Undo Step 1.Therefore, the total depth of the circuit above is 2 k + = (cid:6) log n (cid:7) +
4, and it has the complexityof 4 n + ω (2 k − n ) = n + ω (2 ⌈ log n ⌉ − n ). The number of ancillas used is 3 · ⌈ log n ⌉ − n . In previous sections, we developed a system of ternary arithmetic with the focus on two types ofquantum ternary adders. The building blocks of these circuits include the Carry circuit C , the circuits AdjC , AdjC computing carry status indicators, and the merging formula M . Moreover, the non-Cli ff ord gates used in these four circuits are S , , C ( S , ) , C ( X ) , and C ( SUM ).In this section, we show that it su ffi ces to have C ( X ) along with Cli ff ord gates to produce the otherthree non-Cli ff ord gates exactly. The key technique involved is to analyze the algebraic expressionsof these gates. In Section 5.1, it is proven that C ( X ) and Horner are equivalent up to Cli ff ord gates,and that all other non-Cli ff ord gates can be obtained from C ( X ). In Section 5.2, we introduce auniversal gate set called supermetaplectic basis, which is a qutrit analog of the qubit Cli ff ord + π -gate. We then illustrate in Section 5.3 that C ( X ) and Horner can both be implemented exactly oversupermetaplectic basis. Therefore, with the supermetaplectic basis, the ternary circuits for arithmeticcan be realized exactly. Let F be the field with three elements { , , } . Then any n -qutrit reversible gate can be represented asa map F n F n , or a sequence of n functions F n F , if one identifies each | i i with i , i = , ,
2. Wewill see that reversible gates have polynomial representations and these polynomial representationsprovide hints to construct one reversible gate from another.Note that 0 = , = = δ i , = − i (mod 3). By default, arithmetic withina ket is taken modulo 3. The following is a list of polynomial expressions of some non-Cli ff ord gates. . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore Fig. 17. A circuit for S , • SUM = V ( X ) : | i , j i 7→ | i , i + j i ; • C ( X ) : | i , j i 7→ | i , j + δ i , i = | i , j − i + i ; • Horner: = V ( V ( X )) : | i , j , k i 7→ | i , j , i j + k i ; • C ( SUM ) : | i , j , k i 7→ | i , j , k + (1 − i ) j i .The above list shows that if a qutrit works as a soft control, then it contributes a linear factor in theexpression of the target qutrit, while a hard control qutrit contributes a quadratic factor.Define C ′ ( X ) : | i , j i 7→ | i , j + i i . Thus, C ′ ( X ) = ( I ⊗ X ) C ( X ) − is equivalent to C ( X ). We will use C ′ ( X ) below for the construction of other gates.The relation between the expressions of Horner and C ′ ( X ) resembles that of a bilinear form and aquadratic form, which are equivalent. This suggests that Horner and C ′ ( X ) are also equivalent. Indeed,the following diagrams give a construction of one from another. • implementation of Horner gate in terms of C ′ ( X ) : | i , j , k i SUM , −→ | i , i + j , k i C ′ ( X ) − , −→ | i , i + j , k − ( i + j ) i SUM − , −→| i , j , k − i − j + i j i C ′ ( X ) , −→ | i , j , k − j + i j i C ′ ( X ) , −→ | i , j , k + i j i . • implementation of C ′ ( X ) , gate in terms of Horner : | i , j , k i SUM , −→ | i , j , i + k i Horner , , −→ | i , j + i + ik , i + k i SUM − , −→ | i , j + i + ik , k i Horner − , , −→ | i , j + i , k i . Note that in the construction of 2-qutrit C ′ ( X ), we made use of a third qutrit, but that qutrit doesnot have to be clean, namely it could have arbitrary state.Similarly, C ′ ( X ) is enough to construct C ( SUM ): C ( SUM ): | i , j , k i C ′ ( X ) , −→ | i , i + j , k i C ′ ( X ) , −→ | i , i + j , k + ( i + j ) i C ′ ( X ) − , −→ | i , j , k + i + j − i j i C ′ ( X ) − , −→| i , j , k + j − i j i C ′ ( X ) − , −→ | i , j , k − i j i SUM , −→ | i , j , k + (1 − i ) j i . To implement C ( S , ) and S , , notice that the circuit in Figure 17 realizes S , , and moreoverwe have: • S , = SUM − ( X − ⊗ I ) S , ( X ⊗ I ) SUM . • C ( S , ) = SUM − , ( X − ⊗ X − ) S , ( X ⊗ X ) SUM , . Recall from Section 2 that C is the qutrit Cli ff ord group generated by H , Q , X , and SUM . Some othergates in C are Z and V ( Z ), where Z = diag(1 , ζ , ζ ), and V ( Z ) = ( I ⊗ H ) SUM ( I ⊗ H − ). It can bedirectly verified that V ( Z ) has the following expression: ^ ( Z ) : | i , j i 7→ ζ i j | i , j i . Improved Quantum Ternary Arithmetics
In [8], it has been established that the multi-qutrit metaplectic gate set C + diag(1 , , −
1) or equiv-alently C + diag(1 , ζ , ζ ) was universal for quantum computation in the sense that any multi-qutritunitary operator can be approximated to any given precision by a circuit over that gate set. We conjec-ture that the metaplectic gate set is not universal for exact reversible computation, i.e. it seems that thesubgroup of reversible classical gates that can be represented exactly by metaplectic circuits is ratherthin. In order to ensure exact representation of the reversible gates over a relatively simple multi-qutritbasis, we expand the basis by adding essentially the “cubic root” of the Z gate to it. To this end weincrease the order of the root of unity used in defining the non-Cli ff ord diagonal gate, and define P as the 1-qutrit diagonal gate diag( ζ − , , ζ ). g Definition 1
The gate set C + P is called supermetaplectic basis. Since the P gate is non-Cli ff ord, this basis is universal for quantum computation. The supermeta-plectic basis resembles the qubit Cli ff ord + T basis in several aspects. Firstly, we show in Section 5.3that all the reversible gates can be constructed exactly over the supermetaplectic basis. Secondly, the P gate is a fundamental diagonal gate in the third level of the Cli ff ord hierarchy [20]. Lastly, it wasshown in [21] that P can be obtained by magic state distillation. We continue exploring the use of polynomial expressions in constructing new quantum gates.The group of reversible gates in C is generated by SUM , X , S , . More precisely, it is described bythe following proposition. Proposition 2 { S , X , SUM } generate a maximal subgroup, which is isomorphic to ≃ GL( n , F ) ⋊ F n ,of the group of reversible gates for any number n of qutrits. Proof:
See Appendix 9.The statement in Proposition 2 for the case n = n , F ) ⋊ F n and the group generatedby { S , X , SUM } is as follows:Given a pair ( A , v ) ∈ GL( n , F ) ⋊F n , where A = ( a i j ) ≤ i , j ≤ n , v = ( v i ) ≤ i ≤ n , then the reversible n -qutritgate corresponding to it maps | x i , for any computational basis element | x i = | x , · · · , x n i , to | A . x + v i .Moreover, any reversible gate of this form is generated by { S , X , SUM } .A function f : F n F is called a ffi ne linear if f ( x , · · · , x n ) = a x + · · · + a n x n + b , where a , · · · , a n , b ∈ F . A reversible n -qutrit gate can be viewed as an n -tuple of functions: | x i 7→| f ( x ) , · · · , f n ( x ) i , where we call f i the coordinates of the gate. Then the above argument shows thata reversible n -qutrit gate is generated by { S , X , SUM } if and only if all of its coordinates are a ffi nelinear functions. Let F n be the set of all a ffi ne linear functions from F n to F .Let D be the group generated by the reversible gates in C , together with the diagonal gates V ( Z )and P . We give a technique to characterize all the diagonal gates in D .By Proposition 2 and the argument above, the reversible gates in D can change the basis element | x i to any element of the form | f ( x ) , · · · , f n ( x ) i , where f i is an a ffi ne linear function F n to F . Theaction of V ( Z ) and P will contribute a scalar to the basis element. Thus the most general n -qutritdiagonal gate in D has the form: g This is the the distillable gate denoted M † in [21]. . Bocharov, S.X. Cui, M.Roetteler, K.M. Svore | i , i , · · · , i n i 7→ ζ P f ∈F n A f f ( i , ··· , i n )9 ζ P f , g ∈F n B f , g f ( i , ··· , i n ) g ( i , ··· , i n )3 | i , i , · · · , i n i , (4)where A f , B f , g are integer parameters. Notice that the a ffi ne linear functions f and g take values in F , while A f , B f , g take values in Z . We have to evaluate f , g first in { , , } , then multiply by A f , B f , g inside Z . This is critical for the term ζ .As an application, we show that V ( V ( Z )) and C ( Z ) are both contained in D . The expressions ofrelevant gates are given below. • V ( Z ) | i , j i = ζ i j | i , j i , P | i i = ζ i | i i , • X | i i = | i + i , S , | i i = | i i , SUM | i , j i = | i , i + j i . • V ( V ( Z )) : | i , j , k i 7→ ζ i jk | i , j , k i . • C ( Z ) : | i , j i 7→ ζ j δ i , | i , j i .For n =
3, the coe ffi cient in Formula 4 can be written as: L ( i , j , k ) = ζ P a , b , c , d = A a , b , c , d ( ai + b j + ck + d )9 ζ Bi j + C jk + Dik , i , j , k ∈ F , (5)where A a , b , c , d , B , C , D are integer parameters h . Again ai + b j + ck + d is assumed to be taken modulo 3.To construct V ( V ( Z )), set L ( i , j , k ) = ζ i jk . Since ζ = ζ , we get the equation:Equ( i , j , k ) : X a , b , c , d A a , b , c , d ( ai + b j + ck + d ) + Bi j + C jk + Dik ) = i jk ( mod 9) , i , j , k ∈ F . (6)The set { Equ( i , j , k ) : i , j , k ∈ F } is a system of 27 linear equations in the variables A a , b , c , d , B , C , and D . Thus there is an e ffi cient way to find the solutions, if any.By direct calculations, one solution to the above system of equations is: ζ i jk = ζ (1 + i + j + k ) + + i + j + k ) + + i + j + k ) + + i + j + k ) + + i + j + k ) + + i + j + k ) + + i + j + k )9 , (7)where the terms on the exponent within each parenthesis is taken modulo 3.In light of the solution in Equation 7, it is not hard to create a circuit realizing V ( V ( Z )). Explicitly,this is given in Figure 18.Similarly, with the same method, we construct a circuit for C ( Z ). See Figure 19.Note that V ( V ( Z )) , C ( Z ) are related with Horner , C ( X ), respectively, by the Cli ff ord gate H ,namely, we have, • ( I ⊗ H ) C ( X )( I ⊗ H † ) = C ( Z ) • ( I ⊗ I ⊗ H )Horner( I ⊗ I ⊗ H † ) = V ( V ( Z )).Therefore, both Horner and C ( X ) can be implemented exactly over supermetaplectic basis. h Actually there are also terms i , j , k on the exponent of ζ , but it is direct to see that ζ i = ζ (2 i mod 3) − ((2 − i ) mod 3)9 up to a globalphase, so the square terms can be absorbed into the ζ terms.0 Improved Quantum Ternary Arithmetics S , X ❥s❝ ❥s❝ ❥s❝ ❥s❝ P P † P † ❥ † s❝ ❥s❝ P X S , ❥ † ❝s ❥ † s❝ ❥ † ❝s X † Fig. 18. A circuit for V ( V ( Z )) P Q S , P P S , Fig. 19. A circuit for C ( Z ) Remark 3
1. The papers [22, 23] developed a similar framework for the binary case.2. If one uses the similar technique for the qubit Cli ff ord + T gates, namely replacing ( ζ , ζ ) with ( ζ , − , one obtains a circuit for the To ff oli gate with T -depth , which is optimal in the ancillafree scenario. We developed improved ternary circuits for reversible ternary adders of two types: the modified ripple-carry and the carry look-ahead adder. We have also derived solutions for a modulo 3 n adder, subtrac-tion and comparison in ternary encoding. We have o ff ered two levels of abstraction for describing thecorresponding ternary circuits: one in terms of reversible reflections of certain types and one in a moreuniform language that allows only one non-Cli ff ord gate: either the C ( X ) : | i , j i 7→ | i , j + δ i , mod 3 i or the P = diag( e − π i / , , e π i / ) gate.Future circuit synthesis work should entail the design of fully modular adders, circuits for singly-and doubly-controlled adders, as well as optimized circuits for singly- and doubly-controlled additiveshifts that would be essential parts of Shor’s integer factorization algorithm.An important theoretical direction of future work would be establishing lower complexity boundfor the arithmetic circuits and evaluating the e ffi ciency of designs presented here versus these bounds. Most of the work in the present paper was done during Summer 2015 when the second author wasinterning with Microsoft QuArC Group.
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Proof:
Let F n be the n -dimensional vector space over the finite field F . Then there is a one-to-one correspondence between the elements of F n and the computational basis of the n -qutrit space( C ) ⊗ n . That is, any element ( x , · · · , x n ) ∈ F n corresponds to the basis element | x , · · · , x n i . Thus anyautomorphism on F n induces a permutation on the n -qutrit basis, which is a reversible n -qutrit gate.Let G = GL( n , F ) ⋊ F n , the semidirect product of GL( n , F ) and F n , and let S n be the symmetricgroup on 3 n elements, or equivalently the group of reversible gates on n qutrits. We first prove thegroup generated by { S , X , SUM } is isomorphic to G . As a corollary of applying the O’Nan-ScottTheorem to the classification of maximal subgroups of the symmetric group [24] [25], it follows that G is a maximal subgroup of S n .The group G is the a ffi ne linear group of degree n over F , namely, it consists of all the pairs ( A , v ),where A is an n × n invertible group with entries in F , and v is a vector in F n . The group G acts on F n as follows: ( A , v ) . x = A . x + v , ( A , v ) ∈ G , x ∈ F n Therefore, we get a map ϕ : G −→ U (3 n ), such that ϕ ( A , v ) | x i = | Ax + v i , where | x i is anycomputational basis vector. This map ϕ is apparently a group homomorphism and injective.For 1 ≤ i , j ≤ n , define A i j , M i ∈ GL( n , F ) , v i ∈ F n as follows. A i j = I n + E ji = . . . . . . . . . , M i = I n + E ii = diag(1 , · · · , , , , · · · , , v i = (0 , · · · , , , , · · · , . It is straightforward to check that ϕ ( A i j , = SUM i j , ϕ ( M i , = ( S , ) i , ϕ (0 , v i ) = X i , wherethe subscript of the gate on the right hand side of each expression denotes the qutrits it acts on. Forinstance, X i is the X gate acting on the i -th qutrit. Therefore, the group generated by SUM , X , S , isisomorphic to the group generated by A i j , M i , v i , for 1 ≤ i , j ≤ n .Clearly all the v i ′ s generate F n as an additive group. We next prove that A i j , M i generate the groupGL( n , F ).Let B i j = M i A i j A − ji A i j = I n − E ii − E j j + E i j + E ji , thus B i j swaps the two basis elements e i and e j .Now given any matrix A ∈ GL( n , F ), multiplying A on the left by A i j , B i j , and M i constitutes the threetypes of row operations on A , and since A is invertible, it can always be reduced to the identity matrixby row operations. This proves that any matrix in GL( n , F ) can be written as a product of A i j , B i j , and M i . Therefore, GL( n , F ) is generated by A i j , M i , and hence G is generated by A i j , M i , and v i .Combining the above argument, we showed that the group generated by SUM , S , X is isomorphicto G = GL( n , F ) ⋊ F n3