InAs nanowire transistors with multiple, independent wrap-gate segments
A.M. Burke, D.J. Carrad, J.G. Gluschke, K. Storm, S. Fahlvik Svensson, H. Linke, L. Samuelson, A.P. Micolich
aa r X i v : . [ c ond - m a t . m e s - h a ll ] M a y InAs nanowire transistors with multiple, independentwrap-gate segments
A.M. Burke, † , ‡ D.J. Carrad, † J.G. Gluschke, † K. Storm, ‡ S. Fahlvik Svensson, ‡ H.Linke, ‡ L. Samuelson, ‡ and A.P. Micolich ∗ , † School of Physics, University of New South Wales, Sydney NSW 2052, Australia, and Solid StatePhysics/Nanometer Structure Consortium (nmC@LU), Lund University SE-221 00 Lund, Sweden
E-mail: [email protected]
Abstract
We report a method for making horizontal wrap-gate nanowire transistors with up to fourindependently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new ap-proach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orien-tation, where a significant subset of the fabrication steps needs to be repeated for each addi-tional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despiteseparations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate tran-sistors on a single nanowire using the exact same process. The excellent scalability potentialof horizontal wrap-gate nanowire transistors makes them highly favourable for the develop-ment of advanced nanowire devices and possible integration with vertical wrap-gate nanowiretransistors in 3D nanowire network architectures. ∗ To whom correspondence should be addressed † School of Physics, University of New South Wales, Sydney NSW 2052, Australia ‡ Solid State Physics/Nanometer Structure Consortium (nmC@LU), Lund University SE-221 00 Lund, Sweden eywords: III-V nanowires, wrap-gate, field-effect transistor, gate-all-around.
A driving force in electronics is the miniaturization of the field-effect transistor, a device wherethe current flowing through a semiconductor channel is electrostatically controlled by the voltageapplied to a metal gate electrode. The traditional planar Metal-Oxide-Semiconductor Field-EffectTransistor (MOSFET) features a two-dimensional channel separated from the gate by a thin in-sulating oxide in a parallel-plate capacitor arrangement. With the reduction in gate length below50 nm, the electrostatics of gate-channel coupling in these planar structures severely compromiseselectrical performance. This has fueled a push towards more advanced transistor designs, e.g.,Fin-FETs and trigate FETs, where the gate is ‘folded’ around the channel to enhance the coupling,mitigate short channel effects, and improve performance and scalability.
Such structures are nowused in Intel’s 22 nm technology node.From an electrostatic perspective, the ultimate configuration involves a gate wrapped aroundthe entire channel.
These structures can be made via traditional top-down approaches usingsilicon-on-insulator wafers but involve advanced processing strategies. Self-assembled nanowiresgrown vertically from a substrate by chemical vapor deposition present an interesting alterna-tive. Their geometry is particularly favorable for making concentric ‘wrap-gates’, a featurethat has been exploited to develop high-performance nanowire transistor arrays for poten-tial industrial applications. Horizontally-oriented wrap-gate nanowire transistors have also beendeveloped using conventional metal/oxide gate formulations, epitaxially grown gates andpolymer electrolyte gates. In forging ahead towards goals of both more complex nanowire devices and architecturesinvolving 3D nanowire transistor networks the next logical step is to develop methods formaking wrap-gate nanowire structures featuring multiple, independently-controllable wrap-gatesegments. We report a method for making a horizontal wrap-gate nanowire transistor with up tofour independently controllable wrap-gate segments and a single horizontal nanowire featuringtwo independent wrap-gated transistors extending from a common source/drain contact. In thisscheme, we limit the technology to fabricating discrete devices with multiple wrap-gates, while2he more complicated vertical processing more easily lends itself to processing and fabrication ofarrays of identical nanowire devices or circuits. We show a key advantage of the horizontal ori-entation: scalability. The step up to two independent wrap-gates requires a substantial change onearlier methods, but once this change is made, devices with more than two wrap-gates can bemade without incurring any additional processing steps. This is in stark contrast to the vertical ori-entation, where each additional gate entails a repetition of a significant subset of the process steps.As a result, while vertical wrap-gate nanowire transistors with two independent gate segmentshave been developed, further scaling in this orientation is likely to be challenging. Returning ourfocus to 3D architectures, this naturally puts the onus back on the horizontal orientation to carrythe scalability burden, hence the importance of research in this direction. Additionally, there issignificant scope for the development of both conventional and novel logic circuits usingmultiple wrap-gate nanowire transistors.Figure 1(b-d) show scanning electron micrographs of our two-, three- and four-gate nanowirewrap-gate transistors. A corresponding schematic for the device architecture is shown in Fig. 1(a).The fabrication process was inspired by previous work by Storm et al. , but it is vital to note thatit is impossible to make multiple gates using a single EBL resist approach. This is because eacharea of the wrap-gate that is etched away necessarily results in a metallic contact to the nanowireafter metal deposition. As a result, a number of significant process variations are required toenable the production of multiple wrap-gate segments; amongst them is the need to use multipleEBL resists to avoid device shorting, changes to outer oxide removal and a very different approachto setting wrap-gate segment length. The first fabrication step for the deposited nanowires is a30 s etch in buffered hydrofluoric acid (BHF) to remove the entire outer Al O layer, which isno longer required after deposition. The underlaying substrate is protected during this etch by theHfO layer. Electron-beam lithography (EBL) was performed using a Raith-150 two system intwo separate stages; these two stages are required irrespective of the number of wrap-gate segmentsor electrical contacts required. In the first stage we expose only the segments of the wrap-gate thatneed removal. This includes the gaps between wrap-gate segments and the points where source3igure 1: (a) Schematic of a horizontal wrap-gate nanowire transistor with two independently-controllable wrap-gate segments. The nanowire (grey) is interfaced by a pair of source and drainelectrodes (yellow) and wrap-gate interconnects (green). The cross-section is presented in the in-set. (b/c/d) Scanning electron micrographs of nanowire transistors with (b) two, (c) three and (d)four independent wrap-gate segments, respectively. The images shown are from the actual devicesstudied here, obtained after measurements were completed. The device in (b) was deliberately cho-sen to highlight that poor wrap-gate appearance does not necessarily correlate with poor electricalperformance – see text. The scale bars in each panel are 500 nm long.4r drain contacts meet the nanowire. The clean gaps between gates show that the outer oxide andAu/W wrap-gate layers have been completely removed. The effective removal of the Au/W isfurther confirmed by the absence of any current leakage between adjacent wrap-gate segments; theremoval of the outer oxide is therefore also confirmed as its removal is pre-requisite to etching thewrap-gate metallization. A 600 nm layer of polymethylmethacrylate(PMMA) EBL resist was usedfor the second layer to define contacts to the nanowire source, drain and gates. The thick resistlayer is needed to ensure continuity of the deposited metal across the wrap-gate segments. Fulldetails of the device fabrication are given in the Supporting Information.Electrical characterization was performed at a temperature T =
77 K to reduce drift andhysteresis due to charge trapping at the Al O /InAs interface. The source-drain current I sd wasmeasured using low frequency a.c. lock-in techniques with an excitation voltage V sd =
30 mV at73 Hz. All gates were initially tested using a Keithley K2400 voltage source to ensure the leakagecurrent remained at an acceptable level ( <
100 pA) over their entire working range. The SRS830digital to analog converter (DAC) voltage outputs were used thereafter to supply either the voltage V g , n to the n th wrap-gate segment or the voltage V bg to the n + -Si back-gate. Low pass RCR filtersand ground isolating circuits were used on each DAC output to prevent ground loops and minimizegate noise in the measurements. Two SRS830 lock-ins were used to simultaneously measure eachrespective transistor’s drain current for the common-source nanowire transistor pair.We begin by characterising the two-gate device. In Fig. 2 we plot I sd versus (a) V g , and (b) V g , ; in each case the other wrap-gate is grounded and the measurement is repeated at back-gatevoltages V bg = + + V bg = V th = −
247 mV and −
237 mV, respectively. We usethe standard approach to obtain V th as the voltage where a fit to the linear region of I sd versus V bg on a linear-linear graph intersects the V bg axis. The sub-threshold slopes are only 2 − × thetheoretical maximum of 15 . T =
77 K. The room temperature scaled sub-thresholdslopes, at 117 and 168 mV/dec, are 50 − this5igure 2: Source-drain current I sd vs wrap-gate voltage: (a) V g , on Gate 1, and (b) V g , on Gate 2for the device in Fig. 1(b) for back-gate voltages V bg = +
10 V (dotted red line), + V g where I sd →
0) for Gate 1 is much lessaffected by the change in V bg indicating that this wrap-gate better screens to enclosed nanowiresegment from the back-gate field, as discussed in detail in the text.6ikely reflects the reduced interface charge trapping at T =
77 K however. The less negative V th that we observe here (c.f. −
670 mV in Ref. ) is also consistent with reduced interface trapping.We have also developed a method for electrically characterising the quality of the wrap-gatestructures based on how the wrap-gate characteristics evolve with back-gate voltage. Nanoscalestructures are rarely ideal because microscopic imperfections are at a scale comparable to the over-all device structure. This is evident for the wrap-gates in Figs. 1(b-d), where holes or ‘mouse-bites’in the gate metallization occur due to the combined effect of granular deposition during the sput-tering process and etchant attack during processing. The question this raises is: Are the defectsjust cosmetic or do they also affect performance? This motivated our method for assessing themelectrically; it relies on measuring how the back-gate influences the I sd versus V g , n characteristicsfor a given wrap-gate segment. At V g , n > V th , the wrap-gated segment is strongly conducting and V bg has significant influence on I sd by gating the nanowire segments external to the wrap-gate seg-ments. We see this behavior for Gates 1 and 2 in Fig. 2. In contrast, at V g , n < V th , the wrap-gatedsegment dominates the device resistance and changes in V bg should only have a significant effecton I sd if the wrap-gate segment imperfectly screens the nanowire it encloses. Imperfect screeningmost likely arises from holes that fully penetrate the wrap-gate metallization rather than, for ex-ample, complete removal of the underside of the wrap-gate where the device sits on the substrate.The reason why we are confident that the underside of the wrap-gate remains intact is that this iswhere the etchant has most restricted access to attack the metallization. Consistent with this, in ourearlier work we saw significant beveling of the wrap-gate ends for the shortest segments (i.e.,length of segment at top side of wrap-gate is much longer than on the bottom side). We observe nobeveled ends in the devices we report here because the wrap-gate etch time is short in this process;as such we expect the underside of the wrap-gates to remain intact aside from holes caused by theetchant attacking the wrap-gate from the side. Indeed, now that we remove the outer oxide as thefirst step we expect this substrate protection to be more effective. In the earlier work, removalof the outer oxide after the first EBL stage could leave the wrap-gate suspended by the PMMA,enabling attack from below by the Au and W etchants. Now that we remove the entire outer oxide7rst, the nanowire drops down onto the substrate before any EBL, bringing the wrap-gate metalinto intimate contact with the HfO2 substrate oxide, where it is better protected during the Au andW etch steps. Were the Au/W wrap-gate to lose its conformal morphology at the underside inthis process, we would expect a strong back-gate effect on all wrap-gates in all devices; this is notobserved in our data.Returning our focus specifically to the device in Fig. 1(b), one might expect both wrap-gates toshow significant V bg dependence in the sub-threshold regime considering their appearance. How-ever, Gate 1 is substantially less V bg -dependent, demonstrating two important aspects regardingwrap-gates in nanowire transistors. The first is that the wrap-gate structures can tolerate significantdefects yet still effectively screen the nanowire from external electric fields. The second is that thevisual appearance of a wrap-gate is a poor indicator for its electrical performance. We chose the de-vice in Fig. 1(b) specifically to highlight these points – in this case we have a device that we mightdiscard given its appearance, yet half of the gates work just as well as they would in a device whereno wrap-gate defects are evident. We find similar behavior for our three-gate device (Fig. 1(c)); thecorresponding data is shown in Supplementary Fig. 1. We suspect this defect-tolerance arises fromthe dual-metal recipe used. The wrap-gate metallization has a thickness of 28 nm and while thereare obvious defects in the wrap-gate surface, these may not extend through the entire metallizationthickness. An interesting engineering challenge would be to model the extent to which a wrap-gatecan tolerate defects, e.g., holes, oxidation, etc., without losing its effectiveness for screening thenanowire from external electric fields. As a final comment regarding the ‘mouse-bites’ in our wrap-gate metallization; the path to minimizing them in future devices would be to improve the qualityof the sputtered gate metal. We used Au here for its high conductivity and robustness against oxi-dation, but it tends to produce sputtered films with a large grain-size. This in turn leads to largervoids between grains, and is likely the root cause of the ‘mouse-bites’. A change in the metal usedfor this outer layer could be beneficial; candidates would include Au-Pd alloy, Pt, Cr or Ir. In anycase, this would require finding a suitable etchant to replace the KI/I etch used for Au, which maybe challenging. Cr and Ir are easier to wet etch, but also more susceptible to oxidation, both during8puttering and after fabrication, reducing device lifetime. Careful optimization of the sputteringsystem may also enable reduced grain size.Figure 3: Source-drain current I sd versus (a) V g , , (b) V g , , (c) V g , and (c) V g , at V bg = + + −
498 mV, 32 mV/dec; (b) −
501 mV, 34 mV/dec; (c) −
486 mV, 25 mV/dec; (d) −
420 mV, 43 mV/dec.Figure 3 shows the individual wrap-gate characteristics for our four-gate device (Fig. 1(d)).The four gates are remarkably similar in performance, with a median threshold voltage V th = − ±
40 mV and average sub-threshold slope of 34 ± V bg -dependence in the sub-threshold region, demonstrating that high-quality wrap-gatescan still be achieved despite the short segment length ∼
400 nm and spacing between wrap-gates9
200 nm. We emphasize that the four-gate structure entails the same number of process stepsas the two-gate structures, a substantial improvement on the vertical orientation where twice thenumber of process steps would be required. The shorter gates in the four-gate device gave lower V th values than those in the two-gate device. This trend was observed over a range of devices; thedata is presented in the Supporting Information. The maximum number of wrap-gates we haveattempted is four, but with some optimization larger numbers of independent wrap-gates should bepossible using the same process. The ultimate limit will be set by the ratio of the EBL defined etchresolution to the nanowire length.While the wrap-gates effectively screen the back-gate in this device, one additional concernthat arises for larger numbers of wrap-gate segments is cross-talk between adjacent back-gate seg-ments due to the short wrap-gate segment length and relatively small separation between segments.A cross-talk experiment was conducted for the four-gate device (Fig. 1(d)) with the followingmethodology. Starting with Gate 1, we obtain the gate characteristic first with V g , = V g , = V g , = V g , n = − . D V th . This process is repeated for each of the three remaining wrap-gates. In the instance wherecross-talk between wrap-gates is significant, we would expect the D V th for nearest neighbours tobe much greater than for next- or next-next-nearest neighbours. The extracted D V th values rangefrom −
30 to −
76 mV (full table of values in Supplementary Fig. 2) and show that the cross-talkis insignificant. The averaged shift for the nearest neighbours is − . − . V th variation of 4 mV anda maximum variation of 16 mV. The small run-to-run V th variation strongly supports the validity ofthe D V th values found in our cross-talk analysis. Cross-talk is thus not a problem at the gate lengthsand separations used in our four-gate device. However, it should become an issue at much smaller10cales; we encourage theoretical work or simulations to determine the relevant length scales wherethis would occur.Table 1: Truth-table demonstrating logic AND operation with Gates 1 and 2 as inputs and I sd asoutput with V g , = V g , = / I sd =
100 nA. The corresponding operating points are shown by the arrows at the topof Fig. 4. Gate 1 Gate 2 Output0 ( V g , n = − . V g , n = − . I sd = V g , n = − . V g , n = I sd =
11 nA)1 ( V g , n = V g , n = − . I sd =
20 nA)1 ( V g , n = V g , n = I sd =
658 nA)To better assess the balance, temporal stability and control of these gates, we performed anin-depth time-series study of how the device behaves as various combinations of gates are swepttogether. The four panels in Fig. 4(a) show the voltage program for the four wrap-gates versus time t . Traces are color-coded to indicate whether four (black), three (blue), two (red) or one (green)wrap-gate segment was being swept with the remaining segments held fixed. When a wrap-gatesegment was swept, it was taken linearly between its ‘on’-state ( V g , n = V g , n = − . ≤ V th , n ) or vice versa. Figure 4(b) shows the expected I sd based on a simpleseries resistance model consisting of five contributions: four variable contributions R n ( V g , n ) forthe wrap-gates and a fixed contribution R used to match I sd between experiment and simulationat V g , = V g , = V g , = V g , = R n ( V g , n ) was assumed as being linear in V g , n . Figure 4(c) shows the measured I sd obtained forthe voltage program in Fig. 4(a). While the general features bear strong similarity to the simplesimulation in Fig. 4(b), there are differences in both the minima at lower t and maxima at higher t in Fig. 4(c) that point to differences in the I sd versus V g , n characteristics between the four wrap-gates. In this particular instance, Gate 4 has a higher R n ( V g , n ) than Gates 1-3. To demonstrate this,in Fig. 4(d) we repeat the simulation with R ( V g , ) = R ( V g , ) = R ( V g , ) = . × R ( V g , ) ;this is the only linear combination of segment resistances that correctly reproduces the measureddata. The imbalance is likely due to a slightly different gate capacitance for Gate 4, potentially11igure 4: (a) The four panels show the applied gate biases V g , (top), V g , , V g , and V g , (bottom)vs time t . The traces are color-coded to indicate that four (black), three (blue), two (red) or one(green) wrap-gate is being swept with the remaining wrap-gates held fixed. (b) Simulated source-drain current I sd vs t assuming the four wrap-gate segments have identical properties. (c) Measured I sd vs t for the device in Fig. 1(d). (d) Simulated I sd vs t assuming the segment inside Gate 4 has1 .
016 times the resistance of the other three segments (see text for details). The arrows at topindicate the operating points for the logic AND demonstration in Table 1.12rising from roughness in the wrap-gate metallization or slight etching of the inner wrap-gate insu-lator due to the outer-oxide buffered HF etch leaking through pores in the wrap-gate metallization.We expect variations between wrap-gate segments to increase as segment length is decreased orif there are imperfections in the gate metallization. Improvements in gate metallization mightbe obtained by moving to more openly-distributed, patterned nanowire arrays, which will limitshadowing effects whilst depositing the gate metal. A focused optimisation of the processes fordeposition of the wrap-gate insulator (ALD) and gate metallization (dc sputtering), as carried outfor vertical nanowire transistor arrays might also help improve the quality and reproducibilityof horizontal wrap-gate nanowire transistors. The latter would focus on reducing the grain sizefor the gate metallization, as discussed earlier. The data in Fig. 4 suggests it might also be pos-sible to compensate by measuring the imbalance and scaling the off-state operating voltages V g , n to tune the device back into balance. We note that the data in Fig. 4(c) demonstrates significantpotential for doing logic with these devices. For example, if we leave Gates 3 and 4 at ground,we can demonstrate traditional two-input logic operations using the remaining Gates 1 and 2. Ta-ble 1 presents a truth-table demonstrating a two-input logic AND gate for Gates 1 and 2 using V ( g , n ) = . V ( g , n ) = − . I sd as the output with I sd <<
100 nA as ‘0’and I sd >>
100 nA as ‘1’. The four corresponding operating points are indicated by the arrowsat the top of Fig. 4. Devices with more than two wrap-gate segments might provide an interest-ing alternative route to multi-input nanowire logic circuits, particularly if incorporated with theability to make multiple contacts at different points along the sequence of wrap-gate segments (seebelow). Note that these devices can be operated more rapidly than in Fig. 4; we deliberately ran ourdevice slowly here to minimise noise/hysteresis arising from the unoptimized wrap-gate structure.Vertical wrap-gate transistors featuring similar materials are capable of GHz operation with properdesign/optimization. Finally, in Fig. 5(a) we present a common-source wrap-gate nanowire transistor pair to demon-strate the full versatility of our fabrication method and potential for making more complex nanowiredevice architectures. This device was produced using exactly the same process as all three devices13igure 5: (a) Scanning electron micrograph of a common-source wrap-gate nanowire transistorpair made using the same process used for the multiple wrap-gate structures in Fig. 1. The scalebar represents 500 nm. (b/c) The measured source-drain current (b) I Asd for Transistor A and (c) I Bsd for Transistor B versus V g , A and V g , B with V bg = I Asd through Transistor A and I Bsd through Transis-tor B were measured simultaneously, and are plotted versus the wrap-gate voltages V g , A and V g , B ,respectively, in Figs. 5(b/c). In each case, the solid black line demonstrates pinch-off in the tran-sistor due to electrostatic depletion of the nanowire segment inside that transistor’s wrap-gate. Incontrast, if we hold a given transistor’s wrap-gate fixed and sweep the other transistor’s wrap-gatewe see a small rise in I sd . The bias on the unswept gate was held at zero for the data in Figs. 5(b/c).This rise is not a cross-talk effect; it occurs because the two transistors form a parallel circuit toground. The total current flowing from the source is set by the total parallel resistance, but theshare of that current flowing through Transistor A will rise if the resistance of Transistor B risesdue to gating on that side. Note that wihout any significant effort having been devoted to optimiz-ing their balance, the two transistors are a reasonably well matched pair: the threshold voltagesdiffer by less than 16% and the sub-threshold slopes are identical.In conclusion, we have demonstrated a method for making horizontal wrap-gate nanowire tran-sistors with up to four independently controllable wrap-gated segments. A key advantage of thisorientation, and our approach, is that the addition of further gates does not require the addition ofany extra steps to the device fabrication process. This is in stark contrast to the vertical orientation,where each additional gate involves the repetition of a significant subset of the fabrication steps. We have shown that our multiple wrap-gate transistors can be made with gates that have very sim-ilar characteristics without extensive optimization of materials or processing. There is little cross-talk between adjacent wrap-gate segments, although in some cases, imperfections in the wrap-gatesmean they imperfectly screen external electric fields, e.g., those generated by a back-gate. We havealso shown that the same basic process can be used to make simple multiple transistor circuits suchas a common-source nanowire transistor pair. As such the method has significant potential formaking more complex nanowire device/circuit architectures, and ultimately, towards couplinghorizontal wrap-gate nanowire transistors with vertical wrap-gate nanowire transistors to achieve3D-integrated nanowire network architectures for future electronic applications. upporting Information. Full details on device fabrication, data for the three-gate device inFig. 1(c), D V th values for the cross-talk experiment on the device in Fig. 1(d), details of the sim-ulation model used for Figs. 4(b/d) and the relationship between V th and gate length are included.This material is available free of charge via the Internet at http://pubs.acs.org. Corresponding author. *E-mail: [email protected]
Acknowledgement
This work was funded by the Australian Research Council (ARC), Nanometer Structure Consor-tium at Lund University (nmC@LU), Swedish Research Council, Swedish Energy Agency (GrantNo. 38331-1) and Knut and Alice Wallenberg Foundation (KAW). APM acknowledges an ARCFuture Fellowship (FT0990285). AMB acknowledges support from the Australian Nanotechnol-ogy Network Overseas Travel Fellowship scheme. This work was performed in part using the NSWnode of the Australian National Fabrication Facility (ANFF). We thank Scott Liles for assistancewith the cross-talk data analysis.
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