Modeling networks of probabilistic memristors in SPICE
RRADIOENGINEERING, VOL. , NO. , ... 1
Modeling networks of probabilistic memristors in SPICE
Vincent J. DOWLING , Valeriy A. SLIPKO , Yuriy V. PERSHIN Department of Physics and Astronomy, University of South Carolina, Columbia, SC 29208 USA Institute of Physics, Opole University, Opole 45-052, [email protected]
Submitted ... / Accepted ...
Abstract.
Efficient simulation of probabilistic memristorsand their networks requires novel modeling approaches. Onemajor departure from the conventional memristor modelingis based on a master equation for the occupation probabilitiesof network states [arXiv:2003.11011 (2020)]. In the presentarticle, we show how to implement such master equations inSPICE – a general-purpose circuit simulation program. Inthe case studies, we simulate the dynamics of ac-driven prob-abilistic binary and multi-state memristors, and dc-drivennetworks of probabilistic binary and multi-state memristors.Our SPICE results are in perfect agreement with known an-alytical solutions. Examples of LTspice codes are included.
Keywords
Memristors, SPICE, networks, probabilistic computing
1. Introduction
SPICE simulation [1,2] is a powerful tool in the hands ofan electrical engineer. In the last decade significant progresshas been made in developing SPICE models of memristivedevices [3–14], as well as memcapacitive and meminduc-tive elements [9, 15]. The common feature of these previousapproaches is the use of differential equations to describethe deterministic evolution of internal state(s) of memorydevices [16, 17].However, there is a strong indication that the deter-ministic description fails when applied at least to certainrealizations of resistors with memory [18–20]. In particular,it was shown experimentally that when a constant voltageis applied to such devices, their state changes in a step-likefashion at random times. In one group of devices, a Pois-son distribution of switching times was observed [18–20].Furthermore, another group of devices is characterized bya log-normal distribution [21]. Several theoretical modelswere pushed forward to account for the randmoness in thememristor switching [22, 23]. The dynamics of networks with discrete-state memris-tors can be imagined as a sequence of transitions betweennetwork states. Recently, we have introduced a master equa-tion approach for the occupation probabilities of the networkstates [24] that can be used to describe circuits that includebinary and multi-state memristors, resistors, voltage and cur-rent sources, and possibly some other components . Inthis previous work [24], the solution of the master equationwas found analytically for networks of N in-series/in-parallelconnected binary memristors driven by a constant voltagesource. It has been demonstrated in Ref. [24] that the masterequation solution allows to calculate many quantities of in-terest including various mean switching times, mean current,resistance, etc.There are two major advantages of the master equa-tion compared to stochastic/Monte Carlo simulations: i ) inprinciple, the master equation can be solved analytically (seeRef. [24] for examples), and ii ) using the master equation,many network characteristics can be found in a single calcula-tion without the need for averaging. In the case of symmetriesin the circuit, the additional benefit of the master equation isits compactness. This means that a single degree of freedomis required to describe equivalent circuit configurations.In this article (which is our second work in a series ded-icated to probabilistic memristive networks), we introducea methodology to simulate the probabilistic memristive net-works in SPICE. The paper is organized as follows. We startwith an overview of the master equation in relation to bi-nary and multi-state probabilistic memristor networks. Thisis followed by a description of the SPICE implementationscheme supplemented by several examples. In particular, weconsider individual probabilistic binary and tri-state mem-ristors driven by ac-voltage, and dc-driven networks thereof.LTspice codes for some of our examples are provided in theAppendix.The approach presented in this work is relatively gen-eral and can be used to model networks combining resistors,probabilistic memristors, constant and time-dependent volt-age and current sources. The application of the master equa-tion to probabilistic memristor networks is a paradigm changein the probabilistic memristor modeling, and its SPICE im- A generalized approach is needed for circuits combining probabilistic memristors and capacitors/inductors.
DOI: 10.13164/re.2020.0001 CIRCUITS a r X i v : . [ c s . ET ] S e p V. J. DOWLING, V. A. SLIPKO, Y. V. PERSHIN, MODELING NETWORKS OF PROBABILISTIC MEMRISTORS IN SPICE . . . plementation makes it affordable to students and researchersworking in the field.
2. Probabilistic memristors and mas-ter equation
Binary memristors are characterized by two resistancestates, R on and R of f (with R on < R of f ) corresponding tothe states 1 (on) and 0 (off). The switching between thesestates is defined by a probabilistic law with voltage-dependentswitching rates (inverses of the mean switching times) givenby [18–20] γ → ( V ) = (cid:40) (cid:16) τ e − V / V (cid:17) − , V >
00 otherwise , (1) γ → ( V ) = (cid:40) (cid:16) τ e −| V |/ V (cid:17) − , V <
00 otherwise . (2)Here, τ ( ) and V ( ) are constants and V is the voltageacross the device. For a memristor in state 0, the proba-bility to switch to state 1 within small time interval ∆ t is γ → ( V ) ∆ t . The probability of swithching from 1 to 0 isdefined similarly.The master equation is written with regard to the occu-pation probabilities of network states. The network state isdefined by a specific combination of the off- and on-states ofmemristors. For a system containing N binary memristors,there exists 2 N such states. The network evolution consistsof a chain of consecutive switchings of memristors (simul-taneous switchings can be neglected). On average, such aprocess is described by the master equation with formd p Θ ( t ) d t = N (cid:213) m = (cid:16) γ m Θ m p Θ m ( t ) − γ m Θ p Θ ( t ) (cid:17) , (3)where p Θ ( t ) is the occupation probability of state Θ , Θ m isthe network state obtained from Θ by flipping the state of m -th memristor, γ m Θ is the switching rate for m -th memristorin the configuration Θ , and γ m Θ m is defined similarly. Theswitching rate γ m Θ equals the switching probability (Eqs. (1)or (2)) for m -th memristor in the state Θ .To demonstrate Eq. (3), consider two in-series con-nected identical memristors subjected to a voltage waveform V a ( t ) . There are 4 possible network states that we denote as00, 01, 10, and 11. In 00, both memristors are in the off-state,in 01, the first is in the off-, while the second is in the on-state,etc. Eq. (3) has the form (a) (b) Fig. 1.
Transition scheme for (a) single three-state memristor,and (b) network of two three-state memristors. d p ( t ) d t = γ p + γ p − γ p , (4)d p ( t ) d t = γ p + γ p − γ p − γ p , (5)d p ( t ) d t = γ p + γ p − γ p − γ p , (6)d p ( t ) d t = γ p + γ p − γ p . (7)The similarity of memristors is taken into account by re-lations like γ = γ , γ = γ , p ( t ) = p ( t ) , etc.Therefore, Eqs. (5) and (6) are the same and the total numberof equations that need to be solved reduces by one. In our no-tation, γ describes the switching rate from state 00 with theflipping of the 1-st memristor. The corresponding switchingrate is given by Eq. (1) with V = V a ( t )/
2, etc. Importantly,the computation of the switching rate involves the voltageacross the switching memristor in the given configuration atthe time moment t . It is assumed that in a K -state memristor the switchingbetween its boundary states ( R on and R of f ) occurs consec-utively through K − i , j , k , and so on, in the set Θ = ( . . . k ji ) denoting the states of the first memristor, thesecond one, and so on, in the network can have more than twovalues. Generally, this leads to the exponential growth of thenumber of network states and, correspondingly, the numberof independent equations for occupation probabilities p Θ ( t ) when N , the number of memristors, increases. Luckily, thenumber of nonzero switching rates γ , corresponding to thenonzero terms in the right hand side of the master equation(3) for a given network configuration Θ , does not typicallygrow as fast.In order to account for potential change in parameter val-ues between resistance states, Eq. (1) and Eq. (2) are modified ADIOENGINEERING, VOL. , NO. , ... 3 (a) V a ( t )M GND (b)
B1 B2C11 C21V1 R21k10kR1 R31kB3p1p0 VI V a V a V a .param tau01=3E5 V01=.05.tran 0 .1 0.05 10E-7.FUNC gm(x,y,z){1/(x*exp(-z/y))}.param tau10=3E5 V10=.05 and More\Memristor probabilistic______________________________\article 2 SPICE\codes_final\N1Switchin (c) - 1 . 0 - 0 . 5 0 . 0 0 . 5 1 . 0- 1 . 0- 0 . 50 . 00 . 51 . 0 Mean current (mA)
V o l t a g e ( V )
Fig. 2.
Ac-driven probabilistic binary memristor: (a) simulated circuit, (b) schematics of SPICE model, and (c) example of current-voltage curvesfound with SPICE simulations. The listing of SPICE model is given in Table A.1. (a) V a M M GND (b)
B1 B2 B3 B4 B51C1 1C2 1C3 1C4 1C5 B6 1C6R110kR210k R61kR710k R111kR121k R161kR171k R211kR221kR310kR410kR510k R810kR910kR1010k R1310kR1410kR1510k R181kR1910kR2010k R231kR241kR2510k B7 R311kR261kR271kR281kR291kR301kV15 B8 1C7p0 p1 p2 p3 p4 p5Va Va VaVa V a Va VIVtVa .tran 0 .002 0 1E-7.func gm(x,y,z){1/(x*exp(-z/y))}.param tau01=3E5 V01=.05.param tau10=3E5 V10=.05 tors and More\Memristor probabilistic______________________________\article 2 SPICE\codes_final\N5Swit
Fig. 3.
Dc-driven network of five probabilistic binary memristors: (a) simulated circuit, (b) schematics of SPICE model. to γ i → j ( V ) = (cid:40) (cid:16) τ ij e − V / V ij (cid:17) − , V > , j = i +
10 otherwise , (8) γ j → i ( V ) = (cid:40) (cid:16) τ ji e −| V |/ V ji (cid:17) − , V < , j = i +
10 otherwise . (9)with τ ij ( ji ) and V ij ( ji ) being the constant values describing theresistance switching from i ( j ) -th to j ( i ) -th memristor state,and i changes from 0 to K − →
3. SPICE modeling approach
Let M be the number of non-equivalent equations forthe occupation probabilites (like the set of Eqs. (4), (5), and(7)). The supremum of M is K N , where K is the numberof memristor states, and N is the number of memristors inthe network. However, in practical cases M can be muchsmaller than K N . For instance, if there are N binary ( K = M = K + M copies of the network with memristors innon-equivalent combinations of states are utilized. These V. J. DOWLING, V. A. SLIPKO, Y. V. PERSHIN, MODELING NETWORKS OF PROBABILISTIC MEMRISTORS IN SPICE . . . circuits (shown in the bottom row in Figs. 2, 3, 5 and 6) areconnected to the input voltage. The voltages across mem-ristors in these circuits are utilized to calculate the transitionrates between the states.To calculate the mean current, we use a voltage-controlled current source connected by a resistor to ground toprovide a current path. For instance, in the case of in-seriesconnected binary memristors, the current source output isdefined by (cid:104) I (cid:105) ( t ) ≡ N (cid:213) m = (cid:18) Nm (cid:19) I m ( t ) p m ( t ) , (10)where the number of states with the same number of mem-ristors in the on-state is taken into account by the binomialcoefficients (cid:18) Nm (cid:19) , and I m ( t ) is the current through the net-work with m memristors in the on-state. The switching time(or any other integral) can be evaluated numerically witha capacitor-voltage-controlled current source. Examples ofsuch calculations can be found below.
4. Simulation examples
In this simulation, a single binary memristor driven byan ac source is considered as seen in Fig. 2(a). Fig. 2(b)contains the schematic for the SPICE implementation andthe corresponding SPICE code can be found in appendixA.1. The memristor has two possible states, R on and R of f ,with resistance values of 1k and 10k Ohms respectively. Weused the model parameter values τ = τ = · s and V = V = .
05 V. The ac source, V a ( t ) , has a peak voltageof 1V and is driven at various frequencies. The memristoris initialized in the off-state and will continue switchingbetween the resistance states until the simulation has ended.The current is calculated using B4 and R4 components inFig. 2(b). The current-voltage curves generated throughSPICE simulation can be seen in Fig. 2(c) and they showthe frequency behavior typical to deterministic memristivedevices [16, 17]. We verified that Fig. 2(b) SPICE modelreproduces some previous results found through Monte Carlosimulations [24]. For this next simulation, we consider a network of bi-nary memristors connected in-series as shown in Fig. 3(a).The network is composed of five memristors driven by a dcsource with a voltage of 5V. Fig. 3(b) contains the schematicfor the SPICE implementation. Each memristor is identicalto one another, meaning the model parameters and the twostates are equivalent from memristor to memristor. The mem-ristors have two possible states, R on and R of f , with resistance values of 1k and 10k Ohms respectively. We used the modelparameter values τ = τ = · s and V = V = .
05 V.
Voltage ( m V)Mean current (mA)
T i m e ( m s ) I ( R 3 1 ) V ( V t ) Fig. 4.
Current as a function of time (black solid line), and calcu-lation of the network switching time (red dashed line) inthe dc-driven network of five probabilistic binary mem-ristors.
Each memristor starts in the off-state and as time progresseseach will switch to the on-state. When a memristor switchesto the on-state, the drop in resistance causes an increase in thevoltage across the off-state memristors increasing the proba-bility of switching for the off-state memristor.According to the analytical theory [24], the networkmean switching time can be calculated as (cid:104) T N (cid:105) = N − (cid:213) j = ( N − j ) γ j . (11)For the parameters of simulations in Figs. 3 and 4, the aboveequation gives (cid:104) T (cid:105) = µ s. Numerically, the same quan-tity can be evaluated using the following integral ∞ ∫ t γ p ( t ) d t . (12)Technically, the integration is done by the components B8 and C7 in Fig. 3, so that the averaged switching time corre-sponds to the saturation limit of V ( Vt ) curve in Fig. 4. Weemphasize that the analytical and numerical (SPICE) valuesfor (cid:104) T (cid:105) are in full agreement. The first multi-state simulation considered is a singletri-state memristor driven by an ac source. The ac source hasa peak voltage of 1.5 V and is driven at various frequencies.Fig. 5(a) contains the schematic for the SPICE implemen-tation and the corresponding SPICE code can be found inappendix A.2. The memristor now has three possible states,off-, intermediate, and on-state. To account for the addedresistance state, a new copy of the memristor network is nec-essarily added to the SPICE implementation. These stateshave resistance values of 10k, 3k, and 1k Ohm respectively.The model parameters, τ ij and V ij , are as specified in theSPICE model schematics (Fig 5(a)). The memristor is ini-tialized in the off-state and will continue switching between ADIOENGINEERING, VOL. , NO. , ... 5 (a)
R110k R23k B4R31k R41kC11 C21 C31
SINE(0 1.5 200)
V1 B1 B2 B3p0 p1 p2 VI V a V a V a V a .tran 0 .1 .09 1E-7.func gm(x,y,z){1/(x*exp(-z/y))}.param tau01=3E5 V01=.05.param tau12=3E5 V12=.07.param tau10=3E5 V10=.05.param tau21=3E5 V21=.07 d More\Memristor probabilistic______________________________\article 2 SPICE\codes_final\N1_3Step_ful (b) - 1 . 5 - 1 . 0 - 0 . 5 0 . 0 0 . 5 1 . 0 1 . 5- 1 . 5- 1 . 0- 0 . 50 . 00 . 51 . 01 . 5 Mean current (mA)
V o l t a g e ( V )
Fig. 5.
Ac-driven probabilistic three-state memristor: (a) schematics of SPICE model, and (c) example of current-voltage curves found withSPICE simulations. The listing of SPICE model is given in Table A.2. The simulated circuit is the same as in Fig. 2(a) with the differenceof different memristor type used. (a) V a M M GND (b)
R110k R33k B4R51k R131kC11 C21 C31
V1B1 B2 B3R210k R410k R610k C41 C51 C61B5 B6 B7R73k R91k R111kR83k R103k R121kp01 p02 VIVa V a V a V a p11 p12 p22 V a V a V a p00 .tran 0 .002 0 1E-7.func gm(x,y,z){1/(x*exp(-z/y))}.param tau01=3E5 V01=.05.param tau12=3E5 V12=.07.param tau10=3E5 V10=.05.param tau21=3E5 V21=.07 d More\Memristor probabilistic______________________________\article 2 SPICE\codes_final\N2_3Step_ful (c) Probability
T i m e ( s )
V ( p 0 0 ) V ( p 0 1 ) V ( p 0 2 ) V ( p 1 1 ) V ( p 1 2 ) V ( p 2 2 ) (d)
Mean current (mA)
T i m e ( s )
Fig. 6.
Dc-driven network of two three-state memristors: (a) simulated circuit, (b) schematics of SPICE model, (c) time-evolution of occupationprobabilities, and (d) current as a function of time.
V. J. DOWLING, V. A. SLIPKO, Y. V. PERSHIN, MODELING NETWORKS OF PROBABILISTIC MEMRISTORS IN SPICE . . . the resistance states until the simulation has ended. Fig. 5(b)shows the current-voltage curves generated by this SPICEsimulation.This next simulation is a network of two tri-state identi-cal memristors driven by a 1.5V dc source shown in Fig. 6(a).The resistance states and model parameters are identical tothe memristor used in the previous configuration. Fig. 6(b),the SPICE schematic used for this simulation is shown. TheSPICE model is designed according to the transition schemein Fig. 1(b). The memristors are initialized in the off-stateand will switch to the intermediate state before switching tothe on-state during the simulation. The evolution of resis-tance state probabilities for this network is shown in Fig. 6(c)and the mean current as a function of time for this SPICEsimulation is shown in Fig. 6(d). The mean current increasesin two steps because of the different time scales for the 0 → →
5. Summary
In summary, the use of the master equation in proba-bilistic circuit modeling [24] offers significant benefits com-pared to the routine Monte Carlo/stochastic simulations.Many circuit characteristics can be found on average in asingle run and the master equation can be, in principle,solved analytically, with several analytical solutions alreadyknown [24]. In this work, we have shown how to implementthe master equation in SPICE. Our examples include simula-tions of binary and multi-state probabilistic memristors andtheir circuits subjected to ac- and dc-voltages. We expect thatour approach will be useful to a broad range of researchersworking in the area of emerging memory devices.
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Appendix A: SPICE code examples
B1 0 p0 I=-gm(tau01,V01,V(Va))*V(p0)*u(V(Va))+gm(tau10,V10,-V(Va))*V(p1)*u(-V(Va))B2 0 p1 I=gm(tau01,V01,V(Va))*V(p0)**u(V(Va))-gm(tau10,V10,-V(Va))*V(p1)**u(-V(Va))C1 p0 0 1 IC=1C2 p1 0 1 IC=.0R2 Va 0 1kR1 Va 0 10kR3 VI 0 1kB3 0 VI I=I(R1)*V(p0)+I(R2)*V(p1)V1 Va 0 SINE(0 1 200 0 0 0 0).FUNC gm(x,y,z)1/(x*exp(-z/y)).param tau01=3E5 V01=.05.param tau10=3E5 V10=.05.tran 0 .1 0.05 10E-7.backanno.end
Table A.1.
SPICE code for ac-driven probabilistic binary memristor.
B1 0 p0 I=(-gm(tau01,V01,V(Va))*V(p0))*u(V(Va))+(gm(tau10,V10,-V(Va))*V(p1))*u(-V(Va))B2 0 p1 I=(gm(tau01,V01,V(Va))*V(p0)-gm(tau12,V12,V(Va))*V(p1))*u(V(Va))+(gm(tau21,V21,-V(Va))*V(p2)-gm(tau10,V10,-V(Va))*V(p1))*u(-V(Va))B3 0 p2 I=(gm(tau12,V12,V(Va))*V(p1))*u(V(Va))+(-gm(tau21,V21,-V(Va))*V(p2))*u(-V(Va))R1 Va 0 10kR2 Va 0 3kR3 Va 0 1kR4 VI 0 1kC1 p0 0 1 IC=1C2 p1 0 1 IC=0C3 p2 0 1 IC=0B4 0 VI I=I(R1)*V(p0)+I(R2)*V(p1)+I(R3)*V(p2)V1 Va 0 SINE(0 1.5 200).func gm(x,y,z)1/(x*exp(-z/y)).param tau01=3E5 V01=.05.param tau12=3E5 V12=.07.param tau10=3E5 V10=.05.param tau21=3E5 V21=.07.tran 0 .1 .09 1E-7
V. J. DOWLING, V. A. SLIPKO, Y. V. PERSHIN, MODELING NETWORKS OF PROBABILISTIC MEMRISTORS IN SPICE . . . .backanno.end