MoS 2 Dual-gate Transistors with Electrostatically Doped Contacts
Fuyou Liao, Yaocheng Sheng, Zhongxun Guo, Hongwei Tang, Yin Wang, Lingyi Zong, Xinyu Chen, Antoine Riaud, Jiahe Zhu, Yufeng Xie, Lin Chen, Hao Zhu, Qingqing Sun, Peng Zhou, Xiangwei Jiang, Jing Wan, Wenzhong Bao, David Wei Zhang
2 R e v i e w A r t i c l e / R e s ea r c h A r t i c l e P l ea s e c hoo s e one Fuyou Liao § , Yaocheng Sheng § , Zhongxun Guo , Hongwei Tang , Yin Wang , Lingyi Zong , Xinyu Chen , Antoine Riaud , Jiahe Zhu , Yufeng Xie , Lin Chen , Hao Zhu , Qingqing Sun , Peng Zhou , Xiangwei Jiang , Jing Wan ( ), Wenzhong Bao ( ), David Wei Zhang Two-dimensional (2D) transition metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS ) have been intensively investigated because of their exclusive physical properties for advanced electronics and optoelectronics. In the present work, we study the MoS transistor based on a novel tri-gate device architecture, with dual-gate (Dual-G) in the channel and the buried side-gate (Side-G) for the source/drain regions. All gates can be independently controlled without interference. For a MoS sheet with a thickness of 3.6 nm, the Schottky barrier (SB) and non-overlapped channel region can be effectively tuned by electrostatically doping the source/drain regions with Side-G. Thus, the extrinsic resistance can be effectively lowered, and a boost of the ON-state current can be achieved. Meanwhile, the channel control remains efficient under the Dual-G mode, with an ON-OFF current ratio of 3×10 and subthreshold swing of 83 mV/decade. The corresponding band diagram is also discussed to illustrate the device operation mechanism. This novel device structure opens up a new way toward fabrication of high-performance devices based on 2D-TMDs. MoS , dual-gate, tri-gate, field effect transistor, extrinsic resistance, electrostatic doping Address correspondence to Jing Wan, email: [email protected] ; Wenzhong Bao, email: [email protected] DP G ox D dI LdV WC V ≈
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ACS Nano , , 7707-7712. Figure 1 (a) Schematics of the MoS tri-gate transistor with electrical connections used to characterize the device. (b) AFM image of the MoS flake after transferring to the buried BG electrodes. The region indicated by a black dashed box will be filled by depositing contact electrode during the next fabrication step. (c) Height profile of the multilayer MoS . The height profile is measured along the red line in (b). (d) Optical image of the fabricated device (two FETs connected in series based on the same MoS flake). Figure 2 (a) Output characteristic curves of MoS Side-G FET with V Dual-G =+4 V. The inset shows an equivalent circuit model of the MoS tri-gate transistor. (b) Transfer characteristic curves of MoS Side-G FET obtained by sweeping the V Side-G from -4 to +4 V with a fixed bias of V D =0.1 V and V BG = V TG =0 V. (c) Output characteristic curves of MoS tri-gate FET for various applied V Dual-G with V Side-G =0 V. The inset shows an equivalent circuit model of the MoS tri-gate transistor with a low V SG . (d) Transfer characteristic curves of V BG , V TG and V Dual-G with V D =0.1 V and V Side-G =0 V at room temperature. (e) Output characteristic curves of MoS tri-gate FET for various applied V Dual-G with V Side-G =+4 V. The inset shows an equivalent circuit model of the MoS tri-gate transistor with a high V Side-G . (f) Transfer characteristic curves of V BG , V TG and V Dual-G with V D =0.1 V and V Side-G =+4 V at room temperature.
Figure 3 V Side-G dependent electrical measurement. Linear (a) and semi-log (b) plot of I D - V DG characteristic of the MoS tri-gate transistor under various applied V Side-G from 0 to +4 V at a step of 0.5 V. (c) I ON / I OFF and extracted values of SS as a function of V Side-G . (d) Extracted values of µ , µ and R ex as a function of V Side-G . Band-diagram of the device when applying low V Side-G (e) and high V Side-G (f) with V Dual-G > V TH . Figure 4
The electrical characteristic of MoS tri-gate FET with V Side-G =+4 V. (a) 2D contour plot of I D as a function of V TG and V BG at constant drain voltage V D =0.1 V. (b) A simplified capacitance model of the tri-gate FETs. (c) Linear plots of BG transfer characteristics with TG voltage ranging from -4 to +4 V. The step of gate voltage change is 1 V. The dashed lines indicate changes in the slope of d I D /d V TG . (d) V TH and µ (extracted from BG transfer curves (c)) as a function of TG bias. Electronic Supplementary Material
Fuyou Liao § , Yaocheng Sheng § , Zhongxun Guo , Hongwei Tang , Yin Wang , Lingyi Zong , Xinyu Chen , Antoine Riaud , Jiahe Zhu , Yufeng Xie , Lin Chen , Hao Zhu , Qingqing Sun , Peng Zhou , Xiangwei Jiang , Jing Wan ( ), Wenzhong Bao ( ), David Wei Zhang Section 1
Figure S1
Photograph (a) and schematic diagram (b) of the customer designed micro-aligner.
Figure S2 (a-i) Fabrication process flow of the tri-gated MoS FET.
Address correspondence to Jing Wan, email: [email protected] ; Wenzhong Bao, email: [email protected]
Figure S4
Transfer characteristics of MoS tri-gate FETs with varied V Side-G values. The thickness of the MoS channel for each panel is 1.3 nm (a), 4 nm (b) and 5 nm (c). µ µ µ µ Section 2
Rational function fitting method
Figure S7
Schematic of equivalent circuit model of the tri-gate MoS FET with a fixed V Side-G . As the simplified equivalent circuit model shown in Fig. S7, Dtotal ch ex D
VR R R I (S1) where total R is the total resistance and ch R is channel resistance, ex R is extrinsic resistance relate to V SG , including the resistance from the ungated regions ( R non-overlapped ) and contact resistance ( R c ) between metal and MoS , D V is drain voltage bias and D I is the drain current. D I can also be written as: =2 D ox GS TH D
WI C V V VL (S2) Where is intrinsic carrier mobility, ox C is the dual-gate oxide capacitance, W and L is the channel width and length, ' D V is effective drain bias of the T3, denoted in Fig. S7. For small D V , the V GS’ is approximately equal to V GS , thus ' 0 Dch D ox GS TH
VR WI C V VL (S3) oxtotal eGS TH
LC WR RV V (S4) Therefore, it can be simplified as a rational function: ay cx b (S5) where a 2 ox LC W , b TH V and x c 2 e R . We can use equation (S5) to fit the total R ~ GS V curve and obtain the fitting parameter c . Section 3
Y-function method [1-6]
The Y-function is defined as = Dm IY g (S6) I D is the drain current, and g m is the transconductance (= DG dIdV ), Therefore, the Y-function can be calculated from the transfer characteristics ( I D - V G ). In the strong inversion region, the Y-function is linearly dependent on 𝑉 G as: = 2g D ox D G THm
I WY C V V VL (S7) where 𝜇 is the low field mobility, 2 𝐶 𝑜𝑥 is the gate oxide capacitance, 𝑉 D is the drain voltage, and 𝑉 TH is the threshold voltage. 𝑊 and 𝐿 are the channel width and length, respectively. After the linear fitting of the Y-function vs. V G , both low field mobility ( 𝜇 ) and threshold voltage ( 𝑉 TH ) can been extracted. Once 𝜇 and 𝑉 TH are obtained, the mobility attenuation coefficient ( 𝜃 ) can be determined as: D G THm G TH
I V Vg V V (S8) The mobility degradation factor ( θ ) includes the effects of the extrinsic resistance (2 R ex ), and can be expressed as: ex ox WC L (S9) where 𝜃 is the intrinsic mobility degradation factor. The θ in multilayer MoS has a significantly larger contribution from ex R as compared to the 𝜃 . Hence, 𝜃 is considered negligible [2, 3]. As a result, the contact resistance ex R can be calculated from 𝜃 . ex ox LR W C (S10)
Figure S8
Extraction of R ex by the Y-function method. (a) Y-function vs. V Dual-G of the tri-gate MoS transistor with Dual-G mode and V Side-G =+4 V. From the linear fit in the strong inversion region (red solid line), both the low-field mobility ( ) and threshold voltage ( V TH ) can be extracted from the x-intercept and the slope. (b) The mobility attenuation coefficient ( θ ) as a function of V Dual-G can be calculated by the equation (3). (c) The 𝑅 ex as a function of V Dual-G which can be calculated from 𝜃 . Referances [1] Fleury, D.;Cros, A.;Brut, H.; Ghibaudo, G. New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs. In , 2008; pp 160-165. [2] Joo, M.-K.;Huh, J.;Mouis, M.;Park, S. J.;Jeon, D.-Y.;Jang, D.;Lee, J.-H.;Kim, G.-T.; Ghibaudo, G. Channel access resistance effects on charge carrier mobility and low-frequency noise in a polymethyl methacrylate passivated SnO nanowire field-effect transistors. Applied Physics Letters , , 053114. [3] Na, J.;Shin, M.;Joo, M.-K.;Huh, J.;Kim, Y. J.;Choi, H. J.;Shim, J. H.; Kim, G.-T. Separation of interlayer resistance in multilayer MoS field-effect transistors. Applied Physics Letters , , 233502. [4] Ghibaudo, G. New method for the extraction of MOSFET parameters. Electronics Letters , , 543-545. [5] Bhattacharjee, S.;Ganapathi, K. L.;Nath, D. N.; Bhat, N. Intrinsic Limit for Contact Resistance in Exfoliated Multilayered MoS FET.
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