Neuron inspired data encoding memristive multi-level memory cell
NNoname manuscript No. (will be inserted by the editor)
Neuron inspired data encoding memristive multi-level memorycell
Aidana Irmanova · Alex Pappachen James the date of receipt and acceptance should be inserted later
Abstract
Mapping neuro-inspired algorithms to sen-sor backplanes of on-chip hardware require shifting thesignal processing from digital to the analog domain,demanding memory technologies beyond conventionalCMOS binary storage units. Using memristors for build-ing analog data storage is one of the promising ap-proaches amongst emerging non-volatile memory tech-nologies. Recently, a memristive multi-level memory (MLM)cell for storing discrete analog values has been devel-oped in which memory system is implemented com-bining memristors in voltage divider configuration. Ingiven example, the memory cell of 3 sub-cells with amemristor in each was programmed to store ternarybits which overall achieved 10 and 27 discrete voltagelevels. However, for further use of proposed memorycell in analog signal processing circuits data encoder isrequired to generate control voltages for programmingmemristors to store discrete analog values. In this pa-per, we present the design and performance analysis ofdata encoder that generates write pattern signals for 10level memristive memory.
Keywords
Multi-level Memory · Memristors · Neuromorphic computing · Ternary logic
Human memory system requires encoding the informa-tion that comes from sensory inputs in the form it can
F. AuthorNazarbayev UniversityE-mail: [email protected]. AuthorNazarbayev UniversityE-mail: [email protected] process and store. The information can be encoded intovisual, acoustic and semantic representations[1]. Infor-mation transmission and transformation of such char-acter is achieved with the neural network of the brain[2]. First, sensory neurons receive the signals in the ana-log domain and pass the signal to the neurons of thenetwork that maintains a voltage gradient across itsmembrane, that has a different charge, depending onthe ions within the cell [3]. If the voltage changes sig-nificantly, an electrochemical pulse called an action po-tential (or nerve impulse) is generated. Thus the net-work of such neurons interacts between themselves inthe mixed signal domains. [4]. The encoded informa-tion is then stored in form of the synapses - a neuron toneuron connection, which strength can be increased ordecreased over time and learning process. Every singleneuron can form thousands of connections with otherneurons in this way, which means a typical brain wouldhave 100 trillion synapses [5]. This information accord-ing to neuroscience literature is stored in form of analoginformation in the human brain.Data processing that takes place in human brainoutperforms modern processors on many tasks like dataclassification and pattern recognition. This inspires neu-romorphic engineers to build massively parallel archi-tectures emulating the human brain by modeling low-power computing elements - neurons and adaptive mem-ory elements -synapses. One of the ways to implementcomputing systems that can mimic massive parallelismand low power operation as in brain is to scale densenon-volatile memory crossbar arrays [6]. In this paper,a neuron inspired memristor based multi-level memory(MLM) with analog data encoder that can be used incrossbar arrays is presented. We build the motivation ofusing multi-level memories on the premise that analog a r X i v : . [ c s . ET ] M a r Aidana Irmanova, Alex Pappachen James
Fig. 1
Ternary bit write pattern generating encoder placed before Multi-Level Memory for writing analog input voltage memories are integral to the development of cognitivealgorithms, both at sensory processing level and in highlevels of cognitive function implementations. The pre-sented circuit is configured to store 10 discrete analogvalues and simulated for different temperature condi-tions.The paper is organized as follows: Section II pro-vides background information of the memory cell usedin the paper. Further, the circuit for data encoder thatgenerates control voltages for writing discrete analogvalues is discussed. In following section simulation re-sults of the memory cell with data encoder at differenttemperature conditions is presented.
In this paper, we present an encoder for proposed mem-ory cell in[7] based on memristors, arranged in a poten-tial divider configuration that could emulate a weightedaddition that is indicative of dendritic segments of theneuron. To enable writing discrete analog values intothe cell it is required to encode the analog input intoternary bit write pattern control voltages that are usedto program memristors in the sub-cells. The memorycell is programmed using ternary bits of different ampli-tude [0 V ; 2 . V ; 4 V ] of corresponding logical values[0; 1; 2].Fig. 1 Shows the example of writing analog input volt-age of an amplitude 1.3V which correspond to 012 writepattern that generates [0 V ; 2 . V ; 4 V ] write pulses to besent to the relative [ V w ; V w ; V w ] write ports.To start with, the main advantage of the design ofgiven memory cell is that it is purely based on memris-tors. As memristors are nanoscale devices that operatewith current leakage which will result in less area andpower consumption [8]. In proposed memory cell shownin Fig. 2, the ungrounded node serves as an input portfor receiving signals and represents the membrane re-sistance. Its structure of voltage divider provides withdifferent V out levels across R during the read opera-tion, resulting from the V r read input voltage appliedacross the membrane resistance, where the membrane Fig. 2
Circuit design of the multi-level memory cell resistance is represented as the total resistance of mem-ristors connected in parallel. The cell is programmed toternary logic to achieve an increased number of statesby exploiting the state changes of multiple memristorsat a given time, overcoming the limitations of using sin-gle memristor that is practically limited by the devicevariability and implementation complexity. Each mem-ristor of the cell is placed into sub-cells, which are usedfor programming the memristor to high V , medium V and low V states. To program each memristor to thedesired state the write signal V w is applied through thewrite port from the positive terminal of the memris-tors, and the reset signal V s that precedes every writeoperation to erase previous states is applied from thenegative terminal - reset port of the device. In general,the memory cell with n sub-cells can store mn discretevalues, where m is the number of different levels of volt-age that is applied through V w , V w , V w write ports euron inspired data encoding memristive multi-level memory cell 3 Table 1
Write pattern for corresponding input range V w V w V w a = 0 a = 0.3 2 2 22 a = 0.31 a = 0.6 1 2 23 a = 0.61 a = 0.9 1 1 24 a = 0.91 a = 1.2 0 2 25 a = 1.21 a = 1.5 0 1 26 a = 1.51 a = 1.8 1 1 17 a = 1.81 a = 2.1 0 0 28 a = 2.11 a = 2.4 0 1 19 a = 2.41 a = 2.7 0 0 110 a = 2.71 a = 3 0 0 0 of the sub-cells. In this paper, simulation results of thememory cell with n = 3 sub-cells are presented, each ofthem programmable to m = 3( V , V , V ) states whichcould result in up to 27 level discrete analog memory. Itis to be noted that resistance values used for connectingto reset, write, read ports R , R , R should be set asR 1 R2 R3, otherwise, for n = 3 and m = 3 memorycell, discrete output levels will decrease down to 10 dif-ferent values. This is the result of equal voltage dropwithin each sub-cell shown in Fig.2 which combines tothe overall number of output states. Achieved 10 V out output states of the memory cell are presented in Fig.5. For reading the V out output states of the circuit readsignal V r is applied to the V r read ports of the sub-cell.For the setup with an encoder, the timeline of the sin-gle cycle of resetting, writing, and reading is provided inFig. 4. For simulations of the circuit initially 4 V writesignal V corresponding to logic 2 , 2 . V write signal V corresponding to logic 1 and 0 V write signal V corre-sponding to logic 0; 4 V V s reset signal; 0 . V V r readsignals were used. As regards resistors values,in this pa-per we used the setup of R = R = R resistances wasset as 500 Ω , and R w = R w = R w resistances was set1500 Ω , respectively. The resistance of R w write port isgreater as it connects to the encoder output ports andto ensure the working of the memory is stable the loadresistance was increased. For the simulations, the mem-ory cell performance memristor model described in [9]was used in LTSpice [10]. Fig. 3
Circuit design of an encoder for MLM
Table 2
Encoder circuit configurationNMOS:W/L ( µ m) 0.36/0.18PMOS:W/L ( µ m) 0.72/0.18 V + /V − V d d V ss -1.5V V th V s V w R R To design an encoder for the proposed memory cell,first, its 10 discrete output levels were sorted from smallto large and its corresponding write pattern codes (Fig.5) were assigned to the analog value ranges [ a ; a ] thatare given in Table 1. In this paper, we assume that ana-log input signal variation will be within 3V amplitudeand this value is divided to 10 ranges. To encode ana-log input signal into write pattern V w , V w , V w controlvoltages it is required to identify which range [ a ; a ]of analog values it belongs to and after that generatethe voltage pulses according to its assigned write pat-tern code [0 V ; 2 . V ; 4 V ] for corresponding [0; 1; 2] logicvalues. To implement this it was decided to constructseparate code selector blocks for each write ports V w .The circuit design of this encoder is presented in Fig.3. The circuit consists of 3 code selecting blocks for 3write ports V w , V w , V w of the memory cell. Selectoritself consists of comparison, thresholding, and summa- Aidana Irmanova, Alex Pappachen James
Table 3
Discrete analog output voltages of 10 level memory cell with data encoder at different temperature condition V out of MLM at 20 ◦ C V out of MLM at 30 ◦ C V out of MLM at 40 ◦ C V out of MLM at 50 ◦ C Mean ( V ) STDEV Mean ( V ) STDEV Mean ( V ) STDEV Mean ( V ) STDEV222 4.462E-04 1.079E-06 4.461E-04 1.130E-06 4.461E-04 9.944E-07 4.461E-04 1.060E-06122 1.884E-03 5.746E-07 1.884E-03 6.277E-07 1.884E-03 6.277E-07 1.883E-03 4.765E-07112 4.319E-03 4.664E-07 4.319E-03 5.979E-07 4.319E-03 5.979E-07 4.319E-03 6.073E-07022 4.712E-03 2.295E-05 4.712E-03 2.326E-05 4.712E-03 2.326E-05 4.712E-03 2.320E-05012 6.816E-03 8.382E-06 6.816E-03 8.310E-06 6.816E-03 8.326E-06 6.816E-03 4.700E-07111 6.967E-03 6.282E-06 6.969E-03 8.235E-06 6.970E-03 8.321E-06 6.970E-03 7.565E-06002 7.898E-03 4.084E-05 7.896E-03 4.041E-05 7.896E-03 4.013E-05 7.896E-03 3.864E-03011 8.266E-03 1.351E-05 8.266E-03 1.342E-05 8.266E-03 1.342E-05 8.266E-03 1.342E-05001 8.513E-03 2.829E-05 8.513E-03 2.798E-05 8.513E-03 2.798E-05 8.513E-03 8.513E-03000 8.598E-03 2.015E-05 8.598E-03 2.017E-05 8.598E-03 2.017E-05 8.598E-03 1.969E-05(a)(b)(c) Fig. 4
Time diagram of a single cycle of the (a) reset (b)write and (c) read signal tion blocks. At the comparison block outputs of 2 com-parators with reference voltages [ a ; a ] are fed to theCMOS AND gate. In case the output of this block ishigh it will generate assigned V w voltage pulse fromthe thresholding block which consists of a comparatorwith V t h reference voltage. As the input signal can be-long to only one range [ a ; a ], outputs of all threshold-ing blocks are summed to implement logical conjunc-tion and produce V w write signal. For comparison andthresholding blocks the model of operational amplifier LT C
LT C . µ CMOS transistor technology.Further information on circuit configuration is providedin Table 2.
To test the performance of the encoder train of pulseswith an amplitude ranged from 0 V to 3 V with the stepof 0 . V and the duration of 0.6ms was fed to the cir-cuit input port (Fig.6 (a)). Before writing the signalsfrom given input train, the memory cell was reset with4 V amplitude signal, preceding each write operation asshown in Fig.4. Afterwards, the write signal is sent tothe encoder and produced write pattern control volt-ages was fed to V w , V w , V w write ports for program-ming the memory cell to discrete analog level. Thenthe read signal with the duration of 0.2ms is sent tocheck the V out output voltage. Output of the encoderresulted in [4 V ; 2 , V ; ( − .
2; 0 . V ] for [2; 1; 0] logicalvalues relatively. Slight variations in the write patternresulted as well in the shift of V out output levels of thememory cell. This can be seen in Fig. 5(a) and Fig. 5(b).In Fig. 5(a) the outputs of the memory cell were pro-grammed by directly applying write pattern voltages,without an encoder, while for Fig. 5(b) the output of thememory cell operating with an encoder at the tempera-ture of 50 ◦ C is provided. Table 3 shows average outputlevels of the memory and its standard deviation at the euron inspired data encoding memristive multi-level memory cell 5(a) (b) Fig. 5
Achieved discrete analog levels of 10 level memory cell (a) directly applying control voltages of write pattern and (b)using an encoder for generating the write pattern(a) (b)5(c) (d)
Fig. 6
Generated output write pattern signal from (a) analog input signal fed to the encoder ranged from 0 V to 3 V with0 . V step for (b) V w , (c) V w , (d) V w write ports. temperature of 20 ◦ C , 30 ◦ C , 40 ◦ C and 50 ◦ C . It can beseen that the output of the memory cell programmedwith an encoder change negligible at this range of tem-perature. Power dissipation for single data encoder anmemory cell pair can reach up to 94.5mW. In this paper, we presented the multi-level memristivememory cell with data encoding control circuits. Pre-sented memory cell can be used in the crossbar arrays tostore discrete analog values. The proposed encoder cir-cuit consists of operational amplifiers and CMOS tran-
Aidana Irmanova, Alex Pappachen James sistors which configuration can be further improved toreduce power and area consumption. Simulation resultsshowed that the memory cell outputs negligibly vary atdifferent temperature conditions. Inspired from neuronstructure the memory cell stores discrete analog val-ues encoding the analog input, which can be used inthe implementations of the neuromorphic systems forsynaptic weights storage. Incorporating analog storageof discrete values allows analog data computation whichresults in improved performance in terms of speed. Toensure the compatibility of the memory cell with dataencoder and stable performance of the memory cell re-sistance values of the resistive network of sub-cells wereincreased which involved increasing write and reset con-trol voltage amplitudes.
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