Organic Electronics Picks Up the Pace: Mask-Less, Solution Processed Organic Transistors Operating at 160 MHz
Andrea Perinot, Michele Giorgio, Virgilio Mattoli, Dario Natali, Mario Caironi
OOrganic Electronics Picks Up the Pace: Mask-Less, Solution Processed Organic Transistors Operating at 160 MHz
Andrea Perinot, Michele Giorgio, Virgilio Mattoli, Dario Natali, Mario Caironi * Dr. A. Perinot, Dr. M. Giorgio, Prof. D. Natali, Dr. M. CaironiCenter for Nano Science and Technology@PoliMi, Istituto Italiano di Tecnologia, 20133 Milan, ItalyE-mail: [email protected]. Virgilio MattoliCenter for Micro-BioRobotics, Istituto Italiano di Tecnologia, 56025 Pontedera (PI), ItalyProf. Dario NataliDepartment of Electronics, Information and Bioengineering, Politecnico di Milano, 20133Milan, ItalyKeywords: Organic transistor, high-frequency, solution processing, direct writing, organic electronics
Abstract
Organic printed electronics has proven its potential as an essential enabler for applicationsrelated to healthcare, entertainment, energy and distributed intelligent objects. The possibilityof exploiting solution-based and direct-writing production schemes further boosts the benefitsoffered by such technology, facilitating the implementation of cheap, conformable, bio-compatible electronic applications. The result shown in this work challenges the widespreadassumption that such class of electronic devices is relegated to low-frequency operation,owing to the limited charge mobility of the materials and to the low spatial resolutionachievable with conventional printing techniques. Here, it is shown that solution-processedand direct-written organic field-effect transistors can be carefully designed and fabricated soto achieve a maximum transition frequency of 160 MHz, unlocking an operational range thatwas not available before for organics. Such range was believed to be only accessible withmore performing classes of semiconductor materials and/or more expensive fabricationschemes. The present achievement opens a route for cost- and energy-efficientmanufacturability of flexible and conformable electronics with wireless-communicationcapabilities. 1 ntroduction
The development of new applications in the fields of healthcare, energy, distributed sensingand entertainment will require the integration of electronic functionalities into everydayobjects. Organic electronics has gained its place among the promising technologies to thispurpose, owing to a set of distinctive features: [1] first, it is compatible with flexible substrates,which allows its integration with objects characterized by non-conventional form factors;second, it enables the use of deposition techniques derived from the graphic arts and givesaccess to cost-efficient manufacturing; third, selected organic materials are biocompatible,allowing for a high degree of integration between electronics and biology. The impressiveprogress in this field has been driven by: (i) the enhancement of a set of figures of merit,primarily the charge mobility of the semiconductors, now well exceeding amorphous siliconand rivalling low temperature deposited metal oxides; [2] (ii) the strengthening of cost- andenergy-efficient fabrication strategies, with the notable examples of printing [3, 4] and laserprocessing, [5-7] which are now suitable for the micron-scale patterning of functional materialson large area; (iii) the demonstration of a set of proof-of-concept applications, includinggreen/biodegradable electronic devices, [8] electronic skins and conformable patches forpersonal healthcare [9-12] or flexible organic microprocessors. [13]
However, in order to widen the set of applications that can be envisioned, a set offunctionalities is still lacking. Among these, wireless communication between distributedelectronic sensors/actuators and data-processing devices, or fast addressing capabilities forlarge-area arrays of sensors or light-emitting devices. The implementation of thesefunctionalities would enable flexible large-area displays or sensor arrays and the creation ofdistributed wireless networks of electronic devices within the Internet of Things (IoT)framework. [14]
So far, this set of applications has been considered out of reach for organicelectronics. 2 fundamental requirement to this goal is the realization of organic transistors, the basicbuilding block of electronic circuits, operating at frequencies well above several tens of MHzand above. Such performance should also be obtained with the sole use of mask-less andscalable fabrication processes, in order to retain the manufacturability edge of organicdevices. [15]
One of the most widely adopted figures of merit to quantify the maximum operationfrequency of single transistors and allow comparison among different technologies is the transition frequency f t , namely the frequency for which the ratio between the small-signaldrain and gate currents is unity. [16] To date, the highest f t obtained for a an Organic Field-Effect Transistor (OFET) is 27.7 MHz . [17] Since f t is proportional to the bias voltage, someauthors have used the voltage-normalized transition frequency f t /V as a more convenientfigure of merit to assess the relative performance of transistor technologies. [5, 18, 19] In this case,the highest f t /V value achieved for OFETs is 2.23 MHz/V, [20] achieved by virtue of a metal-oxide/self-assembled monolayer dielectric layer with high areal capacitance (700 nF/cm ), asub-micron channel length defined via high-resolution silicon stencil masks and extremelylow contact resistance (29 Ωcm) between gold electrodes and a small-molecule organicsemiconductor. These results however, together with the wide majority of the works on high-frequency OFETs, included masks and/or evaporation steps in the process flow. [21-24] Such anapproach, while allowing the access to improved performances by virtue of an enhancedcontrol over the deposition of the functional layers, poses a number of difficulties in terms ofthe future scalability to cost-efficient mass production. The sole use of mask-less direct-writing or solution-based techniques largely complicates the achievement of high-frequencyoperation, an issue also testified by the very limited number of attempts in the past. [5, 25-28]
As of now, despite the technologies and materials exhibiting the performances required forhigh-frequency operation in excess of several MHz and approaching the 100-MHz range ( i.e. charge mobility approaching 1 cm /Vs and patterning resolutions below 1 µm) are in principleavailable, further progress has been hampered by a set of critical aspects that have been often3verlooked. Primarily, the achievement of high effective charge mobility in downscaledtransistors requires to obtain normalized contact resistances ( R c W ) below 1 kΩcm (or less,depending on the other physical parameters and bias point of the transistor), which have beenrarely demonstrated. [19] This aspect is intertwined with the need for reduction of the capacitiveparasitism related to the gate-to-source and gate-to-drain geometrical overlap, which, in theframe of the current-crowding injection model, also affects charge-injection in a non-trivialway. [15]
Finally, the design of efficient strategies for the dissipation of the generated heatbecomes of paramount importance in order to prevent the destructive breakdown of the deviceand to allow for continuous-mode operation: downscaled OFETs with channel lengths in theorder of the µm, sustaining a current per unit width in excess of 1 mA/mm and voltages in therange of few tens of volts, need to dissipate efficiently a power density in the range 10 to 100Wmm -2 , which can easily lead to thermal breakdown of the device. The latter is notsurprising, considering that the constituting materials, in particular plastic substrates, arecharacterized by a very low thermal conductivity, making heat dissipation highly inefficient.Recently, it was proposed that, for some applications ( e.g. switching power converters,pulsed-mode data transfer), this can be circumvented by operating the transistor in pulsedmode, which allowed to reach a record f t of 40 MHz at a bias of 8.6 V in such operationregime. [29] However, fully exploiting the possibilities offered by a high-frequency organictechnology requires continuous-mode operation, which in turn requires the adoption ofefficient dissipation strategies.Here we show that a route for the realization of high-frequency OFETs operating at a record-high f t of 160 MHz and f t /V of 4 MHz V -1 can be implemented with a combination of scalablelaser-based direct-writing techniques and solution-based deposition of organic polymers. Wecarefully selected a set of solutions to the problems illustrated above that complies with therequirement of a fully mask-less and solution-based process flow: these include laser-basedpatterning of metallic inks with a micron-scale resolution, the modification of the electrodeswith a self-assembled monolayer for the achievement of low contact resistance and the4doption of a substrate with high thermal conductivity. With this result, we prove thatoperational frequencies in excess of 100 MHz can be achieved with organic transistors.Moreover, we do not only show a working organic transistor with the highest f t to date and thehighest f t /V for continuous operation, but we also demonstrate that a route for the achievementof this performance with scalable, mask-less, solution-based techniques is available, and thatthe future implementation of cost- and energy-efficient mass manufacturing of high-performance organic electronic applications is credible. Results
We realized high-frequency OFETs in a bottom-contact, top-gate architecture with the layoutschematized in
Figure 1a , carefully selecting the architecture, materials and processes inorder to overcome a variety of limitations to high-frequency operation. Our fabrication process relies on the flow illustrated in Figure 1b. We selected femtosecond-laser sintering as a direct-writing patterning technique for the realization of micron-scaleconductive electrodes for OFETs. Such an approach was successfully adopted in the past forthe realization of metallic grids [30] and OFETs, [7, 31, 32] including high-frequency, direct-writtenand printed OFETs, [27, 33] also on plastic substrate. [5]
The choice of the proposed fabricationscheme is advantageous for a variety of future implementations into a wide set ofapplications, by virtue of its digital nature and compatibility with different substrate materials.However, devices of the kind we realize in this work, when fabricated on plastic, are prone tosuffer of thermal runaway or breakdown (described later in the text), due to the significantamount of power density in the channel region of the device and to the limited thermaldissipation properties of plastics (commonly exhibiting thermal conductivity in the range 0.1– 0.5 Wm -1 K -1 ). To comply with the need for efficient thermal dissipation of such generatedheat, we adopted here a highly thermally-conductive substrate of aluminum nitride (AlN),exhibiting a thermal conductivity in the order of 170 Wm -1 K -1 .5o fabricate our OFETs we first coat our substrate with an Ag-nanoparticle ink, then welocally induce the agglomeration of the metal nanoparticles into conductive structures vialaser sintering. [5] Then, the unprocessed part of the ink is washed out with an organic solvent,leaving high-resolution conductive patterns with a thickness of 70 nm on the substrate. Thesestructures will constitute the source and drain electrodes of the realized OFETs, yielding achannel length L = 1.2 µm, a channel width W = 800 µm, an electrode width L c = 1.7 µm. Topromote an efficient charge injection from such electrodes into the semiconductor, we theninduce the self-assembly of a monolayer of dimethylamino(benzenethiol) (DABT) on thesurface of the metallic patterns. [34] Then, we adopt the widely-studied and good electrontransporting semiconducting co-polymer poly[N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5’-(2,2’-bithiophene), P(NDI2OD-T2), and deposit a thinlayer of such material via off-centered spin-coating from a solution in toluene. Such aselection of deposition technique and solvent yields a semiconducting layer with enhancedcharge transport properties thanks to the promotion of aggregates formation in the solution,which in turn yields the formation of a layer of aligned polymer nanofibrils. [35, 36]
We thenadopted a bilayer dielectric: we first deposit a 40-nm-thick layer of polystyrene blended withan azide-based crosslinker (1,11-Diazido-3,6,9-trioxaundecane) and we cross-link such layervia UV-light exposure at a wavelength of 256 nm. On top of the polystyrene interlayer, wespin-coat a 300-nm-thick layer of poly(vinyl cinnamate), which is then analogously photo-crosslinked. The complete dielectric bilayer exhibits an areal capacitance C diel = 8.54 nF cm -2 ,calculated using the literature value of 3.4 for the dielectric constant of poly(vinyl cinnamate)and a value of 2.6 for cross-linked polystyrene (determined from our measurements oncapacitor devices). The top gate electrode is then realized via laser sintering incorrespondence of the transistor channel, keeping the overlap with source and drain electrodeslow, to comply with the need of reducing the overlap capacitive parasitism. This is the firsttime laser sintering [31] is used for the fabrication of gate electrodes on polymer dielectrics intop-gate structures. Encapsulation of the device to prevent degradation induced by the6xposure to the ambient environment concludes the fabrication; further details are reported inthe Supporting Information.A top-view representation of the final device is shown in Figure 1c alongside with amagnified micrograph of the active region of the transistor, which highlights the finealignment between the top gate electrode and the channel area. We confirmed such alignment,associated with a low capacitive parasitism, with cross-sectional SEM imaging of the device(Figure 1c), which allows to estimate the size of the geometrical overlap between electrodesin the range ∼ Figure 2a ) and output characteristics (Figure S3) of ourtransistors, verifying a correct operation up to a bias voltage of 40 V, with a maximum gateleakage current in the order of the nA, with respect to a channel current in the order of fewmA. This proves that laser processing on top of a multilayer stack of organic materials,including a semiconductor and a dielectric, is compatible with the fine patterning of high-resolution conductive electrodes without damage to the underlying materials. We then highlight how the integration of a substrate with a high thermal conductivity in ourprocess allows ideal DC operation of the device and prevents the thermal breakdown. Inparticular, in the case of OFETs with the same architecture and comparable fabricationprocess, realized on a glass substrate (which exhibits a lower thermal conductivity in the orderof 1 Wm -1 K -1 ), when the generated power per unit area approaches the range 20-30 W mm -2 ,the devices start to suffer from thermal degradation, the current driven by the device saturates/drops with respect to the increase of the gate voltage and severe hysteresis appears in thetransfer curve (Figure S4). Contrarily, for the devices of this work, even at the bias pointcorresponding to the maximum generated power per unit area P th ( I d = 2.18 mA, V d = 40 Vand P th = 90 W mm -2 ), correct operation of the device is preserved and no signs of thermaldegradation are visible. We calculated the apparent charge mobility of our devices in the linear ( µ lin ) and saturationregimes ( µ sat ) versus gate voltage (Figure 2b). The ideality of the DC operation of the7ransistors is confirmed by the flatness of the curves in the fully accumulated regime above 10V, with a slight roll-off that can be attributed to some residual impact of the contactresistance. The maximum values for the apparent charge mobility are µ lin = 0.22 cm V -1 s -1 and µ sat = 0.62 cm V -1 s -1 . We extracted the width-normalized contact resistance R c W and theintrinsic charge mobility µ i of our devices, which we estimate to be R c W = 300 Ωcm and µ i =1 cm V -1 s -1 in the saturation regime at a bias point of V g = V d = 40 V (see SupplementaryInformation for details). Such a value of R c is not only a key requirement in order to accessfrequency regimes in excess of 100 MHz, [15, 19] but is among the best reported values forOFETs in general and is extremely low when considering the case of transistors realized viadirect-writing, solution-based methods and optimized for low geometrical overlap ofelectrodes and high frequency operation. [37-39] We then measured the AC characteristics of our device by means of S-parameters, using asetup already described in our previous work, [27] calibrated with a SOLT procedure andcorrected with a 12-term error model. From the measured S-parameters, the parasiticcontributions of the pads and interconnections are de-embedded from the measurement with aone-step procedure [40] and the hybrid parameter h is extracted (Figure 2c), allowing toidentify f t according to h (f t ) = 0 dB, which yields an unprecedented f t of 160 MHz at a biasvoltage of 40 V for OFETs in the case of the best device (Figure 2c, linear fit). In terms of thevoltage-normalized transition frequency f t /V , we reached a figure as high as 4 MHz V -1 , alsoin this case the highest value reported for an OFET. Such extracted f t performance is robustwith respect to thermal degradation effects: measurements on a nominally identical deviceresults in a practically identical f t of 158 MHz, which remains stable after a second,consecutive measurement of h at V g =
40 V (Figure 2d, black and red lines) and after furthermeasurements at gate biases of 35 and 30 V (Figure 2d, blue and purple lines). As a crosscheck of the consistency of the AC performance, we extracted the values for thegate/drain and gate/source capacitances C gd and C gs for V g = V d = 40 V, alongside with the8otal gate capacitance C g = C gd + C gs (Figure S5). The total gate capacitance, at a first order,can be estimated as follows: C g ≅ C diel W ( L + L ov + d ) (1)where L ov is the geometrical overlap between gate and source (or drain) electrode and 2 d, forlow-overlap structures of the kind presented here, accounts for the contribution of the fringingfield in the form of an “equivalent overlap length”, equal to the thickness of the dielectric d . [15] According to this formula, and with L ov in the range 0-250 nm, the total gate capacitance C g can be estimated to be in the range 101 - 135 fF, which is in good agreement with the valueextracted from our measurement (140 – 150 fF above 30 MHz, Figure S5). Thetransconductance and output resistance can be estimated from the DC curves respectively as g m = d I d d V g and r o = ( d I d d V d ) − , evaluated at the transistor bias V g = V d = 40 V, yielding g m =0.115 mS and r o = 25.3 kΩ. These values obtained from the DC characterization are inagreement with the S-parameters measurements ( g m = 0.115 mS and r o = 22 kΩ at 10 MHz,Figure S6). In addition, we verified that g m is not altered by the de-embedding procedure,confirming the consistency of the obtained results (Figure S6).The measured f t can be compared to the theoretical value estimated from the transistor DCelectrical parameters and geometrical dimensions, according to: f t = g m π C g . (2)With the range of values for C g calculated above and with the range of values for g m extractedfrom DC, the theoretical f t is calculated to be in the range ~ 140 - 180 MHz, which isconsistent with our measured value. By including our additional analysis on the contactresistance (see Supplementary Information), the measured f t can also be related to the valuepredicted by more refined theoretical models in recent reports, [15, 19] which include not only theeffects of the fringing electric field for low-overlap structures (already accounted for byEquation (1)) but also the effects associated with charge injection physics in staggered OFETs9ith small electrode overlap. The application of such model consistently returns, for theparameters of the transistors of this work, a predicted f t in the range 138-146 MHz (seeSupplementary Information), which is not dissimilar to our measured result.Overall, high-frequency operation at 160 MHz of solution-processed OFETs is demonstratedvia an S-parameter measurement and further validated by the agreement of the extractedtransistor small-signal AC parameters with the ones calculated through physical andgeometrical considerations. This experimental demonstration agrees with and complementsthe theoretical roadmaps described in recent works. [15, 19] Discussion
Contrarily to the widespread assumption that organic electronics is relegated to very low-frequency operation, we have shown here that organic FETs can operate at an f t of 160 MHzand f t /V of 4 MHz V -1 . This value of f t is by far the highest reported for any organic transistorto date, while f t /V is the best reported for organic transistors capable of sustaining continuousbiasing (Table S1). The significance of this achievement is further reinforced by the soleadoption of direct-writing and solution-based fabrication methods, which have traditionallycomplicated the achievement of high-performance figures of merit, as well as finely-controlled patterning of functional materials at the micron scale. The OFET AC performance demonstrated in this work was achieved both by devising a set ofstrategies to overcome the bottlenecks to high-frequency operation and by combining theminto a fabrication scheme solely using scalable techniques. First, the high patterning resolutionnecessary both to downscale the transistor dimensions and to contain the capacitive parasitismhas been achieved by using laser sintering, which allowed the fine alignment of micron-sizedelectrodes via direct writing. Second, the charge injection from the contacts, which must bevery efficient for downscaled architectures with low overlap between gate and bottomelectrodes, has been promoted by inducing the self-assembly of an amine-based monolayer.This approach allowed to achieve width-normalized contact resistance R c W = 300 Ωcm,10hich is among the best reported values for solution-processed, direct-written OFETs ingeneral. This achievement is further reinforced by the fact that it is associated with anarchitecture optimized for high-frequency operation, whose low electrode overlap is well-known to be detrimental for charge injection. Third, thermal breakdown/degradation has beenavoided by using an appropriate thermally-conductive substrate. The latter result highlights anunprecedented need for substrate materials for OFETs, combining flexibility and sufficientthermal conductivity, thus indicating a clear path to be further pursued in future. [41-44] In conclusion, we have demonstrated that high-frequency operation in excess of 100 MHz isaccessible to organic-based electronics. The result we show here represents a suitablecomplement and a validation to a set of recent reports that theoretically detailed a feasibleroadmap towards high-frequency operation or organic transistors. [15, 19]
Within the roadmapdetailed in such works, our achievement of a R c W of 300 Ωcm in high-frequency devicesbased on printed polymers constitutes one of the key enablers. These achievements challenge the conventional, well-known tradeoff between the higherelectrical performances of inorganic materials ( e.g. silicon, metal-oxides, carbon nanotubes)with the advantageous mechanical properties and the cost- and energy-efficient processabilityof organics. Our findings, overall, outline a credible route towards the adoption of organics inan expanded set of applications, including remote healthcare, distributed sensing, design andentertainment, requiring the availability of a technology integrating large-area electronics withwireless-communication capabilities, realized via cost- and energy-efficient productionschemes. Experimental Section
For the experimental section, please refer to the Supporting Information.
Acknowledgements
The authors are grateful to L. Criante for the support with the femtosecond laser machiningsetup. Part of the work has been carried out at Polifab, the micro- and nanotechnology centerof the Politecnico di Milano. This work was financially supported by the European ResearchCouncil (ERC) under the European union’s Horizon 2020 research and innovation programme“HEROIC”, grant agreement 638059. 11 eferences [1] X. Guo, Y. Xu, S. Ogier, T. N. Ng, M. Caironi, A. Perinot, L. Li, J. Zhao, W. Tang, R.A. Sporea, A. Nejim, J. Carrabina, P. Cain, F. Yan,
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Andrea Perinot, Michele Giorgio, Virgilio Mattoli, Dario Natali, Mario Caironi*
Methods
Materials:
Aluminum Nitride substrates were purchased from MARUWA CO. The Ag-nanoparticle ink used in laser sintering (NPS-L) was purchased from HARIMA.Dimethylamino(benzenethiol) was purchased from TCI Chemicals. P(NDI2OD-T2) waspurchased from Polyera. Polystyrene (M w = 2000000), poly(vinyl cinnamate) (M n = 40000)and 1,11-Diazido-3,6,9-trioxaundecane were purchased from Sigma Aldrich. The epoxy resinwas purchased from Robnor. FET fabrication:
On the AlN substrates we first defined, via conventional photolithography,a set of structures and calibration patterns for connecting our FETs to the high-frequencyprobes for S-parameter measurement. The details on the structures can be found in
Giorgio etal . [1] Then, we coated the Ag-nanoparticle ink onto these substrates via spin-coating at 7000rpm for 5 min. Then, we patterned the source and drain bottom electrodes through lasersintering using the setup and following the procedures illustrated in our previous work. [2]
Inthis case, the incident laser power was 17.2 mW at a scanning speed of 0.05 mm s -1 . Theunprocessed part of the ink was removed by thorough rinsing with o-xylene. Then, Ar-plasmais applied for 4 minutes at a power of 100 W, and the self-assembly of DABT on the silverelectrodes is induced by dipping the samples in a solution of 17 µl DABT in 12 ml ofisopropanol for 15 minutes. The samples are then rinsed with isopropanol. The semiconductorlayer is then deposited via off-centered spin-coating [3] (in nitrogen atmosphere) of a 7 g/lsolution of P(NDI2OD-T2) in toluene, at a speed of 1000 rpm for 30 s. The samples are thenannealed at 100 °C for 15 minutes. After cooling, a 40-nm-thick layer of polystyrene, mixed1ith 1,11-Diazido-3,6,9-trioxaundecane at a weight ratio of 10:1, is deposited via spin-coatingat a speed of 1500 rpm for 5 minutes from a solution in n-butyl acetate at a concentration of7.5 g/l. Then, we spin-coated a solution of 50 g/l poly(vinyl cinnamate) in cyclopentanone at aspeed of 1500 rpm for 2 minutes, so to yield a 300-nm-thick layer, which is then cross-linkedanalogously to the underlying layer. We then patterned the gate electrodes via laser sinteringwith the same procedure as illustrated above, using an incident power in the range 4.9-5.3mW and a scanning speed of 0.02 mm s -1 . Finally, we encapsulated the devices by spin-coating a 50 g/l solution of PMMA in o-xylene at a speed of 1300 rpm for 60 s, followed byannealing at 60 °C for 20 min for solvent removal, followed by deposition of a 1-um-thicklayer of parylene via CVD, finally completed by drop-casting a bi-component epoxy resin.After 24 h, the samples are then annealed for 8 h in nitrogen atmosphere at 105 °C. Measurement:
The thickness of the laser-sintered electrodes and of the polymer layers weremeasured with an Alpha-Step IQ profilometer by KLA-Tencor. The DC measurements wereperformed in nitrogen atmosphere using a Keysight B1500A Semiconductor ParameterAnalyzer. The AC measurement was performed in ambient atmosphere using a setup andcalibration method already described previously. [1]
The parasitism attributed to themeasurement pads and interconnections has been removed by measuring an open structurewith a geometry identical to the interconnections used for the transistor measurement. [1] upporting FiguresFigure S1: Cross-sectional SEM images of the realized device, with magnifications of thearea in the vicinity of the bottom electrodes. Measurements of the electrode geometricaloverlap are also shown. 3 igure S2:
Optical image of a typical device and related confocal profilometry highlighting aparticular of the laser-sintered gate track. The average thickness of the track on top of thedielectric stack is ~ 40-50 nm. All images were acquired with a Leica DCM 3D ConfocalProfilometer, at 150x magnification. Profilometer data were elaborated with Gwyddionsoftware (plane tilting, profile extraction, file conversion). C u rr en t ( m A ) Drain Voltage (V) V g = 0 V V g = 10 V V g = 20 V V g = 30 V V g = 40 V Figure S3:
Measured output curve for the realized high-frequency OFET.4 igure S4:
Measured transfer curves for OFETs on a glass substrate with low thermalconductivity, in the order of 1 W/mK. The devices are fabricated with the same architectureand comparable process as the ones fabricated on AlN substrate, and differ in terms ofchannel length and dielectric material (in this case, L = 1.4 µm, poly(vinyl alcohol) is used inplace of poly(vinyl cinnamate) and the channel width is W = 800 µm or W = 80 µm). a)Transfer curves for V d = 20 V in logarithmic scale. b) Same transfer curves (only forwardscan) in the linear regime. C apa c i t an c e ( f F ) Frequency (Hz) C gd C gs C g Figure S5:
Calculated gate capacitances, extracted from the S-parameter measurement.5 g m ( m S ) Frequency (Hz) g m (De-embedded) g m (Before de-embedding) r o (De-embedded) r o ( k ) Figure S6:
Calculated g m and r o , extracted from the S-parameter measurement. We show theextracted value for g m both before and after the de-embedding. Table S1 : Selected results in the literature for high-frequency organic transistors and circuits, ordered in terms of f t /V. Here reported only the works exhibiting f t /V in excess of 1 MHz/V, incontinuous-mode operation. Reference f T (MHz) f t /V (MHz/V) a) FlexibleSubstrate Mask-lessfabrication
This Work
160 4 X Yes
Borchert et al . [4] Perinot et al . [2] Yamamura et al . [5]
20 2 X X
Nakayama et al . [6]
19 1.9 X X
Uno et al . [7]
25 1.67 X X
Giorgio et al . [1]
19 1.27 X Yes
Kitamura et al . [8] Uemura et al . [9]
20 1 X X a) Our calculation when not reported. f t is normalized to the highest voltage between source-gate or drain-gate. X: not applicable. xtraction of the contact resistance In the saturation regime, which is the case of interest here, only the contact resistance atsource side matters (provided that voltage drop on the contact resistance at drain side is lowenough to maintain the transistor in saturation [10] ).In the framework of the current crowding model, suitable for staggered transistors, contactresistances can be expressed as: R C = R y W L tanh ( L ov L ) , (1)Where: L ov is the gate-contact overlap; R y is the resistance per unit area taking into accountinjection and transport across the bulk; L = √ R y / R sh is the injection length, viz. thecharacteristic length over which injection would take place for very large L ov , R sh being thechannel sheet resistance. Modelling the carrier mobility as a power law, μ = μ ( V G − V T ) γ , thesheet resistance can be expressed as R sh = [ μ C ins ( V G − V T ) γ + ] − . For the case of very small L ov , which is the case of interest here (actually for L ov < L , to beverified a posteriori ), Equation (1) can be simplified as the sum of a constant term and of a V G -dependent term, as it follows [11] : R C = R y W L ov + L ov W R sh = R c , const + R c ,var ( V G ) , (2)where the first term accounts for injection and transport across the film, whereas the secondterm accounts for transport along the film at the semiconductor/insulator interface. The challenge in the saturation regime is due to the fact that the current voltage relationshipincorporating the effects of contact resistance is actually an implicit function, without thepossibility of writing current as an explicit function of V G in the general case: I = μ C ins WL ( V G − V T − R C I ) γ + , (3)7here V T is the threshold voltage. There are 5 unknowns in Equation (3): , , V T , R c, const , L ov ,( R c, var can be expressed as a function of , , V T , L ov ). To extract them from experimentaldata, we devise an iterative fitting algorithm. In addition, to ease the procedure and reduce thenumber of fitting parameters, we select reasonable ranges for µ and V T , and for each ( µ , V T )couple we run the following algorithm.The parameter γ is initialized at 0.01. Since and V T are fixed and is initialized (or fitted, vide infra ), we can calculate ^ V G , the base which is raised to (γ + 2) in Equation (3): ^ V G = V G −V T − R C I = ( Iμ C ins WL ) γ + . (4) Now we take advantage of the fact that: V G and I are experimentally measured; and V T are fixed. We plot V G −V T − R C I versus V G and, exploiting Equation (2), we fit R c,const , L ov and γ , with the constraint γ > 0. The fitting is done in the range 23 V < V G < 40 V. With the value for γ estimated at step 2, we jump to step 1 and reiterate for 100 cycles.We sometimes experienced oscillations in the fitted value for between 0 and a certain ~ γ .Indeed, for consistent and realistic fitted parameters, ~ γ is very close to 0 (actually smaller than0.043), therefore the impact of such oscillation is negligible. In these cases, to proceed withthe analysis, we arbitrarily chose γ = ~ γ and we run a final direct fit of R c , determining R c,const and L OV . Later, we verified that different choices for γ ( i.e. γ = ~ γ or γ = ~ γ ) did notappreciably change the results of the fitting.The parameters γ , R c,const and L ov extracted with µ in the range 0.94 – 1.1 cm /Vs and V T in therange 5.9-6.2 V are shown below in Table S2. From the independent measurement of thegeometrical overlap between electrodes and of the dielectric thickness, within the framework8f the gate capacitance model illustrated in the main text, [12] we identify the acceptable valuesfor L ov ( i.e. L ov < 0.61 µm) and we highlight the corresponding combinations in redin Table S2. Table S2:
Extracted values of γ, R c,const , L ov as a result of the fitting of the experimental curves according to our algorithm. Values corresponding to the combinations where L ov is within the acceptable range (according to a second independent measurement) are highlighted in red.In order to evaluate the goodness of the fitting resulting from the algorithm outlined above,we define as a figure of merit the quantity err , with the aim of weighting the goodness offitting for both the current and the contact resistance: We calculate the quantity er r I = ∑ V g = V V ( I − I fitted I fitted ) We calculate the quantity er r R c = ∑ V g = V V ( R c − R c , fitted R c , fitted ) We define er r = er r R c + er r I err for each combination of parameters and V t is presentedIn Table S3, where the acceptable values are highlighted in red with the same criterion asTable S2 above. Table S3:
Calculated values for err according to our algorithm. Values corresponding to the combinations where L ov is within the acceptable range (according to a second independent measurement) are highlighted in red.The best fittings of the experimental data curves when combined with the constraints on theacceptable range of L ov are identified for V T = 6.1 V and 1.02 cm /Vs < μ < 1.08 cm /Vs(Figure S7): indeed, the range for μ ~ 1 cm /Vs is consistent with independent reports for theadopted semiconducting polymer P(NDI2OD-T2) [10] and the range for V T is reasonable andconsistent with the measured transfer curves for our devices. In addition we verified that theinjection length L is larger than L ov , as needed for equation (2) to hold (indeed Equation (2) isa very good approximation of Equation (1) already starting from L ov = L , where the relativeerror is as low as 1.54%). [11] igure S7: Experimental data and fitted curves as a result of our algorithm, for thecombinations corresponding to V T = 6.1 V and a) μ = 1.02 cm /Vs, b) μ = 1.04 cm /Vs, c) μ = 1.06 cm /Vs, d) μ = 1.08 cm /Vs.For these ranges, 0.52 µm < L ov < 0.61 µm, γ is approximately zero (below 0.043) and 2888 Ω< R c,const < 3072 Ω. Different choices for gamma returned extremely similar results:11 For γ = ~ γ : 0.54 µm < L ov < 0.61 µm and 2912 Ω < R c,const < 3022 Ω, For γ = ~ γ : 0.41 µm < L ov < 0.57 µm and 2768 Ω < R c,const < 3126 Ω. In conclusion, we estimate for our high-frequency OFETs an R c ~ 3600-3700 Ω at a biasvoltage of 40 V. Such R c is composed of a constant component estimated as R c,const ~ 3000 Ωand of a bias-dependent component calculated through Equation 2. The corresponding width-normalized contact resistance for our OFET is thus R c W ~ 300 Ωcm at a bias of 40 V in thesaturation regime. 12 onsistence of R c W with the theoretical predictions for f t The experimental values reported here for f t can be analyzed in the frame of a recentlyreported theoretical roadmap for high-frequency operation of organics. [12] With the model ofthat work, we express: f t = μ eff ( V G −V T ) πL ( L + L ov ) where the parameters are defined analogously to the definitions in the main text, and μ eff = μ + μ R c WL C ins ( V G − V T ) The contact resistance is described in accordance with the current-crowding model as inEquation (2), and considered as fully insisting on the source electrode.When plugging in the parameters of the transistors of this work, as determined by the methoddescribed in the previous section, we obtain f t ~ 138 - 146 MHz, which is consistent with theexperimental measurement. We remark that, in the adopted model, the voltage dependence ofthe mobility on the gate voltage is not accounted for. However, such contribution is effectiveonly at a second order, since γ < 0.043. 13 ibliography [1] M. Giorgio, M. Caironi, IEEE Electron Device Lett. , , 953.[2] A. Perinot, M. Caironi, Advanced Science , , 1801566.[3] N.-K. Kim, S.-Y. Jang, G. Pace, M. Caironi, W.-T. Park, D. Khim, J. Kim, D.-Y. Kim,Y.-Y. Noh, Chem. Mater. , , 8345.[4] J. W. Borchert, U. Zschieschang, F. Letzkus, M. Giorgio, M. Caironi, J. N. Burghartz,S. Ludwigs, H. Klauk, presented at , 1-5 Dec. 2018, 2018.[5] A. Yamamura, S. Watanabe, M. Uno, M. Mitani, C. Mitsui, J. Tsurumi, N. Isahaya, Y.Kanaoka, T. Okamoto, J. Takeya, Science Advances , .[6] K. Nakayama, M. Uno, T. Uemura, N. Namba, Y. Kanaoka, T. Kato, M. Katayama, C.Mitsui, T. Okamoto, J. Takeya, Adv Mater Interfaces , , 1300124.[7] M. Uno, T. Uemura, Y. Kanaoka, Z. Chen, A. Facchetti, J. Takeya, Org. Electron. , , 1656.[8] M. Kitamura, Y. Arakawa, Jpn. J. Appl. Phys. , , 01BC01.[9] T. Uemura, T. Matsumoto, K. Miyake, M. Uno, S. Ohnishi, T. Kato, M. Katayama, S.Shinamura, M. Hamada, M.-J. Kang, K. Takimiya, C. Mitsui, T. Okamoto, J. Takeya, Adv.Mater. , , 2983.[10] D. Natali, L. Fumagalli, M. Sampietro, J. Appl. Phys. , , 014501.[11] D. Natali, J. Chen, F. Maddalena, F. García Ferré, F. Di Fonzo, M. Caironi, AdvElectron Mater , , 1600097.[12] A. Perinot, B. Passarella, M. Giorgio, M. Caironi, Adv. Funct. Mater. , n/an/a