Overview of CMOS sensors for future tracking detectors
aa r X i v : . [ phy s i c s . i n s - d e t ] O c t Proceedings of the CTD/WIT 2019PROC-CTD19-134October 17, 2019
Overview of CMOS sensors for future tracking detectors
Ricardo Marco Hern´andez
Instituto de F´ısica Corpuscular (CSIC-UV), Spain
ABSTRACTThe depleted CMOS sensors are emerging as one of the main candidatetechnologies for future tracking detectors in high luminosity colliders. Itscapability of integrating the sensing diode into the CMOS wafer hosting thefront-end electronics allows for reduced noise and higher signal sensitivity. Theyare suitable for high radiation environments due to the possibility of applyinghigh depletion voltage and the availability of relatively high resistivity substrates.The use of a CMOS commercial fabrication process leads to their cost reductionand allows faster construction of large area detectors. A general perspective ofthe state of the art of these devices will be given in this contribution as well as asummary of the main developments carried out with regard to these devices inthe framework of the CERN RD50 collaboration.PRESENTED ATConnecting the Dots and Workshop on Intelligent Trackers (CTD/WIT 2019)Instituto de F´ısica Corpuscular (IFIC), Valencia, SpainApril 2-5, 2019 onnecting the Dots and Workshop on Intelligent Trackers. IFIC (Valencia). April 2-5, 2019
Current large pixel detectors in High Energy Physics, such as the ones which will be part of the ATLASTracker Detector [1] or the CMS Tracker Detector [2] upgrades for the High Luminosity Large HadronCollider (HL-LHC), mostly follow a hybrid aproach. In a hybrid pixel detector the sensor and the readoutelectronics are independent devices connected by means of bump-bonding, as it can be seen in Figure 1.This fact allows for independent development of the sensor and readout electronics technologies to copewith high radiation environments and particle rates. However, bump-bonding is a complex and expensiveassembly process with a limited output rate. Moreover, the overall material budget of several layers restrictsthe accuracy of the particle trajectory measurement in hybrid pixel detectors.Figure 1: Diagram of a hybrid pixel detector.A promising alternative to the current hybrid approach is the so-called depleted monolithic active pixelsensors (MAPS). These kind of sensors integrate the sensing diode and the readout electronics in the sameCMOS wafer, as it is shown in Figure 2. The charge is mainly collected in the depleted area created byapplying reverse bias. The pixel electronics is placed inside an isolated n-well. This sensor technology offersthe possibility of noise reduction and higher signal sensitivity. An important adavntage is that its commercialCMOS fabrication process and its integration leads to an easier production, a large cost reduction and afaster fabrication. Furhtermore, this technology can save material budget due to its reduced thickness.Figure 2: Diagram of a depleted CMOS MAPS sensor.Unfortunately, although the depleted CMOS sensor technology offers several clear advantages, there areseveral aspects of this technology which still have to be improved, as the radiation tolerance, the timingresolution and a fast readout capbility to cope with high particle rates.
The two main n-on-p CMOS sensor design concepts according to their collection electrode size, known as thefill factor, are depicted in Figures 3(a–b). In the large-fill factor structure (Figure 3a), the sensing diode is1 onnecting the Dots and Workshop on Intelligent Trackers. IFIC (Valencia). April 2-5, 2019 made up of the p-substrate and the deep n-well while the electronics are place,d inside the charge collectionwell. High resisitvity substrates, up to 3 kΩ · cm [3], are currently available for this structure. Since a high biasvoltage can be applied to the device, there will be on average shorter drift distances and, as a consequence,a higher radiation tolerance capability. However, the sensor capacitance is larger in this structure, up tohundreds of fF [4] depending on the pixel size, so the noise will be also larger. The electronics will also havelower speed and will need more power to counterbalance this fact. Furthermore, this structure is more proneto cross talk from digital electronics into sensor. (a) (b) Figure 3: Large fill-factor structure (a) and small fill-factor structure (b).On the other hand, the small fill-factor structure (Figure 3b) is characterized by the fact that the sensordiode and the readout electronics are separated by the p-substrate. Higher resistivity substrates, up to8 kΩ · cm [3], can be used with this structure but only low bias voltage can be applied to the substrate.Therefore, longer drift distances are required on average and consequently, this structure tends to a lowerradiation tolerance. Nevertheless, the sensor capacitance is very small, a few fF [4], having a lower noisecompared to the large fill-factor structure. Thus, the electronics implemented in the small fill-factor structurecan be faster and less power-consuming. As it has been aforementioned, there are three important challenges that the depleted CMOS sensor tech-nology has to face: the radiation hardness, the timing resolution and a fast data readout.
The first challenge is to increase the radiation hardness of this sensor technology, currently about 10 eq /cm [5], to reach the equivalent fluences required, for instance, for the Future Circular Collider,which will be larger than 7 · eq /cm [6]. In order to meet this requirement, the CMOS sensorswill need to increase the allowed substrate biasing as well as to access to high resistivity substrates, since thedepleted depth is proportional to the product of these two parameters. In that sense, the effective dopingconcentration of the p-substrate varies with irradiation in a different way for high and low resistivities [7],there is a increase of the depletion depth after irradiation for lower resistivities (up to equivalent fluences ofabout 2 · eq /cm ) whereas the depletion depth decreases after irradiation for higher resistivities.This fact has to be considered in the sensor design process. The backside processing of CMOS sensors is alsoan improtant factor to increase their radiation tolerance since having back bias contact or thinned deviceswill improve their charge collection efficiency. Another relevant aspect for a better radiation hardness wouldbe the possibility of implementing multiple nested wells in order to increase the isolation between the CMOSelectronics and the substrate so that higher bias voltages could be applied to the devices. Finally, the useof CMOS technologies with smaller features sizes would also increase the radiation tolerance of the depletedCMOS sensors. 2 onnecting the Dots and Workshop on Intelligent Trackers. IFIC (Valencia). April 2-5, 2019 The second challenge is to improve the timing resolution of this kind of devices from the current one, lowerthan 10 ns [8][9], to a even better resolution, lower than 5 ns. There are different sources of time uncertaintysuch as the charge collection time, the delay in the readout electronics and the time-walk in the comparator.The reduction of the charge collection time is constrained by the sensor geometry and bias whereas theelectronics delay improvement is limited by the readout electronics power consumption. Therefore, thereis more room for improvement in the reduction of the time-walk by applying new design methods for thediscrimination of the analogue signals like using a time-walk compensated comparator [5], the two-thresholdmethod or the ramp method [8].
The third challenge for this technology is to be able to get a fast readout of the data to deal with highparticle rates in future high luminosity colliders. For instance, a particle rate higher than 1000 MHz/cm isforeseen in the inner pixels layers of the ATLAS tracker detector in the HL-LHC [1]. One of the advantagesof the depleted CMOS sensor technology is the implementation of the full readout architecture in the samedevice to cope with detector demands, not only in terms of particle rates but also for triggering or timestamping. There are different readout architectures such as the column drain architecture implemented inthe LF-Monopix device [10] or the parallel pixel to buffer architecture implemented in the ATLASPix M2device [11]. In the former architecture, the address and time stamp is read out in each pixel and then thedata are moved selectively to the chip periphery whereas in the latter architecture the binary data of eachpixel are moved inmediately to the device periphery and proccessed there upon a trigger arrival. Anothertype of asynchronous readout architecture has been also implemented in the TJ-Malta device [12]. Thesereadout architectures are being tested to optimize the integration, cross-talk and speed of the device. There is a number of commercial foundries available for the fabrication of depleted CMOS sensors. TheCMOS sensors community has already a valuable experience with some of these vendors from several de-velopments carried out. Large fill-factor structures have been produced in LFoundry Srl, ams AG andTSI Semiconductors Corp, in the framework of the ATLAS upgrade and the Mu3e experiments, like theH35Demo device [13], implemented in the ams 350 nm process , the LF-Monopix device [10], implementedin the LFoundry 150 nm process, or the MuPix7 and MuPix8 devices [8], implemented in the ams and TSI180 nm processes, to mention a few ones. Regarding the small fill factor structures, some devices of this typehave been also produced in TowerJazz Ltd. following the TJ 180 nm process as the TJ-Monopix device [10]or the TJ-Malta device [12]. A special type of CMOS technology, the High Voltage Silicon On Insulator, isalso available at X-FAB Semiconductor Foundries AG, several devices have been implemented in the XFAB180 nm process, like the XTB01 device [14]. Finally, it must be emphasized that the current technologiesavailable for CMOS sensors offer feature sizes larger than 130 nm, therefore the radiation tolerance and logicdencity of these devices can be further improved with smaller sizes in the future.
The CERN RD50 is an international collaboration with more than 300 members aimed at developing andcharacterizing radiation-hard semiconductor devices for high luminosity colliders. As it has been mentioned,semiconductor sensors will be exposed in the HL-LHC or FCC to hadron fluences not withstood by currentLHC sensors. Among other research interests, the collaboration has a research line in new detector structures,such as n-on-p sensors, 3D sensors, low gain avalanche photodiodes and depleted CMOS sensors. The latterare a priority for RD50. In fact, several depletion depth and charge collection measurements have been3 onnecting the Dots and Workshop on Intelligent Trackers. IFIC (Valencia). April 2-5, 2019 already carried out with different CMOS devices [15][16]. Moreover, there is a new effort within the RD50collaboration to develop different matrices of pixels and test structures in depleted CMOS processes.Figure 4: Diagram of the RD50-MPW1 depleted CMOS sensor cross-section.A small depleted CMOS sensor prototype, the RD50-MPW1 [17] device of 5 mm by 5 mm, has beenalready developed using the 150 nm LFoundry process in two different resistivities, 500 Ω · cm and 1.9 kΩ · cm.The device has a total thickness of 280 m. The main goals of this design are to test the technology used andverify the validity of novel designs. Figure 4 shows a diagram of the RD50-MPW1 device cross-section, whereit can be seen that the device has a large fill factor structure. The RD50-MPW1 device has test structuresfor Edge-Transient Current Technique (E-TCT) measurements and two independent CMOS pixels matrices.One is a photon counting matrix with 28 by 52 pixels with embedded readout electronics, charge amplifierand discriminator, and a 16-bit counter. The other matrix has 40 by 78 pixels, with a size of 50 µ m by 50 µ m, with embedded readout electronics following a column drain readout architecture similar to the FEI3readout chip [18]. The DAQ development and the device characterization activities related to the RD50-MPW1 device are still ongoing. The sensors are fully functional but the measured leakage current is higherthan expected. Figure 5: Diagram of the RD50-ENGRUN1 device main blocks.Finally, the so-called RD50-ENGRUN1 device, a large area demonstrator, is also being designed withinthe CERN RD50 collaboration using the 150 nm process of Lfoundry. A diagram of the main blocksof the RD50-ENGRUN1 device can be seen in Figure 5. This device has several independent depletedCMOS pixel matrices and test structures. The pixel matrices have different purposes and the main goalspursued in this design are the improvement of the current time resolution with dedicated readout circuits,the implementation of new sensor cross-sections, the assesment of pre-stitching options to incrase the devicesize beyond the reticle size limitation and the increase of radiation tolerance by sensor design and backsideprocessing. The design effort is being carried out by several of the institutions already involved in the RD50CMOS project. The DAQ development and TCAD simulations are also running in parallel with the devicedesign. 4 onnecting the Dots and Workshop on Intelligent Trackers. IFIC (Valencia). April 2-5, 2019 It has been pointed out that the depleted CMOS sensor technology is very promising for future silicon trackingdetectors due to its lower cost, easier and faster detector assembly, faster fabrication turn-around and largermaterial budget saving. However, some challenges must still be faced to cope with future tracking detectorsrequirements in terms of radiation hardness, timing resolution and fast data readout. This sensor technologyis a priority for the CERN RD50 collaboration, which has been involved in the radiation tolerance studyof depleted CMOS sensors. Within the CERN RD50 collaboration, a project to develop depleted CMOSsensors has been started. The RD50-MPW1 chip has been designed and fabricated ans is currently undertest. The RD50-MPW2 has been designed and already submitted aimed at reducing the leakage current andimproving the readout electronics speed. A larger RRD50-ENGRUN1 device is being designed with severalmatrices of pixels with the main goal of improving the timing resolution.
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