Porting of eChronos RTOS on RISC-V Architecture
Shubhendra Pal Singhal, M. Sridevi, N Sathya Narayanan, M J Shankar Raman
PPorting of eChronos RTOS on RISC-VArchitecture
Shubhendra Pal Singhal , M. Sridevi , N Sathya Narayanan , and M JShankar Raman Department of Computer Science and EngineeringNational Institute of Technology, Tiruchirappalli Department of Computer Science and EngineeringIndian Institute of Technology, Madras [email protected]@gmail.com
Abstract. eChronos is a formally verified Real Time Operating System(RTOS) designed for embedded micro-controllers. eChronos was targetedfor tightly constrained devices without memory management units. Cur-rently, eChronos is available on proprietary designs like ARM, PowerPCand Intel architectures. eChronos is adopted in safety critical systems likeaircraft control system and medical implant devices. eChronos is one ofthe very few system software’s not been ported to RISC-V. RISC-V isan open-source Instruction Set Architecture (ISA) that enables new eraof processor development. Many standard Operating Systems, softwaretool chain have migrated to the RISC-V architecture. According to thelatest trends[4], RISC-V is replacing many proprietary chips. As a se-cure RTOS, it is attractive to port on an open-source ISA. SHAKTI andPicoRV32 are some of the proven open-source RISC-V designs available.Now having a secure RTOS on an open-source hardware design, designedbased on an open-source ISA makes it more interesting. In addition tothis, the current architectures supported by eChronos are all proprietarydesigns [14], and porting eChronos to the RISC-V architecture increasesthe secure system development as a whole. This paper, presents an ideaof porting eChronos on a chip which is open-source and effective, thusreducing the cost of embedded systems. Designing a open-source systemthat is completely open-source reduces the overall cost, increased thesecurity and can be critically reviewed. This paper explores the designand architecture aspect involved in porting eChronos to RISC-V. Theauthors have successfully ported eChronos to RISC-V architecture andverified it on spike[10]. The port of RISC-V to eChronos is made avail-able open-source by authors[16]. Along with that, the safe removal ofarchitectural dependencies and subsequent changes in eChronos are alsoanalyzed.
Keywords: eChronos, Porting, Real Time Operating Systems, RISC-V, SHAKTI a r X i v : . [ c s . O S ] D ec Shubhendra Pal Singhal
Porting is the process of converting the software for the another architecture.A software has many exceptions and forms of programming specific to the ar-chitecture like memory or register allocation. To be able to run such executablefile, we need porting. There are many OS porting techniques available in theliterature [5] that follow trial and error approach. In this paper, we have usedthe hit and trial approach for porting eChronos on an open-source architectureRISC-V[11,13].
The eChronos RTOS is a real-time operating system (RTOS) [14]. It is intendedfor tightly resource-constrained devices without memory management units andvirtual memory support. Also, RTOS code base is designed to be highly modularso that only the minimal amount of code necessary is ever compiled into a givensystem image[14]. The eChronos RTOS is highly configurable and functional asshown in FIG 1[3].
Fig. 1. eChronos RTOS functionality
RISC-V is an open-source hardware ISA based on Reduced Instruction Set Com-puter (RISC) principles. RISC-V is a layered and extensible open-source ISA orting of eChronos RTOS on RISC-V Architecture 3 which means that it can support the implementation of well defined extensionsfor a given application. RISC-V offers a very flexible usage of instruction setwhich adds to upto RISC-V becoming more popular[4]. RISC-V is modular andflexible, which reduces the effort to develop the ancillary software for a specificprocessor.
Porting of OS is a time consuming process as it involves a changes to big andcomplex programs. Porting every specific program seems to be a bit irrational.So the solution to such a complex problem are the modern day compilers, whichtranslates the high level language program to a platform independent code un-like the traditional compilers translating the code directly to the machine code.The intermediate language can then execute all programs and it gets translatedinto a sequence of machine code by a code generator to create a executable file.The use of intermediate code enhances the portability of the compiler, becauseonly the machine dependent code (the interpreter or the code generator) of thecompiler needs to be ported instead of porting the program itself. The remainingpart of the code in the compiler can be treated as an intermediate code and thenprocessed by the ported code interpreter. This reduces design efforts, becausethe machine independent code just needs to be developed only once to create aportable intermediate code. An interpreter is less complex to code and it followsa certain algorithm avoiding the need to be specifically port for every singleprogram [7]. A software can be compiled and linked from source code for variousoperating systems and architectures. Real Time Operating System files are allarchitecture dependent. A small mistake in port files will lead to an easy systemcrash. [5,12].
The subsequent sections explain the step-wise process involved in the porting ofeChronos for RISC-V architecture.
The following are the prerequisites1 A Linux operating system running on personal computer with 4GB RAM.2 A GNU based environment, that has all necessary software packages men-tioned in [10].
The following steps need to be done to run eChronos on an emulator,
Shubhendra Pal Singhal
Installation of RISC-V emulator
Follow the following steps that are listedbelow for the installation of RISC-V tools [1,2,9]:1
The following packages are required for the RISC-V tools: autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-devlibusb-1.0-0-dev gawk build-essential bison flex texinfo gperf libtool patchutilsbc zlib1g-dev device-tree-compiler pkg-configlibglib2.0-dev zlib1g-dev libpixman-1-dev2
Set up a directory for the RISC-V tools, and the RISC-V envi-ronment variable, which we refer to in future steps. mkdir RISC-Vcd RISC-Vexport RISC-V= { P W D } Get the RISC-V tools cd RISC − V git clone https://github.com/RISC-V/RISC-V-gitcd RISC-V-toolsgit submodule update –init –recursive4 Get RISC-V qemu sources, and build them: cd RISC − V /RISC − V − tools git clone https://github.com/heshamelmatary/RISC-V-qemu.gitcd RISC-V-qemugit checkout sfencegit submodule update –init dtc./configure –target-list=RISC-V64-softmmu,RISC-V32-softmmu –prefix= RISC − V make -j8 && make install5 Build the 64-bit toolchain cd RISC-V/RISC-V-toolssed -i ’s/build project RISC-V-gnu-toolchain –prefix=$RISC-V/build projectRISC-V-gnu-toolchain –prefix=RISC-V –with-arch=rv64imafdc –with-abi=lp64’./build.sh6
Installation of eChronos
Download and install the eChronos[4]. orting of eChronos RTOS on RISC-V Architecture 5
Fig. 2.
Flow Diagram of eChronos Shubhendra Pal Singhal
The FIG.2 shows the system diagram of eChronos. The following steps explainFIG 2[8]. that help eChronos produce an executable file (of the test program)[14]:1 Ensure that there is no break in the packages installed earlier and the depen-dencies are installed properly. A yml file is created for the purpose of testingthe version of the dependencies installed and whether they are suitable forrunning eChronos or not? : e.g. running 3.4 version of python needs to beverified.2 / x.py build packages executes x.py file which uses the skeleton of the systemas a reference for the order of installation. The following output files will beproduced by x.py : • release /prj − < version > .zip • release / < rtos − f oo > − < version > .zip • release / < build − name > − < version > .zip3 If the installation shows any error related to traceback like Traceback (mostrecent call last):File ”prj/app/prj.py”, line 1293, in start sys.exit(main()), then the installa-tion or dependencies are not installed properly. Follow the earlier steps againproperly.4 After prj errors are removed, we have to ensure that the class standard cfg.pyshould contain the RISC-V architecture. Simultaneously, spike[10] emulatoris installed. The test setup.sh script downloads the package eChronos fromGithub. It contains travis to ensure that if package is missing then the al-ternative can be downloaded i.e. the posix version[14].5 Components folder:api-conditions, context-switch-RISC-V, docs, error, interrupt-event-RISC-V,message-queue, rigel, rigel.py, stack-RISC-V, task, timer-RISC-V are thenecessary components that will be created once the script runs properly.6 After ensuring a proper installation of eChronos, we test our sample pro-gram. prj/app/prj.py build < example name > command runs the test caseon eChronos RTOS and produces the binary file which can be tested on spike.7 The block ”Test case runs” is explained in detail in section 4.1.3. Porting requires the understanding of the flow of data and the subsequentchanges in the system related to architecture. As eChronos is architecture depen-dent, there were many changes pertaining to specificity of the architecture like : orting of eChronos RTOS on RISC-V Architecture 7
General architecture similar to 8086 consists of extra data segment by default,but in case of RISC-V architecture, it has to be declared explicitly. The defaultedata (extra data segment) initialization is missing from RISC-V architecture sothe edata declaration had to be removed from every file in eChronos.[6]. Like-wise, there were some architecture dependent terms which had to be modified,so as to provide support to eChronos for RISC-V. eChronos initially could run only one program(test case) i.e. concurrency of taskA and task B. eChronos could not run any generic program like ”Hello World”.Porting eChronos on RISC-V, thus became difficult because RISC-V cannotsupport the execution of concurrent programs. So porting eChronos on RISC-V meant that we have to change the test case to a generic one which RISC-Vcan support. Thus, eChronos was first changed to support generic programs like”Hello World” and then the subsequent execution of its exe file on the RISC-Vcould intimate whether eChronos is ported successfully or not.
The components section of eChronos con-sists of libraries like mutex, context switching and other concurrency supportivepackages which are not used by our sample program. We removed all the unnec-essary packages and removed their declarations from all the files like x.py coreconfiguration, prj.py file beacuse ”build packages” command would take unnec-essary time executing irrelevant packages otherwise.After ensuring correct set of packages like rigel, api-conditions, errors, doc etc.we try to modify the test case. Test case has only one external dependency i.e.print statement. ”printf” could used as one of the options but then gcc supportfor eChronos needs to be ensured which leads to multiple dependency issues andthese issues might be difficult to track. Also, we need to port eChronos with min-imal set of library dependencies and thus, we configured the print function[16]by using write() command of stdio library which is comparatively a less complexfunction than printf function of gcc. Thus, a test program with least dependencyis programmed and now, we have to produce its executable file to ensure thatevery interlinked package is working properly. This implies that if its executablefile is generated, then removal of unnecessary packages was a success plus thetest case is running properly on eChronos else we have to again solve the packageerror and keep on trying(hit and trial). Further, if risc-v linker along with thisexecutable file, generates a system dump (which executes properly on spike too)then eChronos is successfully ported on RISC-V.
Initialization of packages
The main principle of porting is to understandwhat lines of code to modify in accordance with the architecture and whatdependencies needs to be taken into consideration. In this case the prj tool
Shubhendra Pal Singhal written in python is the initial script which initializes all the packages presentand creates the required directories. When prj tools runs in eChronos, project.prjis the skeleton file which runs x.py file. It states all the dependencies of packagesthat is required by the system to function properly. There are many componentslike errors, api-conditions etc which are addressed by eChronos and needs to beinitialized. x.py helps in initialization of these packages.. / x.py build packagesThe command . / x.py will initialize the packages that are mentioned in skeletonof your system in x.py file. For instance : For RISC-V, rigel is the system namewhich has packages like error, test case etc. mentioned in x.py file, which helpsin initial creation of sub-directories. This helps to create the build structure ina modular fashion where every module consists of .exe files of different packagesinitialized in x.py file. Running an application on eChronos prj/app/prj.py build machine-RISC-V-common.example.hello is the command that runs the test case by first creatingan exe file of the test case. After creating .exe files of packages using build com-mand, we run test case using these packages. This exe file created by OS isarchitecture dependent and may raise some errors if OS files are corrupted ornot ported correctly.
Fig. 3. machine-riscv-common.example.hello.prxorting of eChronos RTOS on RISC-V Architecture 9
Test case is stored in the hello.c file. machine-RISC-V-common.example.hello.prxconsists of skeleton of how the test case should run as shown in Fig3. It consistsof the modules names which needs to be executed in the sequential order. Thiscommand searches for .prx file which contains all the files to be used for runningyour program stored in the system.We will illustrate this using our model rigel.1.) .prx file instructs the system to compile debug.c in generic folder, hello.c ingeneric folder, default-linker.py in RISC-V folder and build.py as mentioned inmachine-RISC-V-common.example.hello.prx file.2.) RISC-V.default-linker means that we should go to the RISC-V folder and rundefault-linker.py file. One thing must remembered that only .c, .py and otherhigh level language files can run in the .prx file.
Data flow of a running application
This section tries to explain the dataflow in eChronos, when a test case run. The file ”debug.h” consists of initializa-tion of function : debug print and debug.c consists of its declaration. The hello.ci.e. the test case uses debug.h as its header file and uses the function debug printto print ”Hello world”. This requires the compilation of header files.1.) build.py file takes the system files and some other helper files like debug.h tocompile, assemble and run your hello.c file in generic folder.2.) hello.c file just wants to print ”Hello World”. So for printing the commandprintf is not used, rather we have created the debug.c file where the print com-mand has been declared. printf command is not used because it is a part ofgcc library which is yet not ported to RISC-V. So a generic print statement isdeclared in debug file.3.) The compilation of all libraries is over. Rigel model along with its componentsis build and the libraries used in the test case are also compiled. Only properlinking of all these files is left. The linker file default.ld is created where the link-ing occurs according to RISC-V architecture. Linker file of different architectureswas referred while making default.ld. This linker file assumed ”edata” one of thevariables to be declared by default but RISC-V does not support any defaultdeclarations. So we changed ”edata=null” and linking errors were solved. Thus,all the compiled files were linked.
As soon as you hit the first command, the out folder is created with rtos-
References
1. Andrew Waterman, Yunsup Lee, D.P.K.A.: The risc-v instruction set manual, vol-ume i: Base user-level isa. Tech. rep., UCB/EECS-2011-62, EECS Department,University of California, Berkeley (May 2016), https://ts.data61.csiro.au/projects/TS/echronos/ , [Online; last accessed 30-Dec-2018]4. Bradbury, A.: The future of operating systems on risc-v (May 24, 2019), , [Online; last accessed 24-May-2019]orting of eChronos RTOS on RISC-V Architecture 115. H Marcondes, AS Hoeller, L.W.A.F.: Operating systems portability:8 bits and beyond. vol. 50, pp. 124–130. 2006 IEEE Conference onEmerging Technologies and Factory Automation, IEEE (Sept 2006).https://doi.org/10.1109/ETFA.2006.355371, [Online; last accessed 23-Dec-2018]6. Holothurion: Porting (22 July 2019), https://en.wikipedia.org/wiki/Porting ,[Online; last accessed 23-July-2019]7. Johnson, D.: Porting hyperkernel to the arm architecture. Tech. rep., Uni-versity of Washington-CSE (2017), https://pdfs.semanticscholar.org/bb86/ea6a08c9b8c09a600367785b27acefff710d.pdf.https:/ , [Online; last accessed 2-Jan-2019]8. June Andronick, Corey Lewis, C.M.: Controlled owicki-gries concurrency:reasoning about the preemptible echronos embedded operating system.pp. 10–24. MARS 2015 (2015). https://doi.org/10.4204/EPTCS.196.2,https://arxiv.org/abs/1511.041709. Kanter, D.: Risc-v offers simple- modular isa. Tech. rep., The Lin-ley Group MICROPROCESSOR (March 2016), https://riscv.org/2016/04/risc-v-offers-simple-modular-isa/ , [Online; last accessed 3-Jan-2019]10. Keller, B.: Risc-v, spike, and the rocket core (Fall 2013), , [Online; last accessed 27-Dec-2018]11. N. Gala, A. Menon, R.B.G.S.M.V.K.: Shakti processors: An open-source hard-ware initiative. 29th International Conference on VLSI Design and 2016 15th In-ternational Conference on Embedded Systems (VLSID), Kolkata, India,, IEEE(Jan 2016). https://doi.org/10.1109/VLSID.2016.130, [Online; last accessed 13-Dec-2018]12. RIOT-OS: Family:arm.riot-os (Mar 27, 2017), https://github.com/RIOT-OS/RIOT/wiki/Family:-ARM , [Online; last accessed 7-Jan-2019]13. RISC-V: Risc-v gnu-toolchain (2017), https://github.com/riscv/riscv-gnu-toolchain , [Online; last accessed 4-April-2019]14. eChronos RTOS: The echronos real-time operating system (2017), https://github.com/echronos/echronos , [Online; last accessed 4-April-2019]15. Shubhendra Pal Singhal, M.S.: Porting of echronos rtos on risc-v architecture.preprint at (2019), https://arxiv.org/abs/1908.11648
16. Singhal, S.P.: Porting and testing on risc-v (2018), https://github.com/singhalshubh/Porting-and-Testing-on-RISCV-https://github.com/singhalshubh/Porting-and-Testing-on-RISCV-