Progress on the ISIS synchrotron digital low level RF system upgrade
Andrew Seville, David B. Allen, Ian S. K. Gardner, Robert J. Mathieson
PROGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF
Abstract
The ISIS synchrotron at the Rutherford Appleton Lboratory in the UK now routinely uses a dual harmonic RF system to accelerate µA to run two target stations simultaneously. The accelation in the ISIS synchrotron is provided by six fundmental frequency (1RF) and four second harmonic (2RF) RF cavities. The 1RF systems are required to sweep from 1.3MHz to 3.1MHz during the 10ms acceleration period, repeated at 50Hz, with the 2RF syste2.6MHz to 6.3MHz. The existing analogue LLRF control system has been in service for over 30 years and is now showing some signs of old age and spare parts are becoing difficult to source. In order to overcome this and to give more stable each of the cavities, changes have been made to the LLRF control system. A new FPGA based combined frequency law generator / master oscillator has been implemented using “off - thebased FlexRIO modules. This initial design has been successfully used during the ISIS operational cycles for over three years. This paper reports on the commissioning of the FlexRIO system, the implementation and recent testing of the cavity control lal replacement of remaining parts of the LPRF system.The ISIS synchrotron supplied first beam toin December 1984ring where they abefore extraction and transport to the target station (TS1). The proton beam iloaded RF cavities.current ranging from 200A to 2000A during the 10ms accelerating period to tune the cavity from 1.3MHz at injection to 3.1MHz at extraction. Since then, there have been several upgrades to the machine. These include the addition, at the turn of the millennium, of four second harmonic (H=4)to 6.3MHz. These enabled the stable acceleration of the higher beam current needed to supply a second target station (TS2 at 10Hz) and whilst maintaining the same mean beam current to TS1 andtarget at 40Hz.The ISIS Synchrotron LLRF system provides the RF signal to each of the sweep is produced by the(FLG) which takes in aone of the Synchrotron dipole to give B and then mapped to an output voltage corr OGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF A. Seville † The ISIS synchrotron at the Rutherford Appleton Lboratory in the UK now routinely uses a dual harmonic RF system to accelerate beam currents in excess of 230 A to run two target stations simultaneously. The accelation in the ISIS synchrotron is provided by six fundmental frequency (1RF) and four second harmonic (2RF) RF cavities. The 1RF systems are required to sweep from 1.3MHz to 3.1MHz during the 10ms acceleration period, repeated at 50Hz, with the 2RF syste2.6MHz to 6.3MHz. The existing analogue LLRF control system has been in service for over 30 years and is now showing some signs of old age and spare parts are becoing difficult to source. In order to overcome this and to give more stable control of the phase of the RF voltage at each of the cavities, changes have been made to the LLRF control system. A new FPGA based combined frequency law generator / master oscillator has been implemented the - shelf” National Instruments PXIbased FlexRIO modules. This initial design has been successfully used during the ISIS operational cycles for three years. This paper reports on the commissioning of the FlexRIO system, the implementation and recent testing of the cavity control lal replacement of remaining parts of the LPRF system. INTRODUCTION
The ISIS synchrotron supplied first beam toin December 1984. 70MeV ring where they are stripped and accelerbefore extraction and transport to the target station (TS1). The proton beam is accelerated by sixloaded RF cavities. These current ranging from 200A to 2000A during the 10ms celerating period to tune the cavity from 1.3MHz at injection to 3.1MHz at extraction. Since then, there have been several upgrades to the machine. These include the addition, at the turn of the millennium, of four second (H=4) RF cavitiesto 6.3MHz. These enabled the stable acceleration of the higher beam current needed to supply a second target station (TS2 at 10Hz) and whilst maintaining the same mean beam current to TS1 andHz.
The ISIS Synchrotron LLRF system provides the RF signal to each of the 10is produced by the(FLG) which takes in a
B(cid:2) one of the Synchrotron dipole to give B and then mapped to an output voltage corr
OGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF † , D. B. Allen The ISIS synchrotron at the Rutherford Appleton Lboratory in the UK now routinely uses a dual harmonic beam currents in excess of 230 A to run two target stations simultaneously. The accelation in the ISIS synchrotron is provided by six fundmental frequency (1RF) and four second harmonic (2RF) RF cavities. The 1RF systems are required to sweep from 1.3MHz to 3.1MHz during the 10ms acceleration period, repeated at 50Hz, with the 2RF systems sweeping from 2.6MHz to 6.3MHz. The existing analogue LLRF control system has been in service for over 30 years and is now showing some signs of old age and spare parts are becoing difficult to source. In order to overcome this and to control of the phase of the RF voltage at each of the cavities, changes have been made to the LLRF control system. A new FPGA based combined frequency law generator / master oscillator has been implemented shelf” National Instruments PXIbased FlexRIO modules. This initial design has been successfully used during the ISIS operational cycles for three years. This paper reports on the commissioning of the FlexRIO system, the implementation and recent testing of the cavity control loops and plans for the gradal replacement of remaining parts of the LPRF system.
INTRODUCTION
The ISIS synchrotron supplied first beam to. 70MeV H (cid:4) ions are injere stripped and accelerbefore extraction and transport to the target station (TS1). s accelerated by sixThese RF cavities acurrent ranging from 200A to 2000A during the 10ms celerating period to tune the cavity from 1.3MHz at injection to 3.1MHz at extraction. Since then, there have been several upgrades to the machine. These include the addition, at the turn of the millennium, of four second RF cavities [1], sweepingto 6.3MHz. These enabled the stable acceleration of the higher beam current needed to supply a second target station (TS2 at 10Hz) and whilst maintaining the same mean beam current to TS1 and the intermediate muon The ISIS Synchrotron LLRF system provides the RF 10 accelerating cavities. The RF is produced by the Frequency Law Generator (cid:2) signal from a search coil within one of the Synchrotron dipole magnets.to give B and then mapped to an output voltage corr OGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF SYSTEM UPGRADE . Allen, I. S. K. Gardner, R. J. Mathieson, STFC
The ISIS synchrotron at the Rutherford Appleton Lboratory in the UK now routinely uses a dual harmonic beam currents in excess of 230 A to run two target stations simultaneously. The accelation in the ISIS synchrotron is provided by six fundmental frequency (1RF) and four second harmonic (2RF) RF cavities. The 1RF systems are required to sweep from 1.3MHz to 3.1MHz during the 10ms acceleration period, ms sweeping from 2.6MHz to 6.3MHz. The existing analogue LLRF control system has been in service for over 30 years and is now showing some signs of old age and spare parts are becoing difficult to source. In order to overcome this and to control of the phase of the RF voltage at each of the cavities, changes have been made to the LLRF control system. A new FPGA based combined frequency law generator / master oscillator has been implemented shelf” National Instruments PXI - expbased FlexRIO modules. This initial design has been successfully used during the ISIS operational cycles for three years. This paper reports on the commissioning of the FlexRIO system, the implementation and recent oops and plans for the gradal replacement of remaining parts of the LPRF system. INTRODUCTION
The ISIS synchrotron supplied first beam to the target re injected into the re stripped and accelerated to 800MeV before extraction and transport to the target station (TS1). s accelerated by six, H=2, ferrite cavities are biased with a current ranging from 200A to 2000A during the 10ms celerating period to tune the cavity from 1.3MHz at injection to 3.1MHz at extraction. Since then, there have been several upgrades to the machine. These include the addition, at the turn of the millennium, of four second , sweeping from 2.6MHz to 6.3MHz. These enabled the stable acceleration of the higher beam current needed to supply a second target station (TS2 at 10Hz) and whilst maintaining the same the intermediate muon The ISIS Synchrotron LLRF system provides the RF accelerating cavities. The RF cy Law Generator signal from a search coil within . This is integrated to give B and then mapped to an output voltage corr
OGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF SYSTEM UPGRADE
I. S. K. Gardner, R. J. Mathieson, STFC
The ISIS synchrotron at the Rutherford Appleton La-boratory in the UK now routinely uses a dual harmonic beam currents in excess of 230 A to run two target stations simultaneously. The acceler-ation in the ISIS synchrotron is provided by six funda-mental frequency (1RF) and four second harmonic (2RF) RF cavities. The 1RF systems are required to sweep from 1.3MHz to 3.1MHz during the 10ms acceleration period, ms sweeping from 2.6MHz to 6.3MHz. The existing analogue LLRF control system has been in service for over 30 years and is now showing some signs of old age and spare parts are becom-ing difficult to source. In order to overcome this and to control of the phase of the RF voltage at each of the cavities, changes have been made to the LLRF control system. A new FPGA based combined frequency law generator / master oscillator has been implemented express based FlexRIO modules. This initial design has been successfully used during the ISIS operational cycles for three years. This paper reports on the commissioning of the FlexRIO system, the implementation and recent oops and plans for the gradu-al replacement of remaining parts of the LPRF system. target cted into the ated to 800MeV before extraction and transport to the target station (TS1). ferrite re biased with a current ranging from 200A to 2000A during the 10ms celerating period to tune the cavity from 1.3MHz at injection to 3.1MHz at extraction. Since then, there have been several upgrades to the machine. These include the addition, at the turn of the millennium, of four second from 2.6MHz to 6.3MHz. These enabled the stable acceleration of the higher beam current needed to supply a second target station (TS2 at 10Hz) and whilst maintaining the same the intermediate muon The ISIS Synchrotron LLRF system provides the RF accelerating cavities. The RF cy Law Generator signal from a search coil within is integrated to give B and then mapped to an output voltage corre- sponding to the RF frequency. This voltage is then summed with the outputs of the phase loop (which damps beam dipole oscillations), the radial loop (beam) and the bunch length loop (designed to damp quarupole beam oscillations and ease extraction between the two bunches) and then fed into the Master Oscillator. Within the beam loops, the RF system hascontrol loops to control the amplitude, phase and tuning of each RF cavity as depicted in figure 1.
Figure 1
The original analogue controls for these systems have been in place, now, for overrecent 2RF controls are showing signs of ageing and sourcing replacement components is becoming increaingly difficult.
INITIAL
Following the commissioning of the 2RF systems in 2004, plans were made to design FLG and Master Oscillator [2] modulesbased on the then new Lattice FPGA devices. These moules were never fully commissioned, partly due to staff turnover, but their designs were used to inform the later DigitalAt thisforward beam compensation (FFBC) units. These had been installed to compensate for beam loading of the RF cavities as beam intensities increased by applying a varible gain and dsumming with the RF drive signal to the cavity from the LLRF system. tal filter implementedwithin a National InstrumentIt soon becammight be able to provide aof the LLRF control system. To this end an initial Master Oscito investigate the was pr ________________________________ † [email protected]
OGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF SYSTEM UPGRADE
I. S. K. Gardner, R. J. Mathieson, STFC sponding to the RF frequency. This voltage is then summed with the outputs of the phase loop (which damps beam dipole oscillations), the radial loop (whichbeam) and the bunch length loop (designed to damp quarupole beam oscillations and ease extraction between the two bunches) and then fed into the Master Oscillator. Within the beam loops, the RF system hastrol loops to control the amplitude, phase and tuning each RF cavity as depicted in figure 1.
Figure 1: ISIS Synchrotron LLRF Co
The original analogue controls for these systems have been in place, now, for overrecent 2RF controls are showing signs of ageing and sourcing replacement components is becoming increaingly difficult.
INITIAL OBSOLESCENCE
Following the commissioning of the 2RF systems in 2004, plans were made to design FLG and Master Oscillator [2] modulesbased on the then new Lattice FPGA devices. These moules were never fully commissioned, partly due to staff turnover, but their designs were used to inform the later Digital - LPRF upgrade project.At this time, plans were made to upgrade the feedforward beam compensation (FFBC) units. These had been installed to compensate for beam loading of the RF cavities as beam intensities increased by applying a varible gain and delay to a beam intensity signal, before summing with the RF drive signal to the cavity from the LLRF system. The upgrade design tal filter implementedwithin a National InstrumentIt soon became apparent that the FlexRIO platform might be able to provide aof the LLRF control system. To this end an initial Master Oscillator design was implemented on the to investigate the was produced in around six months, which co ___________________________________________ † [email protected]
OGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF
I. S. K. Gardner, R. J. Mathieson, STFC, Didcot sponding to the RF frequency. This voltage is then summed with the outputs of the phase loop (which damps beam dipole oscillations), the ch maintains the horizontal position of the beam) and the bunch length loop (designed to damp quarupole beam oscillations and ease extraction between the two bunches) and then fed into the Master Oscillator. Within the beam loops, the RF system hastrol loops to control the amplitude, phase and tuning each RF cavity as depicted in figure 1.
ISIS Synchrotron LLRF Co
The original analogue controls for these systems have been in place, now, for over recent 2RF controls are showing signs of ageing and sourcing replacement components is becoming increa
OBSOLESCENCE
Following the commissioning of the 2RF systems in 2004, plans were made to design FLG and Master Oscillator [2] modulesbased on the then new Lattice FPGA devices. These moules were never fully commissioned, partly due to staff turnover, but their designs were used to inform the later upgrade project. time, plans were made to upgrade the feedforward beam compensation (FFBC) units. These had been installed to compensate for beam loading of the RF cavities as beam intensities increased by applying a varielay to a beam intensity signal, before summing with the RF drive signal to the cavity from the he upgrade design tal filter implemented on the new FlexRIO FPGA within a National Instruments PXI crate.e apparent that the FlexRIO platform might be able to provide a means ofof the LLRF control system. To this end an initial Master lator design was implemented on the to investigate the potential for this approach.duced in around six months, which co ___________ † [email protected]
OGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF
Didcot, UK sponding to the RF frequency. This voltage is then summed with the outputs of the 3 beam loops: the bphase loop (which damps beam dipole oscillations), the the horizontal position of the beam) and the bunch length loop (designed to damp quarupole beam oscillations and ease extraction between the two bunches) and then fed into the Master Oscillator. Within the beam loops, the RF system hastrol loops to control the amplitude, phase and tuning each RF cavity as depicted in figure 1.
ISIS Synchrotron LLRF Control System.
The original analogue controls for these systems have 35 years. Even the more recent 2RF controls are showing signs of ageing and sourcing replacement components is becoming increa
OBSOLESCENCE PLANNING
Following the commissioning of the 2RF systems in 2004, plans were made to design replacement units for the FLG and Master Oscillator [2] modules. based on the then new Lattice FPGA devices. These moules were never fully commissioned, partly due to staff turnover, but their designs were used to inform the later time, plans were made to upgrade the feedforward beam compensation (FFBC) units. These had been installed to compensate for beam loading of the RF cavities as beam intensities increased by applying a varielay to a beam intensity signal, before summing with the RF drive signal to the cavity from the he upgrade design included a swept digon the new FlexRIO FPGA PXI crate. e apparent that the FlexRIO platform means of replacement for more of the LLRF control system. To this end an initial Master lator design was implemented on the FPGA potential for this approach.duced in around six months, which co
OGRESS ON THE ISIS SYNCHROTRON DIGITAL LOW LEVEL RF UK sponding to the RF frequency. This voltage is then 3 beam loops: the beam phase loop (which damps beam dipole oscillations), the the horizontal position of the beam) and the bunch length loop (designed to damp quad-rupole beam oscillations and ease extraction between the two bunches) and then fed into the Master Oscillator. Within the beam loops, the RF system has individual trol loops to control the amplitude, phase and tuning trol System.
The original analogue controls for these systems have 35 years. Even the more recent 2RF controls are showing signs of ageing and sourcing replacement components is becoming increas-
PLANNING
Following the commissioning of the 2RF systems in replacement units for the . These were based on the then new Lattice FPGA devices. These mod-ules were never fully commissioned, partly due to staff turnover, but their designs were used to inform the later time, plans were made to upgrade the feed - forward beam compensation (FFBC) units. These had been installed to compensate for beam loading of the RF cavities as beam intensities increased by applying a varia-elay to a beam intensity signal, before summing with the RF drive signal to the cavity from the included a swept digi-on the new FlexRIO FPGA module, e apparent that the FlexRIO platform replacement for more of the LLRF control system. To this end an initial Master FPGA modulepotential for this approach. The design duced in around six months, which compared sponding to the RF frequency. This voltage is then eam phase loop (which damps beam dipole oscillations), the the horizontal position of the d-rupole beam oscillations and ease extraction between the idual trol loops to control the amplitude, phase and tuning The original analogue controls for these systems have 35 years. Even the more recent 2RF controls are showing signs of ageing and s-Following the commissioning of the 2RF systems in replacement units for the These were d-ules were never fully commissioned, partly due to staff turnover, but their designs were used to inform the later - forward beam compensation (FFBC) units. These had been installed to compensate for beam loading of the RF a-elay to a beam intensity signal, before summing with the RF drive signal to the cavity from the i-, e apparent that the FlexRIO platform replacement for more of the LLRF control system. To this end an initial Master module sign pared avourably to the 3 years it had taken for the Lattice FPGA The use of the FlexRIO platform fitlimited resources: a small RF team already supporoperation of an operational machine running 24/7 for 200 days per year. Buying “offsave considerable development time. View licence agreement in place withments, which includeopment modcommunity on site at RALon both for su DIGITAL LLRF DEVELOP
A staged implemewas adopted, starting Oscillator (MO), and then replace more and more of the existing sysuited to the reconfigurable nand would also allow confgrow followprojects using Diagnostics the deployed digital sywould have to be siFPGA code period of dbeam, howevusually schedeach user cycle.The MO code was imodule and front end tran2013. In August 2014, this had been ethe functionality of theMaster Oscillator, within crate, as shown in figure 2.
Figure 2: Digital FLG /Master Oscillator
The
B(cid:2) and Beam loop signals were fed into a NI5734 4channel digitiser adapter, amodule, on which a 17 bit word was gesponding to the frequency increment (transmitted across the PXIPeer (P2P) streaming to a and used as the counter increment in a DDS, which was then output on one of the Transceiver adaptersystem in place of the origiA second LO system was then adfrequency doubler to generate the bly to the 3 years it had taken for the Lattice FPGA - based design to be built and configured.The use of the FlexRIO platform fitlimited resources: a small RF team already supporoperation of an operational machine running 24/7 for 200 days per year. Buying “offconsiderable development time. View licence agreement in place withwhich includes use ofdule, so there was a strong Laty on site at RALfor support and for f DIGITAL LLRF DEVELOP staged implementation of the d, starting with tor (MO), and then place more and more of the existing sythe reconfigurable nand would also allow confwing some reliabiprojects using Windows PXI controllers section. The process of reverting backthe deployed digital systemto be simple and was designeddevelopment. Testing the syver, was limited to the mduled within a 2each user cycle.
The MO code was imule and front end trangust 2014, this had been etionality of the beam loop summing aMaster Oscillator, within crate, as shown in figure 2. igital FLG /Master Oscillator and Beam loop signals were fed into a NI5734 4channel digitiser adapter, amodule, on which a 17 bit word was gesponding to the frequency increment (transmitted across the PXIPeer (P2P) streaming to a nd used as the counter increment in a DDS, which was then output on one of the ceiver adapter and tem in place of the origiA second LO system was then adcy doubler to generate the bly to the 3 years it had taken for the design to be built and configured.The use of the FlexRIO platform fittedlimited resources: a small RF team already supporoperation of an operational machine running 24/7 for 200 days per year. Buying “off - the - shelf” hardware should considerable development time. STFC haView licence agreement in place withuse of the LabView there was a strong Laty on site at RAL, with much experfor future succession pla DIGITAL LLRF DEVELOP tation of the digital LLRF system with the replacement of the Mator (MO), and then expanding the digplace more and more of the existing sythe reconfigurable nature of the FPGA devicesand would also allow confidence in the new system to reliability issues with previous PXI controllers The process of reverting backtem to the analogue ple and fast, if necdesigned offline throughout the first . Testing the syer, was limited to the machine within a 2 -
3 day periodmplemented on a single FPGA ule and front end transceiver adapter in Dgust 2014, this had been exbeam loop summing aMaster Oscillator, within two FPGA mocrate, as shown in figure 2. igital FLG /Master Oscillator and Beam loop signals were fed into a NI5734 4channel digitiser adapter, attached to the FLG FPGA module, on which a 17 bit word was gesponding to the frequency increment ( (cid:5) transmitted across the PXI - express backPeer (P2P) streaming to a Local Oscilnd used as the counter increment in a DDS, which was then output on one of the DAC channels of the NI5781 fed into the existing analogue tem in place of the original Master oscillatorA second LO system was then added cy doubler to generate the frequebly to the 3 years it had taken for the bespokedesign to be built and configured.ted in well with our limited resources: a small RF team already supporoperation of an operational machine running 24/7 for 200 shelf” hardware should STFC have a LaView licence agreement in place with National InLabView FPGA dthere was a strong LabView user , with much experience to draw ture succession planning. DIGITAL LLRF DEVELOPMENT igital LLRF system ment of the Mathe digital system place more and more of the existing system. This wasture of the FPGA devicesdence in the new system to ity issues with previous PXI controllers within our Beam The process of reverting back logue LLRF sycessary. The initial throughout the first . Testing the system live with chine physics shifts 3 day period at the end of plemented on a single FPGA ceiver adapter in December, xpanded to include beam loop summing amplifier and A modules in the PXI igital FLG /Master Oscillator Configuration and Beam loop signals were fed into a NI5734 4tached to the FLG FPGA module, on which a 17 bit word was generated corr (cid:5) (cid:6)(cid:7)(cid:8) ). (cid:5) (cid:6)(cid:7)(cid:8) was then kplane via Peerllator (LO) FPGA, nd used as the counter increment in a DDS, which was nels of the NI5781 fed into the existing analogue oscillator. ed which includefrequency sweep, with bespoke design to be built and configured. in well with our limited resources: a small RF team already supporting operation of an operational machine running 24/7 for 200 shelf” hardware should a Lab-nstru-FPGA devel-View user ence to draw ning. igital LLRF system ment of the Master tem to This was ture of the FPGA devices dence in the new system to ity issues with previous Beam from system The initial throughout the first tem live with physics shifts at the end of plemented on a single FPGA cember, panded to include plifier and s in the PXI tion. and Beam loop signals were fed into a NI5734 4 - tached to the FLG FPGA ed corre-was then plane via Peer - to - tor (LO) FPGA, nd used as the counter increment in a DDS, which was nels of the NI5781 fed into the existing analogue included a cy sweep, with the add2RF syto a NI5782 model with two input/output chapled at up to 250MHz. This was successfully tested with beam in August 2014.However, when the above system was expanded to be used with more LO FPGAs, the increased time taken to send the with (cid:5) (cid:6)(cid:7)(cid:8) This delay was compounded by the use of the PXIexpress backplane for system configuration data, which sporadmanibeam phase loop leading to dramatic beam losses.A faster means of broadcasting by modulating the 17 bit word over the four of the PXItrigger lines, with a 40MHzwas In February 2016, the system was used to supply the RF signaISIS user cycle. The system was configured to provide a single 1RF input sweep to the analogue LLRF system and a θ analogue cavity control loops Figure
The Frequency law trim function and the tion were obtained from the ISIS VISTA controls via a UDP based LabView programdeveloped by Tim Gray in the ISIS ControlsThis system, with occasional code updates, formed the basis of ISIS opewhichcontiThe miniage monitor and The cavity tuning loop bandwidth is the loop error is reduced by applying a calculated tune”the cavity bthe additional dynamic phase offset (2RF systems. The to a NI5782 model with two input/output chapled at up to 250MHz. This was successfully tested with beam in August 2014.However, when the above system was expanded to be used with more LO FPGAs, the increased time taken to send the (cid:5) (cid:6)(cid:7)(cid:8) word overwith the PXI - express update periodThis delay was compounded by the use of the PXIexpress backplane for system configuration data, which sporadically disrupnifested itself during beam tests in instbeam phase loop leading to dramatic beam losses.A faster means of broadcasting by modulating the 17 bit word over the four of the PXItrigger lines, with a 40MHzwas successfully tested with beam in April 2015.In February 2016, the system was used to supply the RF signals to the analogue LLRF system throughout the ISIS user cycle. The system was configured to provide a single 1RF input sweep to the analogue LLRF system and phase modulated 2RF sweep into each of the 2RF analogue cavity control loops Figure 3: D-LLRF Configuration for first user cycle.
The Frequency law trim function and the tion were obtained from the ISIS VISTA controls via a UDP based LabView programveloped by Tim Gray in the ISIS ControlsThis system, with occasional code updates, formed the basis of ISIS opewhich work to detinued.
CAVITY TUNING
The analogue RF cavity tuning loopminimising the phase error ge monitor and The cavity tuning loop bandwidth is the loop error is reduced by applying a calculated ” correction functionthe cavity bias regtional dynamic phase offset (he LO transceiver adapterto a NI5782 model with two input/output chapled at up to 250MHz. This was successfully tested with beam in August 2014.
However, when the above system was expanded to be used with more LO FPGAs, the increased time taken to word over multipleexpress switch fabric delayupdate period to be increased This delay was compounded by the use of the PXIexpress backplane for system configuration data, which disrupted the broadcast data stream. Thfested itself during beam tests in instbeam phase loop leading to dramatic beam losses.A faster means of broadcasting by modulating the 17 bit word over the four of the PXItrigger lines, with a 40MHz bitsuccessfully tested with beam in April 2015.In February 2016, the system was used to supply the ls to the analogue LLRF system throughout the ISIS user cycle. The system was configured to provide a single 1RF input sweep to the analogue LLRF system and phase modulated 2RF sweep into each of the 2RF analogue cavity control loops as shown in Figure
LLRF Configuration for first user cycle.
The Frequency law trim function and the tion were obtained from the ISIS VISTA controls via a UDP based LabView programveloped by Tim Gray in the ISIS ControlsThis system, with occasional code updates, formed the basis of ISIS operations for the nexevelop the cavity vol
CAVITY TUNING
RF cavity tuning loopphase error between the cavity gge monitor and a monitor of the Tetrode grid voltage. The cavity tuning loop bandwidth is the loop error is reduced by applying a calculated function [3] beias regulator, as shown in figure tional dynamic phase offset ( θ ) required for the ceiver adapters wereto a NI5782 model with two input/output chapled at up to 250MHz. This was successfully tested with However, when the above system was expanded to be used with more LO FPGAs, the increased time taken to multiple P2P streamsswitch fabric delay, to be increased from 2.6µs to 5.2µs. This delay was compounded by the use of the PXIexpress backplane for system configuration data, which the broadcast data stream. Thfested itself during beam tests in instbeam phase loop leading to dramatic beam losses.A faster means of broadcasting (cid:5) (cid:6)(cid:7)(cid:8) was by modulating the 17 bit word over the four of the PXIbit - rate (on each line)successfully tested with beam in April 2015.In February 2016, the system was used to supply the ls to the analogue LLRF system throughout the ISIS user cycle. The system was configured to provide a single 1RF input sweep to the analogue LLRF system and phase modulated 2RF sweep into each of the 2RF as shown in Figure LLRF Configuration for first user cycle.
The Frequency law trim function and the tion were obtained from the ISIS VISTA controls via a UDP based LabView program, dubbed “PixyBroveloped by Tim Gray in the ISIS Controls This system, with occasional code updates, formed the tions for the next three years, dvelop the cavity voltage control loops
CAVITY TUNING
RF cavity tuning loop is controlled by between the cavity ga monitor of the Tetrode grid voltage. The cavity tuning loop bandwidth is 5kHz or so, and so the loop error is reduced by applying a calculated before sending the, as shown in figure 4) required for the s were upgraded to a NI5782 model with two input/output channels sam-pled at up to 250MHz. This was successfully tested with However, when the above system was expanded to be used with more LO FPGAs, the increased time taken to P2P streams, combined required the from 2.6µs to 5.2µs. This delay was compounded by the use of the PXI - express backplane for system configuration data, which the broadcast data stream. This fested itself during beam tests in instability in the beam phase loop leading to dramatic beam losses. was implemented by modulating the 17 bit word over the four of the PXI - e rate (on each line), whichsuccessfully tested with beam in April 2015. In February 2016, the system was used to supply the ls to the analogue LLRF system throughout the ISIS user cycle. The system was configured to provide a single 1RF input sweep to the analogue LLRF system and phase modulated 2RF sweep into each of the 2RF as shown in Figure 3.
LLRF Configuration for first user cycle. θ phase func-tion were obtained from the ISIS VISTA controls via a , dubbed “PixyBroker”, Group. This system, with occasional code updates, formed the t three years, during age control loops s controlled by between the cavity gap Volt-a monitor of the Tetrode grid voltage. Hz or so, and so the loop error is reduced by applying a calculated “Cav-ing the signal to 4. ) required for the ed m-pled at up to 250MHz. This was successfully tested with However, when the above system was expanded to be used with more LO FPGAs, the increased time taken to bined the from 2.6µs to 5.2µs. - express backplane for system configuration data, which is bility in the mented e which In February 2016, the system was used to supply the ls to the analogue LLRF system throughout the ISIS user cycle. The system was configured to provide a single 1RF input sweep to the analogue LLRF system and phase modulated 2RF sweep into each of the 2RF c-tion were obtained from the ISIS VISTA controls via a , This system, with occasional code updates, formed the ing age control loops s controlled by t-a monitor of the Tetrode grid voltage. Hz or so, and so v-to igure 4: RF cavity tuning For the 2RF systems, under heavy beam loading,level control loop 0V, as the required gap Voltage is supplied by the beam itself. The cavity tuning phase detector ate and the tuning lofigure 5.
Figure 5: Tu Assuming that the system response from the output of the LLRF system down back up the monitor cables to the phase ple delay, the phase detector ence. This ationally for the years or so.
DEPLOYED SYSTEM ARCH
The D - LLRF system as currently deplschematically in figure
Figure 6: D-
The NI - RF cavity tuning
DEPLOYED SYSTEM ARCH
LLRF system as currently deplschematically in figure 6. -LLRF System Architecture.
RF cavity tuning.
DEPLOYED SYSTEM ARCH
LLRF system as currently depl
LLRF System Architecture.
DEPLOYED SYSTEM ARCHITECTURE
LLRF system as currently deployed is shown
LLRF System Architecture. als under heavy beam loading.
Assuming that the system response from the output of ode grid and a sim-into the cavity tuning fixed amplitude refer-ed opera-2RF systems for the last three
ITECTURE oyed is shown 8135 RealTime Controller operates the “Boot - Virtual Instrument (VI) that files to each FPGA on power up, per-sation and clock synchronisation of the and then marshals data from the Host VI gram and ISIS VISTA controls system to the FLG and each of the ten currentlysysteThis relies on a faster MQTT basedwhich will makeThe Windows Host with t(usually only aFLG setup paand sweep. The LLRF syFPGA tab ters loop operation anthe vvalues of tem, Theloscope VI, which can u10000 pointshown in figure 7selecbacksingle FPGA stream
Figure
Trolding the displayed signals on the PC VI, but local trigering on each VI will soon be implemented which should reduce the The FPGA on 120MS/sshown sch
Figure 8 each of the ten LO FPGA Modules.rently still used to pass data to and from thesystem, where parameters areis relies on polla faster MQTT basedwhich will make paraThe Windows Host with tabbed panes (usually only accessed FLG setup pane which contains Beam loop gain seand displays the top and bosweep. The status tab iLLRF system and aFPGA tab allows interactive editing of ters for each cavityloop operation anvirtual “Function Moues of function , eg the demanded gapvolts aThe Windows PC is also scope VI, which can u10000 point channelsshown in figure 7lected in each FPGA andkplane to the RT controsingle FPGA can bestream for display on
Figure 7: Host Oscilloscope
Triggering of the display is currently applied by thresolding the displayed signals on the PC VI, but local trigering on each VI will soon be implemented which should reduce the The FLG FPGA code FPGA on the NI0MS/s, 4 channelshown schematically in figure
Figure 8: FLG FPGA
LO FPGA Modules.ed to pass data to and from theparameters are ling of the VISTA data faster MQTT based method is cuparameter updates The Windows Host VI provides a local user interface abbed panes to access cessed by RF ene which contains Beam loop gain sethe top and bottom frstatus tab includes dtem and a simple LPRF On/Off buttonllows interactive editing of cavity, such as phase ofloop operation and PI Loop gainstion Module” chafunction profiles from thdemanded gapvolts aWindows PC is also used to operascope VI, which can update up to 4 simultaneouschannels at up to a. The 4 virtual signals are generated aned in each FPGA and streamed over the PCIplane to the RT controller where can be selected and for display on the host PC
Oscilloscope VI. iggering of the display is currently applied by thresolding the displayed signals on the PC VI, but local trigering on each VI will soon be implemented which should reduce the traffic on the PXIFLG FPGA code is implemented using LabView NI - FLG FPGA System Diagram
LO FPGA Modules. The PixyBroker ed to pass data to and from the set by machine oof the VISTA database chamethod is currently being tester updates event drivides a local user interface access the RF setup RF experts). These ine which contains Beam loop gain setom frequency for the cludes deployment status for the simple LPRF On/Off buttonllows interactive editing of the sephase offsets, Open / Closed Loop gains. A furtherule” channels with from the VISTA codemanded gapvolts amplitude proused to operate a pdate up to 4 simultaneousup to a 50Hz refresh ratetual signals are generated anstreamed over the PCIler where the channels ed and sent via a the host PC.
VI. iggering of the display is currently applied by thresolding the displayed signals on the PC VI, but local trigering on each VI will soon be implemented which traffic on the PXI - e bus. mplemented using LabView R FPGA module digitiser module8. System Diagram.
PixyBroker VI is ed to pass data to and from the controls chine operators.base channels and rently being testeddriven. vides a local user interface the RF setup parameters ). These include an ne which contains Beam loop gain settings quency for the RF ployment status for the simple LPRF On/Off button. The LO setup parame-Open / Closed ther tab displayswith “last sent”VISTA controls sys-ofile a virtual oscil-pdate up to 4 simultaneous, fresh rate, as tual signals are generated and streamed over the PCI - expresschannels for a sent via a networkiggering of the display is currently applied by thresh-olding the displayed signals on the PC VI, but local trig-gering on each VI will soon be implemented which mplemented using LabView module and NI - VI is ls . nels and ed vides a local user interface ters clude an tings RF ployment status for the The LO e-Open / Closed displays ” s-l-, , as d xpress for a network h-g-gering on each VI will soon be implemented which mplemented using LabView 34 The code is he B(cid:2) signal, toutputs are digiinto the FLG give B, which is then mapped to The F inc wordFrequency law Trim funcontrols system and signals, before being tranFPGA modules by the trigger line modulation scheme.Previous tests digitised beam sCORDIC algFigure 9 shows a comparison of the beam phase signal measured using this approach with that existing analogue beam phase loop.implemented existing analogue beam phase loopnal may then be used tocorrection and possnents for use in
Figure 9: Analogue and Digital
The FLG FPGA module is also used to distribute the Frame start other FPGA modules, which will enable pulsing of expeimental parameter values at repetition frequencies from 50Hz down to 50triggering different TS2 beam.
The LO FPGA is implementules.
Figure 10: LO
The Gap Voltage monitor signal is digit5782 transceiver adapter at 250MS/sFPGA. The signalsignal, together with the 3 re digitised on the FLG FPGA. Here, give B, which is then mapped to word is summed with cy law Trim funcs system and scaled vebefore being tranFPGA modules by the trigger line modulation scheme.ous tests successfully beam sum electrode signal foCORDIC algorithm to geshows a comparison of the beam phase signal measured using this approach with that existing analogue beam phase loop.lemented on the operational sylogue beam phase loopmay then be used to geneand possibly pruse in Feed Forward Beam Compensatio
Analogue and Digital
The FLG FPGA module is also used to distribute the trigger and machine timing signals other FPGA modules, which will enable pulsing of expeimental parameter values at repetition frequencies down to 50/640triggering different parameter values for The LO FPGA code, shown schematically in Figure ted on each of
LO FPGA System Diagram
Gap Voltage monitor signal is digittransceiver adapter at 250MS/ssignal is decimaer with the 3 anised on the front end adapter and passed Here, the
B(cid:2) signal give B, which is then mapped to F inc via a look up tsummed with a scaledction obtained from the VISTA scaled versions of the digibefore being transferred to the local oscillator FPGA modules by the trigger line modulation scheme.successfully used IQ electrode signal forithm to generate a beam phase signal. shows a comparison of the beam phase signal measured using this approach with that existing analogue beam phase loop. This willthe operational system logue beam phase loop. The generate the Bunch Length Loopbly provide Beam eed Forward Beam Compensatio Analogue and Digital Beam Phase Detection
The FLG FPGA module is also used to distribute the and machine timing signals other FPGA modules, which will enable pulsing of expeimental parameter values at repetition frequencies /640 th Hz. This will also alloparameter values for , shown schematically in Figure each of the LO NI - System Diagram.
Gap Voltage monitor signal is digittransceiver adapter at 250MS/s and passed to the LO mated, appropranalogue beam loop front end adapter and passed signal is integratvia a look up tscaled version of thetained from the VISTA sions of the digitised loop ferred to the local oscillator FPGA modules by the trigger line modulation scheme. demodulation of electrode signal followed by abeam phase signal. shows a comparison of the beam phase signal measured using this approach with that generated by the This will soontem to replace the . The same beam siate the Bunch Length Loopvide Beam I and Q compeed Forward Beam Compensation. Beam Phase Detection
The FLG FPGA module is also used to distribute the and machine timing signals to the other FPGA modules, which will enable pulsing of expeimental parameter values at repetition frequencies ranging This will also allow for parameter values for TS1 beam , shown schematically in Figure 7966R FPGA mo
Gap Voltage monitor signal is digitised on the and passed to the LO priately scaledbeam loop front end adapter and passed ted to via a look up table. version of the tained from the VISTA ised loop ferred to the local oscillator FPGA modules by the trigger line modulation scheme. lation of a lowed by a beam phase signal. shows a comparison of the beam phase signal by the soon be place the same beam sig-ate the Bunch Length Loop compo-
Beam Phase Detection.
The FLG FPGA module is also used to distribute the to the other FPGA modules, which will enable pulsing of exper-ranging w for beam and , shown schematically in Figure 10, FPGA mod- the NI - and passed to the LO ly scaled and passed into an layed word Q components rate that for the demandThe bon thadapand Q each of thefeed theturn The modupipelinetransanalogueTetrode grid VThesioned loops shifts in February and March 2019. tensity beam (~230losses. to the tion at this intenfeed forward beam loading very tuning performan Q components can be driven negtions for both loops Further tests on a single carried outforward beam coThe beam injection and for the first 3ms of ashown in ficontrolled Figure passed into an IQlayed reference signal generated from the rword used to step throughcomponents are PI loops. The setpoint for the that for the I loop is a scaled version of the amplitude demand profile obtained from the VISTA coThe beam wall current moon the 2 nd analogue input adapter module. This Q beam correction each of the I and feed the IQ - moduturn fed to the RF cavithe I and Q PI loop oudulate an RF sweeppipeline delay and output on the 2sceiver adapter. This can then be fed directly into thlogue cavity tuningTetrode grid Voltage. IQ LOOP
The system architecture described abovsioned to replace the anloops on a single 1RF cavity during machine shifts in February and March 2019. This system was used tensity beam (~230losses. No feed foto the digitally contion at this intensity using the anfeed forward beam cobeam loading can very small amplitudetuning loops to beperformance even forcomponents can be driven negtions for both loops Further tests on a single ried out with both the delayed output tuning and ward beam co measured ambeam injection and for the first 3ms of ashown in figure trolled by the old an
Figure 11: Analogue and Digital IQ - demodulator block along with asignal generated from the rused to step through a DDSare each used as process vaThe setpoint for the loop is a scaled version of the amplitude obtained from the VISTA coeam wall current monitor signal is also digitanalogue input channel. This is then IQ correction components Q PI loop outputs ulation of a DDS RF fed to the RF cavity via a trPI loop outputs RF sweep which is delay and output on the 2ceiver adapter. This can then be fed directly into thty tuning phase detector in placoltage.
LOOP OPERATION system architecture described abovto replace the analogue a single 1RF cavity during machine shifts in February and Ma
This system was used tensity beam (~230µA) at 40Hz to TS1, with o feed forward beam controlled cavitysity using the anbeam compensationcan cause the level controltude signal, cauecome unstable.even for the low amplcomponents can be driven negtions for both loops signal remain stable.Further tests on a single IQ loop both the delayed output tuning and ward beam compensation appliedmplitude and phase for this cavity beam injection and for the first 3ms of aure 11, compared with those for by the old analogue system. Analogue and Digital or block along with asignal generated from the rDDS look up table.used as process variaThe setpoint for the Q loop is set toloop is a scaled version of the amplitude obtained from the VISTA connitor signal is also digitchannel of the IQ demodulated to give components. These are then PI loop outputs and the rDDS RF sweeptransceiver DACputs above are used direcwhich is then passed through adelay and output on the 2 nd DAC channel ceiver adapter. This can then be fed directly into thphase detector in plac
OPERATION system architecture described above was commi amplitude & pa single 1RF cavity during machine This system was used to accelerateat 40Hz to TS1, with eam compensation was applied trolled cavity during these testssity using the analogue sytion is not polevel control loopcausing the cavity phase ble. The IQ - looplow amplitude casecomponents can be driven negative, but the remain stable. loop controlledboth the delayed output tuning and applied in the LO FPGAphase for this cavity beam injection and for the first 3ms of acceleration pared with those for logue system. Analogue and Digital Controlled. or block along with a de-signal generated from the received F inc ble. The I and riables in sepa-loop is set to zero and loop is a scaled version of the amplitude ntrol system. nitor signal is also digitised the transceiver demodulated to give I beam These are then added toand the result used to sweep, which is in DAC channel. used directly to then passed through achannel of the ceiver adapter. This can then be fed directly into thephase detector in place of the
OPERATION e was commis-amplitude & phase control a single 1RF cavity during machine physicserate a high in-at 40Hz to TS1, with low beam tion was applied these tests. Opera-logue system without possible, as the loop to output athe cavity phase and loop gives bettercase, as the I and tive, but the error func-controlled cavity were both the delayed output tuning and feed in the LO FPGA. phase for this cavity during celeration arepared with those for a cavity e- inc and a-zero and loop is a scaled version of the amplitude sed er beam to used to in to then passed through a he e e of the s-hase control physics n-beam tion was applied a-out ble, as the a and better and c-were feed . during re ty he phase transient during beam injection for the ana-logue amplitude / phase controlled cavity was ~30º com-pared with ~5º for the digital IQ controlled cavity. One can also see that the IQ controlled cavity amplitude pro-file appears much smoother. These results were very encouraging and plans were made to deploy the design for all ten RF cavities. Several more FPGA modules would be required for the operation-al deployment for this number of systems, with sufficient spares. In early 2019, the FLG FPGA module and 4-channel digitiser were replaced by a Kintex 7 PXIe7971R FPGA module and NI5783 4-channel transceiver adapter, as the FPGA utilisation was approaching 90% and a larg-er device would speed up compilation times and the addi-tional 4 DAC channels on the new transceiver adapter could then be used to generate auxiliary signals such as the Frequency Law signal sent to the Beam Intensity monitor and an RF sweep used for machine extract tim-ing. This would also allow the PXIe7966 FPGA modules already purchased as FLG FPGAs to be re-deployed as spare LO FPGA modules. The new design with a digital IQ controller was de-ployed on the single 1RF cavity for the beginning of the ISIS user cycle in June 2019. However, 3 hours into the user cycle, the system lost synchronisation between some of the LO FPGAs, causing dramatic beam losses. Previ-ously the system had been running stably for more than a week. The 4 channel digitiser adapter and Virtex-5 FPGA module were reinstated as FLG FPGA and beam was restored for the rest of the user cycle. Subsequent investigations found differences in the clock implementation on new 7971R FPGA module lead-ing to additional 2.5ns delay. This was just sufficient to cause sporadic loss of synchronisation. The FLG FPGA code was then changed to reduce the F inc bit clock rate to 20MHz (previously 40MHz), which would give sufficient room for any jitter on the bit transfer to fall well within the F inc bit update clock period. The updated FLG code was commissioned on the Kin-tex-7 FPGA module and 4 channel transceiver adapter and this was deployed for the beginning of the ISIS user cycle starting on 10th September and has been successful-ly running to date. The six fundamental cavities are now controlled with the digital IQ loop, though due to prob-lems elsewhere on the machine, available time to setup the digital feedforward beam compensation the systems was limited, so we are operating with traditional grid-voltage input to the cavity tuning loop and also using the analogue FFBC system until the next user cycle. CONCLUSIONS & FUTURE WORK
The choice of the NI PXIe platform gave a fast route to implement the initial simple system designs but did then add constraints to the full design, requiring some lateral-thinking solutions to be developed. The reconfigurable aspect of the FPGA modules enabled a gradual implemen-tation of the system, which built confidence during the initial operation as a combined Frequency law generator / Master oscillator, and gave the ability to test individual ‘add-on’ pieces of code functionality during machine development time, prior to operational deployment. This approach may have led to a longer development time than designing a new, fully functioning system. However, the system has now been successfully com-missioned for operational use in controlling the ISIS syn-chrotron RF cavities. The use of a digital IQ loop has given improved performance over the existing analogue amplitude and phase loops. Should feedforward beam compensation still be necessary, it will be implemented within the FPGA, allowing the ageing analogue beam compensation units to be removed and reduce machine downtime. The digital IQ loop control will be deployed for all 10 RF cavities, with triggered virtual oscilloscope signals and an updated ISIS VISTA controls interface in early 2020. Also, the FLG FPGA code will be updated to use the Wall Current monitor signal to directly operate the beam phase and also the bunch length loops and also to provide the auxiliary signals for extraction triggering etc. Further development is required to operate the cavity tuning loop (beyond the current production of the RF sweep fed into the existing analogue system). This may require moving the feed forward beam compensation code onto the FLG FPGA, to allow room for the cavity tuning IQ demodulation on the LO FPGAs. Future work will include updating the LLRF system in response to changing requirements caused by upgrades to the cavity high power drive amplifiers and bias regulators. We also aim to reduce the RF power budget by 10-20% with the use of beam triggered RF. The LLRF team will be providing support for the LLRF system for the ISIS Front Test Stand [4,5], which has an initial design using the same NI PXI-e platform hardware. Many of the techniques and code (eg VISTA controls interface, IQ loops, etc.) may be re-used for this project. REFERENCES [1 ] A. Seville, D. J. Adams, D. Bayley, I. S. K. Gardner, J. W. G. Thomason, and C. M. Warsop, “Progress on Dual Harmonic Acceleration on the ISIS Synchrotron”, in Proc. 11th European Particle Accelerator Conf. (EPAC'08) , Genoa, Italy, Jun. 2008, paper MOPC121, pp. 349-351. [2] C. W. Appelbee, A. Daly, and A. Seville, “Digital Master Oscillator Results for the ISIS Synchrotron”, in
Proc. 22nd Particle Accelerator Conf. (PAC'07) , Albuquerque, NM, USA, Jun. 2007, paper WEPMN076, pp. 2203-2205. [3]
R. J. Mathieson, D. Bayley, N. E. Farthing, I. S. K. Gard-ner, and A. Seville, “Improvements to ISIS RF Cavity Tuning”, in
Proc. 3rd Int. Particle Accelerator Conf. (IPAC'12) , New Orleans, LA, USA, May 2012, paper THPPC025, pp. 3332-3334. [4] D. C. Plostinar et al. , “Current Status of the RAL Front End Test Stand (FETS) Project”, in