Reducing Quantum Cost in Reversible Toffoli Circuits
RReducing Quantum Cost in Reversible Toffoli Circuits
Marek Szyprowski Institute of Computer Science Warsaw University of Technology Nowowiejska 15/19, 00-665 Warsaw, Poland [email protected]
Pawel Kerntopf Department of Theoretical Physics and Informatics University of Łód ź Pomorska 149/153, 90-236 Łód ź , Poland [email protected] Abstract — Recently, reversible circuit synthesis has been intensively studied. One of the problems that has not been solved for a long time was exact minimization of gate count (GC) in 4-bit circuits. Finally, last year a tool of practical usage for finding optimal gate count Toffoli networks for any 4-variable function was developed. However, not much work has been done yet on exact minimization of quantum cost (QC) in 4-bit circuits. This paper presents an application of the above mentioned tool to reducing QC of 4-bit reversible circuits. It is shown that for benchmarks and for designs taken from recent publications it is possible to obtain savings in QC of up to 74% comparing with previously known circuits.
Keywords-reversible circuits, synthesis, quantum cost I. I NTRODUCTION
A gate (circuit) is called reversible if there is a one-to-one correspondence between its inputs and outputs. Research on reversible logic circuits is motivated by advances in quantum computing, nanotechnology and low-power design. Therefore, reversible logic synthesis has been intensively studied. The attention has been focused on the synthesis of circuits built from the NCT library of gates. Satisfactory reversible logic synthesis algorithms for arbitrary libraries of gates and cost functions have not been found yet. In addition, NCT library synthesis techniques developed for such circuits scale not well and optimal circuits not always can be found even for relatively small numbers of inputs and outputs. Many reversible circuit synthesis algorithms have been proposed. However, they sometimes generate very suboptimal circuits. Therefore, to improve circuit quality, different techniques, consisting of a series of local optimizations have been developed. However, the problem is that some circuits cannot be reduced only by local optimization. Also, for larger functions these algorithms require many iterations of local optimization that leads to a high runtime. For many years only few exact optimal circuits have been found for n -variable functions with n > 3. For example, it was even not known what is the maximal gate count in optimal circuits implementing 4-bit reversible functions. Last year a very fast tool capable of synthesizing optimal circuits for any 4-bit reversible specification was finally developed [2] what has become a real breakthrough. With this tool it was possible to establish that there are 144 4-bit functions requiring 15 gates in their optimal circuits and that there exists none requiring 16 gates [3, 12]. Quality of a reversible circuit is usually estimated by gate count (GC) or by a metric called quantum cost (QC). Much less effort has been devoted to minimization of QC in reversible circuits. Maslov et al. [14] used a mixture of different techniques (including MMD algorithm, Reed-Muller spectra based algorithm, template application and resynthesis) to improve either gate count or quantum cost what led to improving results for some benchmarks from [12]. However, exact minimization of QC was not the aim of this approach. Donald and Jha [1] added a new option for optimizing QC to their earlier algorithm. Due to this they were able to improve results for some benchmarks but have attempted to find exact minimal values for small circuits only. They performed similar experiments for an extended library of gates including also SWAP, Fredkin and Peres gates. Wille et al. [27] formulated a synthesis problem as a quantified Boolean formula and then solved it by applying Binary Decision Diagrams. This enabled to find the minimal as well as the maximal QCs for the specified number of gates up to seven gates. However, these calculations were performed only for minimal gate count circuits. Grosse et al. [4] considered synthesis for networks made of multiple-control Toffoli gates using SAT-like engines. Their approach to reducing quantum cost was the same, i.e. minimization of the number of gates as the first step and only then trying to reduce quantum cost with the fixed gate count. However, as we will show in the paper, finding exact minimal quantum cost circuits for larger functions requires considering circuits having greater number of gates than the minimal size ones. Some efforts have been recently made to reduce QCs of designs. One of the recent approaches consists in looking for circuit realizations using quantum elementary gates like NOT, controlled NOT, two square roots of NOT [16, 17, 20, 21] or Hadamard gates [15]. However, we show that significant reduction of QC can also be obtained without considering elementary quantum gate library. First, we have developed a tool similar to the one reported earlier in [2] capable of finding a circuit having a minimal number of gates for any 4-bit reversible function. Then we have programmed and run an approach capable of finding all circuits implementing a given reversible function with a specified value of GC . Our calculations have led to obtaining savings in QC over 50% for some known benchmark functions and for designs reported in recent publications on synthesis of reversible circuits. At the same time we have shown that the numbers of all quantum cost minimal circuits for larger designs achieve the order of 10 . he paper is organized as follows. Section II recalls basic concepts of reversible logic. In Section III notions of cost functions and optimal reversible circuits are introduced. Sections IV presents a survey of recent results on synthesis of 3-bit and 4-bit reversible Boolean circuits. In Section V details of the fast algorithm for optimal gate count synthesis of 4-bit circuits are overviewed. Section VI contains description of our approach to searching for minimal quantum cost 4-bit reversible circuits. In Section VII our experimental results are collected and compared to known circuits from benchmark pages and from the literature. Section VIII summarizes the paper with conclusions and suggestion for further research. II. PRELIMINARIES Definition 1.
A completely specified n -input n -output Boolean function (referred to as n * n function) is called reversible if it maps each input assignment into a unique output assignment. There are 2 n ! reversible n * n Boolean functions. For n = 3 this number is equal to 40,320 and for n = 4 is greater than 2 · . Definition 2. An n -input n -output ( n * n ) gate (or circuit) is reversible if it realizes an n * n reversible function. In a reversible circuit fanout of each gate output is always equal to 1. As a consequence n*n reversible circuits can be only build as a cascade of k*k reversible gates ( k ≤ n ). Definition 3.
A set of reversible gates that can be used to build reversible circuits is called a gate library . Many gate libraries have been examined in the literature. The so called
NCT library consists of 1*1 NOT, 2*2 CNOT and 3*3 TOFFOLI gates. In this paper we will also discuss the usage of 4*4 TOFFOLI gates and 3*3 PERES gates. Below we define all these gates.
Definition 4. N OT ( x ) gate performs the operation ( x ) → ( x ⊕ C NOT ( x , y ) gate performs the operation ( x , y ) → ( x , x ⊕ y ), 3*3 T OFFOLI ( x , y , z ) gate performs the operation ( x , y , z ) → ( x , y , z ⊕ xy ), 4*4 T OFFOLI ( x , y , z , u ) gate performs the operation ( x , y , z , u ) → ( x , y , z , u ⊕ xyz ), 3*3 P ERES ( x , y , z ) gate performs the operation ( x , y , z ) → ( x , x ⊕ y , z ⊕ xy ), where ⊕ denotes XOR operation. The first four of the above defined gates (denoted N, C, T, T4, respectively) invert one input if and only if all others are 1, passing the other inputs unchanged to corresponding outputs. Each of the N, C, T, T4 gates is invertible, i.e. equal to its own inverse. Let us note that a PERES( x , y , z ) gate is equivalent to a TOFFOLI ( x , y , z ) gate followed by a CNOT ( x , y ) gate. Inverted
PERES gate is not equal to PERES gate. We will denote them by P -1 and P, respectively [13]. III. COST FUNCTIONS AND OPTIMAL REVERSIBLE CIRCUITS For any reversible function there exist many reversible circuits implementing it. Thus a cost function has to be defined to evaluate the quality of a circuit. Usually, additive cost functions are applied. Therefore, adding a gate to a circuit leads to increasing its cost. A cost of each gate type is often expressed as a non-zero value. The cost of the (hypothetically) simplest gate is assumed to be 1. A number of gate cost functions have been proposed (see, e.g. [28]). The simplest cost function of a reversible circuit is equal to total number of gates. It is called gate count (GC in short). Although this cost function probably would not be applicable to future technologies, it is used in the literature for comparing the quality of synthesis algorithms. Nevertheless, it could be treated as an approximation of practical cost functions for small reversible circuits. Other cost functions are also considered. The most widely used, called quantum cost (QC), is based on cost of elementary quantum gates as each reversible gate can be built from several elementary quantum gates. It is assumed that the cost of each elementary quantum gate equals 1, so the cost of a reversible gate equals to the total number of elementary quantum gates used. The quantum cost of N, C, P, T and T4 gates is assumed to be 1, 1, 4, 5 and 13, respectively (see for example [5, 12]). By an optimal circuit we mean the best possible implementation, i.e. the one having the minimal cost. The set of optimal circuits implementing a reversible function depends on a gate library and a cost function. It should be noted that a reversible function may have many equivalent optimal circuits. A database of all optimal circuits can be generated by building recursively new circuits from all gates that belong to the gate library and selecting only the circuits with the minimal cost after incrementing the number of gates in the circuits by 1. Such databases have been described in the literature, but usually only one optimal circuit is stored for each function (see, e.g. [14, 18]. Let us define an equivalence class in the set of reversible functions with respect to the cost of optimal circuits realizing these functions. Definition 5.
Two reversible Boolean functions are called cost-equivalent if they belong to the same equivalence class (called a cost-equivalence class , or a conjugacy class in [2]) under simultaneous input/output relabeling and inversion. It can be easily shown that two cost-equivalent functions have the same or reverse optimal circuits (i.e. optimal circuits for all cost-equivalent functions have the same cost for all cost metrics [2]). A cost-equivalence class can contain maximally 2 · n ! functions (number of permutations of all variables doubled by the possibility of inversion). We will be using the following popular vector notation for an n -variable reversible Boolean function f : [ f (0), f (1), ... , f (2 n -1)], where each binary vector f(i ) will be expressed as a decimal. ABLE I. T
RUTH TABLE FOR FUNCTION F x x x y y y Definition 6.
The canonical representative of a cost-equivalence class is the function whose vector [ f (0), f (1), ... , f (2 n -1)] is lexicographically smallest. Example 1.
Let us consider a reversible function f given in Table I. Its vector notation is [1,0,3,2,5,7,4,6]. It can be easily checked that this is the canonical representative of the cost-equivalence class of f as all functions belonging to this class are as follows: [1,0,3,2,5,7,4,6] [1,0,3,2,6,4,7,5] [1,0,3,7,5,4,2,6] [1,0,6,2,5,4,7,3] [2,3,0,1,5,7,4,6] [2,3,0,1,6,4,7,5] [2,3,0,7,6,1,4,5] [2,5,0,1,6,7,4,3] [4,3,6,7,0,1,2,5] [4,5,3,7,0,1,2,6] [4,5,6,1,0,7,2,3] [4,5,6,2,0,1,7,3] IV. A SURVEY OF RECENT RESULTS ON SYNTHESIS OF GATE COUNT OPTIMAL
AND
CIRCUITS
We have generated databases of all optimal circuits for 3*3 reversible Boolean functions for NCT library and two cost functions (GC and QC). After generating the databases we were using them in our research on synthesis of reversible circuits [6-9, 22-24]. During this research we have found all reversible functions requiring the maximal number of 8 gates in gate count optimal circuits. Next we discovered that for some of these functions longer circuits implementing them exist with much smaller QC. Fig. 1 shows such an example in which adding one gate leads to reducing QC from 24 to 13, i.e. by 45,8% (taking into account that two pairs of TOFFOLI and
CNOT gates form two PERES gates). In general, this property is encountered in circuits of relatively large size. Thus, when looking for minimal quantum cost circuits one have to consider circuits of different sizes. This observation attracted our attention to the problem of minimizing QC in reversible circuits. The databases generated by us for NCT library revealed one more interesting property of the set of all optimal 3*3 circuits. Namely, the greater the size of an optimal circuit the greater the number of all optimal circuits implementing the given function, e.g. the maximal number of all gate count as well as quantum cost optimal 3*3 circuits is higher than 1000 [8]. One can expect that in case of greater numbers of inputs/outputs the same property will hold and the maximal number of all gate count optimal 3*3 circuits will grow at least exponentially. Our recent experiments for 4-bit functions presented at the end of this paper show that this hypothesis is justified. GC = 8, QC = 24 GC = 9, QC = 13
Figure 1. Two circuits implementing the same reversible function TABLE II. D
ISTRIBUTION OF THE NUMBER OF CIRCUITS IMPLEMENTING
FUNCTION
NTH _ PRIME INC [17]
OVER THEIR SIZE
Gate count Similar properties of reversible functions have been discovered by us with respect to the cardinality of the set of all (i.e. not only optimal) circuits implementing a given function. Table II shows how fast this number can grow for n = 4 depending on the circuit size. The above discussed properties demonstrate how difficult is the task of finding exact minimal quantum cost reversible circuits. V. G
ATE COUNT OPTIMAL CIRCUITS SYNTHESIS
In the years 2007-2009 the problem of developing algorithms for synthesis of all gate count optimal 4*4 reversible circuits using NCT library have attracted attention of some researchers [10, 11, 25, 29-31]. Only in one of them it was claimed that a hash table has been constructed consisting all 8-gate optimal circuits which potentially enables constructing optimal circuits up to size of 16 gates [10]. However, besides one relatively simple example no experimental data were supplied. In addition, the example showed that the tool was quite slow. Recently, Golubitsky, Falconer and Maslov [2] presented the algorithm for finding a gate count optimal reversible circuit for any 4*4 reversible function. The algorithm is based on the fact that the set of all functions that have an optimal circuit up to 9 gates can be effectively stored in memory of today computers. It also relies on the fact that for each cost-equivalent class of reversible functions it is sufficient to store only its canonical representative, so the amount of required memory can be reduced almost 48 times . The functions in such database are stored in hash tables. The database can be used directly to find GC of an optimal circuit for any reversible function f up to 9 gates if the canonical representative of function f is used for the database lookup. unctions that require more than 9 gates in an optimal circuit need additional processing to determine GC of optimal circuits. Namely, the algorithm relies on the fact that any optimal circuit for the function f can be partitioned into two circuits which realize functions g and r , such as: f = g ○ r , where symbol ○ denotes composition (cascading of the circuits). The above equation can be transformed into the following: f ○ r -1 = g. The algorithm iterates over all functions in the database that have optimal circuits of length i for i = {1,…,9}, computes their inversions and then compose the function f with each of them. For the resulting function g it checks the length of an optimal circuit using the procedure from the beginning of the paragraph. If such function g with optimal circuit of length j has been found in the database, the length of the optimal circuit for the function f equals to i + j [2]. The above procedure provides an effective and very fast way of finding the length of an optimal circuit for any 4*4 reversible function. It can also be easily extended to a fast algorithm for finding an optimal circuit [2]. One just needs to store the last gate with each function in the database and the complete circuit can be easily constructed. Using the computer system with 16 AMD Opteron 2300 MHz processors and 64GB RAM authors of [2] managed to create a database for 9-gate optimal circuits and synthesize an optimal circuit for a given 4*4 reversible function in about 0.01s on average. A similar approach has been presented in [10]. However, the authors decided to store the complete circuits in the database. They only had managed to create a database for n =8. This decreased the synthesis speed so generating an optimal circuit for an example benchmark took approximately 35s. VI. O UR SYNTHESIS ALGORITHM
We have decided to extend the method presented in [2] for developing a tool capable of finding all reversible circuits with a specified gate count implementing the given reversible function. The algorithm is very similar to many heuristic algorithms of reversible circuit synthesis described in the literature. In each step a reversible gate is selected and added at the end of the current gate cascade (see Fig. 2). It might be necessary to backtrack and try another gate if the circuit for the given reversible function has not been found (Fig. 3). For selecting a gate algorithms rely on the criterion called a complexity measure. It limits the search tree and allows to avoid selecting gates that do not lead to an optimal circuit [28], [29].
Figure 2. A general scheme of one step of a search-based algorithm
Figure 3. Example of the search tree of a search-based algorithm
Definition 7.
A partial realization of a given reversible Boolean function f is a gate cascade, such that after adding a gate (or gates) a circuit implementing f is created. Definition 8.
A remainder function is a Boolean function to be implemented in a circuit that has to be added to the current partial realization to get a circuit implementing a specified reversible function. In Fig. 2 f T denotes the remainder function to be implemented after selecting G as the first gate of the circuit under construction. Definition 9. A complexity measure is a function that assigns a number to each reversible function in such a manner that functions with complex optimal circuits have higher measures than functions with simple optimal circuits. The perfect complexity measure assigns a monoto-nically decreasing numbers to remainder functions after adding consecutive gates in an optimal circuit for a given reversible function.
Note that the simple search-based algorithm is only guided by a complexity measure. It selects only the gates that generate decreasing complexity measure for the remainder functions. Even such simple algorithm can find more than one reversible circuit if it continues to run after finding the first reversible gate cascade that implements the specified function and use backtracking to check all paths in search tree. VII. E
XPERIMENTAL RESULTS
It can be easily noticed that the gate count calculated with the algorithm from [2] is a perfect complexity measure for the heuristic algorithms. We have decided to perform an experiment for finding quantum cost optimal circuits with specified sizes for previously proposed 4*4 reversible benchmarks. As a result of our calculations of all optimal circuits for 3*3 reversible functions we expected in advance that in some cases the runtimes could be very high. The results of our calculations are presented in Tables III-VI. The reversible circuits that have been found with this approach improve substantially previously reported circuits with best known quantum cost. The minimal value of the quantum cost of circuits found by us is sometimes more than two times smaller than the maximal one. For some benchmarks improvement was up to 74%. ur initial analysis of optimal circuits for 3*3 reversible functions showed that the quantum cost optimal circuits have higher average GC than the gate count optimal circuits. This is why we considered an extension to the algorithm for synthesis of all 4*4 reversible circuits. Namely, increasing by a the initial value considered as the complexity measure for function f , the algorithm will find all reversible circuits of length equal to o , o +1, …, o + a , where o is the length of the optimal circuit for the function f . The value of the parameter a needs to be adjusted experimentally to limit the calculation time and the number of generated circuits. Both the calculation time and the number of the circuits grow exponentially with the increasing value of a (see Tables III-VI). The proposed approach allows to find the 4*4 reversible quantum cost optimal circuits for a specified length of the reversible gate cascade. This does not mean that these circuits are exact minimal in terms of quantum cost, because there might exist longer cascades with lower quantum cost value (see the results in Tables III-VI). Nevertheless, the circuits we have found using the above described method are usually better in terms of quantum cost than the best circuits known from the literature. Our algorithm can be very easily parallelized. Calculations of the optimal circuit length for the remainder functions after applying all possible gates can be performed independently. In practical applications one should also consider adding a time limit, because the calculation take a lot of time for the parameter a larger than 2 and circuits longer than 13 gates. The calculation time also depends on the size of the database and the computer system used for calculations. Our results have been obtained on IBM pSeries p5 550 with two 4-way 1.65GHz POWER5+ CPUs with total of 16GB of memory. We used a database for 8-gate circuits. All the times are given in cpu-seconds . To present our results in a compact way we have shortened the names of gates: - NOT(a) is denoted by Na, - CNOT(a,b) is denoted by Ca-b, - TOFFOLI(a,b,c) is denoted by Tab-c, - TOFFOLI(a,b,c,d) is denoted by T4abc-d. We have adopted a method of calculating quantum cost applied in [12]. Possibility of grouping T and C gates into Peres gates or inverted Peres gates are detected and marked in the following way:
ABLE III. Q
UANTUM C OST OPTIMAL IMPLEMENTATIONS WITH SPECIFIED GATE COUNT FOR G G BENCHMARK
FUNCTIONS [12]
GC QC min in [12] 15 -75 340066 366283 Ca-d Cc-a Cd-c Tac-b Cb-a Ca-c
BENCHMARK FUNCTIONS FROM [3, 2, 12]
GC QC min in [3] 12 30-72 374 73 Cc-a Na Ca-d Tab-d Tcd-b
FUNCTIONS FROM [26, 10, 19, 31, 15, 32]
GC QC min mini_alu [0,1,2,3,4,5,14,11,8,6,10,9,12,15,13,7] GC=6, QC=62 in [26] 6 30-62 12 1 Tbc-a Tad-b Tad-c Tbc-a Tbc-d Tad-c 7 23-67 108 9
App2.11 [7,14,9,6,11,0,13,2,5,15,10,12,1,4,3,8] GC=14, QC=82 in [32] 9 Tabd-c Tac-b Cb-c Tabc-d Tbd-a Tad-b Cb-c Cc-d Nd Ca-c Tbc-d Tad-c Tbc-d Tac-b Tbd-a Ca-c Cc-d Ca-b Nd
UANTUM C OST OPTIMAL IMPLEMENTATIONS WITH SPECIFIED GATE COUNT FOR
FUNCTIONS FROM [30]
GC QC min f1 [0,1,2,3,15,10,11,13,9,12,5,4,14,8,6,7] GC=13, QC=24 in [30] 9
CONTINUATION ) QUANTUM COST OPTIMAL IMPLEMENTATIONS WITH SPECIFIED GATE COUNT FOR
FUNCTIONS FROM [30]
GC QC min g10 [0,1,10,11,12,5,7,15,14,4,3,8,2,9,6,13] GC=13, QC=23 in [30] 9 Cb-a
UR IMPROVEMENTS OF QUANTUM COST
Benchmark best known source our best circuit ∆ QC % impr.
47 [3] 39 -8 17.0
61 [3] 31 -30 49.2
53 [3] 33 -20 37.7
47 [3] 35 -12 25.5
43 [3] 31 -12 27.9 nth_prime4_inc
51 [3] 26 -25 49.0
32 [3,12] 28 -4 12.5 decode42
30 [3] 28 -2 6.7 hwb4
21 [3,12] 19 -2 9.5 imark
19 [3] 17 -2 10.5 mperk
15 [3] 13 -2 13.3 oc5
39 [3] 34 -5 12.8 oc6
42 [3] 37 -5 11.9 oc7
41 [3] 34 -7 17.1 oc8
48 [3] 35 -13 27.1 primes4
42 [3] 22 -20 47.6 mini_alu
62 [26] 16 -46 74.2 aj_e11
30 [26] 28 -2 6.7 mod10_171
56 [26] 32 -24 42.9 mod10_176
41 [26] 21 -20 48.8
30 [10] 26 -4 13.3 msaee
72 [19] 34 -38 52.8 gyang
103 [31] 36 -67 65.0 dmasl
128 [15] 24 -104 81.3
App2.2
102 [32] 35 -67 65.7
App2.11
82 [32] 26 -56 68.3 average:
Table IV compares our synthesis results to the ones collected in [2, 3] for a set of known benchmarks (we have omitted simple benchmarks , rd32 and shift4 as exact minimal quantum cost circuits for them have already been found). The comparison is favorable for our circuits, (e. g., our circuits for the functions nth_prime4_inc and primes4 are approximately 50% off from those reported in [3]). Again, the lowest values of quantum cost for circuits found by us are shown in bold in the column QC. Note that usually initial increasing of circuit size leads to lowering quantum cost but further increasing of GC causes a rise of QC (see results for benchmarks imark and oc5 ). Table V compares our synthesis results to 4*4 designs we could find in RevLib [26] and in recent publications. For some of these functions (e.g. mini-alu and gyang ) improvements (shown in bold) of over 60% are reported. Table VI compares the results of our synthesis algorithm with the results in [30] where 4*4 quantum cost optimal circuits built from Peres gates were searched. For a fair comparison we calculated GC in circuits from [30] by considering a Peres gate as two gates like in our designs. For 12 out of 14 functions considered in [30] our designs have smaller QC and for the other two functions we have obtained the same minimal values of QC. Table VII shows the collective data comparing our circuits to previously found ones realized by using gates exclusively from NCT library. These data were taken from Tables III-V. For some benchmarks and designs taken from the literature we have obtained savings in QC of over 74% comparing with previously known circuits. Average improvement is equal to 44.7 %. In Fig. 5 and Fig. 6 circuits for our best QC improvement ( mini_alu [26] and dmasl [15]) are shown together with the source circuits found in the literature. For some of the benchmarks considered in the paper better results could probably be generated, however we had to stop calculations due to time limitations in our experiments. Studying Tables III-VI one can see that increasing the gate count up to a certain value causes the reduction of quantum cost of best circuits. Usually this quantum cost reduction is achieved by replacing pairs of multiple-control Toffoli gates by cascades built from smaller gates. Further reduction of QC is achieved by grouping Toffoli and CNOT gates into Peres gates. The presented method does not guarantee finding quantum cost minimal circuits because the length (GC) of such circuits is not known. However, for an arbitrary selected circuit length it allows for generating 4*4 circuits with the least quantum cost if the computation time is not too large. Due to this property we were able to find circuits with QC smaller than results obtained by the other methods presented in the literature. III. C ONCLUSIONS AND FUTURE WORK
A common practice in synthesis of reduced quantum cost reversible circuits (e.g. see [5], page 704) is first find a gate count optimal circuit and then map the resulting circuit into quantum gates. However, as we showed in the paper, this approach does not lead to minimal quantum cost circuits. It requires considering circuits having greater number of gates than the minimal one to be able to find exact minimal quantum cost circuits. Research presented in the paper can be extended in different directions. One possibility is to consider other extensions to quantum cost model, like for example inter-gate optimizations [16, 17, 20, 21]. The other possibility is to apply the proposed method for another criteria of optimality. Namely, the large number of the reversible circuits that realize the same reversible function suggest that the circuits might also differ significantly under other criteria, e.g. depth of a circuit, latency, testability properties or new cost functions (like LNN cost or transistor cost [28]). Due to limitations in speed and memory space of current computer systems the proposed method cannot be used directly for circuits with more than 4 inputs/outputs. However, it might be applied to optimize some parts of n * n circuits, n > 4, having relatively long 4*4 subcircuits. A CKNOWLEDGMENT
This work was supported by the Polish Ministry of Science and Higher Education under Grant 4180/B/T02/2010/38. R
EFERENCES , [28] R. Wille, M. Saeedi, and R. Drechsler, “Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost,” Proc. 18th Int. Workshop on Logic and Synthesis, 2009, pp. 43-49.[28] R. Wille, M. Saeedi, and R. Drechsler, “Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost,” Proc. 18th Int. Workshop on Logic and Synthesis, 2009, pp. 43-49.