ROS: Resource-constrained Oracle Synthesis for Quantum Computers
Giulia Meuli, Mathias Soeken, Martin Roetteler, Giovanni De Micheli
BBob Coecke and Mathew Leifer (Eds.):Quantum Physics and Logic 2019 (QPL)EPTCS 318, 2020, pp. 119–130, doi:10.4204/EPTCS.318.8 c (cid:13)
G. Meuli, M. Soeken, M. Roetteler, G. De MicheliThis work is licensed under theCreative Commons Attribution License.
ROS: Resource-constrained Oracle Synthesis for QuantumComputers
Giulia Meuli Mathias Soeken
EPFLLausanne, Switzerland [email protected]
Martin Roetteler
Microsoft QuantumRedmond, United States
Giovanni De Micheli
EPFLLausanne, Switzerland
We present a completely automatic synthesis framework for oracle functions—a central part in manyquantum algorithms. The proposed framework for resource-constrained oracle synthesis (
ROS ) isa LUT-based hierarchical method in which every step is specifically tailored to address hardwareresource constraints.
ROS embeds a LUT mapper designed to simplify the successive synthesissteps, costing each LUT according to the resources used by its corresponding quantum circuit. Inaddition, the framework exploits a SAT-based quantum garbage management technique. Those twocharacteristics give
ROS the ability to beat the state-of-the-art hierarchical method both in number ofqubits and in number of operations. The efficiency of the framework is demonstrated by synthesizingquantum oracles for Grover’s algorithm.
Practical quantum computers are nowadays a realistic prospect thanks to advances in fabrication tech-nology and the effort of the research community to revolutionize computing [6, 17, 9]. Quantum systemsenable computation over superposition of states and are based on physical phenomena that are funda-mentally different from the ones exploited in classical computing systems. For this reason, they requirethe development of dedicated logic synthesis tools.The peculiarities of quantum computation can be exploited to solve problems that cannot be solvedwith standard computers in a reasonable time, by running innovative quantum algorithms. The possibleapplications span among others factorization [20], quantum chemistry [3], and satisfiability solving [8].Many quantum algorithms include combinational logic operations. The large amount of resourcesnecessary to perform such computations can overcome the resources available, hence preventing somealgorithms to be computed on a constrained quantum hardware. Consequently, there is a large interestin finding synthesis methods that minimize the impact of combinational logic on the cost of quantumalgorithms.Some automatic quantum circuit synthesis methods have been proposed [13, 7, 1, 19], which can beapplied to relatively small logic designs. Hierarchical methods proved to be applicable to larger designs,as they are based on multi-level logic representations [18]. Among them, the LUT-based hierarchicalreversible logic synthesis (
LHRS ) framework has been proposed in [21], and is currently part of the opensource project
RevKit . It exploits classical logic synthesis methods to create quantum circuits of anygiven combinational logic component. Objective functions of the synthesis are: the number of qubitsand the number of operations required to perform the target function. https://github.com/msoeken/revkit
20 ROS:Resource-constrained Oracle Synthesis for Quantum Computers
LHRS uses LUT mapping to decompose the target function. The decomposition step is a crucialphase in this hierarchical method, as it is the starting point of the synthesis process. For this reason, itis of paramount importance to control its behavior. The k -LUT mapping technique that is used in LHRS originates from the open source logic synthesis tool abc [5] and has been originally designed for thesynthesis of classical circuits.In this work, we develop an alternative hierarchical framework:
Resource-constrained Oracle Syn-thesis (ROS). It embeds a new quantum-aware LUT-mapper, that is specifically designed for the appli-cation into a hierarchical synthesis framework. Classical LUT-mappers, like the one used by
LHRS ,aim at minimizing area and delay, but none of them have an immediate direct counterpart in quantumcircuit synthesis. Instead, our mapper is designed to minimize metrics that make each LUT easier to besynthesized into a quantum circuit.We show that the hierarchical flow that integrates our new mapper achieves a consistent reduction inthe number of gates of the final circuits. We also integrate in the flow a method for quantum garbagemanagement that has been proposed in [11]. This method enables to efficiently uncompute intermediateresults, giving control on the number of extra qubits (ancillae) of the circuit.We show that our approach can effectively improve the state-of-the-art both in number of qubitsand in number of operations. Rather than providing a method that generates additional Pareto optimalsynthesis results, our approach systematically beats existing ones by improving the qubit count while notincreasing the gate count—and vice versa—by improving the gate count while not increasing the qubitcount. We apply the ROS flow to synthesize quantum oracles, which could be applied in algorithmssuch as Grover’s search, and compare our results with the state-of-the-art hierarchical method (
LHRS )showing improved results.
Quantum computing processes qubits. A qubit can be in one of the “classical” logic states, 0 and 1, or inany superposition of these states. The state of a qubit q can be defined by the linear combination of theclassical states using two complex coefficients, q = a | i + a | i , with a , a ∈ C and | a | + | a | = | a | = | a | = / q = a | i + a | i + a | i + a | i , with a , a , a , a ∈ C and | a | + | a | + | a | + | a | =
1. As a consequence, 4 complex coefficients are needed torepresent a two-qubit state, while 8 complex coefficients are necessary to describe a 3-qubit system. Ingeneral, to represent the state of n qubits and to simulate the quantum system behavior on a classicalcomputer, 2 n complex coefficients are required.While modeling a combinational functionality for the use in a quantum computation, it is possible toconsider all the inputs as Boolean values—even when embedded as part of a quantum algorithm whereentangled states in superposition are being applied..Meuli, M.Soeken, M.Roetteler, G.DeMicheli 121The state of a qubit can be modified by applying quantum operations. All possible operations are re-versible and can be represented by unitary matrices. Both single-qubit operations and 2-qubit operationsare available, the latter changing the state of a qubit according to the state of a second one.There are different universal sets of quantum operations, targeting different technologies. In thiswork, we refer to the set that consists of the following operations: Controlled-NOT (CNOT), Hadamard( H ) and rotations of an arbitrary angle θ over the Z-axis of the Block sphere ( R z ( θ ) ). All quantumoperations can be represented by unitary matrices of dimension 2 n × n , where n is the number of qubitsaffected by the operations. For the selected universal set, the representative matrices are:CNOT = (cid:18) (cid:19) , H = √ (cid:0) − (cid:1) , R z ( θ ) = (cid:18) e − i θ e i θ (cid:19) A quantum oracle is defined as a “black box” operation performing a multi-output Boolean function f : B n → B m . The effect of an oracle O performing the operation f over two registers, one of n qubits tostore the inputs, | x i , and one of m qubits to store the outputs, | y i , can be described as follows: O ( | x i ⊗ | y i )
7→ | x i ⊗ | y ⊕ f ( x ) i The cost of a quantum circuit depends on the number of qubits required for the computation, and thenumber of operations that are performed. Automatic tools can be used to take into account technologyconstraints by synthesizing low cost quantum circuits.
We call a function f : B n → B , where B = { , } , a Boolean function over n variables. A Boolean func-tion can be represented by its truth table in the { , − } encoding, which is a bitstring b n − b n − . . . b ofsize 2 n where b x = ( − ) f ( x ,..., x n ) when x = ( x x . . . x n ) The Hadamard transform matrix over n variables is defined as: H n = H n − H n − H n − − H n − ! , H = n variables. For example the last row of an n -variable Hadamard matrix will be the truthtable of the parity function p = x ⊕ x ⊕ · · · ⊕ x n .The Rademacher-Walsh spectrum S of the function f expressed as a truth table in the { , − } encod-ing F is defined as: S = H n F Each coefficient of the spectrum represents the correlation with a parity function of a subset of the inputs.
Example 1
Given the 3-input majority Boolean function f ( x , x , x ) = h x x x i , its truth table is:F = (cid:16) − − − − (cid:17) The Rademacher-Walsh spectrum of f is:S = H F = (cid:16) − (cid:17)
22 ROS:Resource-constrained Oracle Synthesis for Quantum Computers n n n n x x x x f cut cut (a) x x x x f (b) x x x x f (c) Figure 1: (a) an AIG graph performing the function f = ( x + x ) x x with two possible 3-feasible cuts;(b) 3-LUT network generated by cut ; (c) 3-LUT network generated by cut .We later make use of the fact that one can derive a quantum gate implementation for a Boolean functionfrom the function’s spectral coefficients [1, 19]. k -LUT mapping Lookup table (LUT) mapping is a decomposition method that has originally been used to map a logicdesign into components of FPGAs (Field Programmable Gate Array) capable of computing any Booleanfunction up to a given number of inputs, i.e., lookup tables. Later, LUT mappers found a successful ap-plication in logic synthesis and circuits optimization [14], as they allow to decompose large functionalityinto smaller functions. Several efficient state-of-the-art mappers are available and they are traditionallydesigned to minimize delay and area of the resulting circuit.The input of the LUT mapping is a multi-level logic network representing a Boolean function. Amulti-level logic network is represented by a graph, in which each node performs a Boolean operationand edges define data dependencies. The inputs of the function are represented by the primary inputs ofthe network. According to the characteristics of the network, we distinguish different graph represen-tations. In And-Inverter Graphs (AIG), nodes perform the 2-input AND Boolean function, while edgescan be complemented to perform inversion. A different network representation, called Xor-And-inverterGraphs (XAG) implements the 2-input XOR in addition to the 2-input AND operation. For example, alogic network representing the function f = ( x + x ) x x is shown in Fig. 1(a). All nodes of this net-work perform the 2-input AND operation between the node’s inputs, dashed edges represent Booleaninversion, and x , x , x and x are the primary inputs.The k -LUT mapper decomposes the multi-level network using k -feasible cuts. A cut for a node n is a set of leaves l , . . . , l n such that each path from n to a primary input includes one of the leaves. A k -feasible cut is a cut that has at most k leaves. Leaves are nodes or primary inputs of the network. InFig. 1(a) two 3-feasible cuts are shown for the node n . The fist cut has leaves n , x and n , while thesecond cut has leaves n , x and x . Fig. 1(b) and (c) show the 3-LUT networks generated by the first andthe second cut, respectively. In the first graph, the node highlighted in blue is a LUT with 3 inputs thatperforms the combined operations of nodes n and n , while in the second graph, the LUT highlightedin red performs the combined operations of three nodes. Comparing the two networks, generated by twodifferent cuts, it is clear how the choices made during the mapping process affect the number of nodes ofthe resulting LUT network and the complexity of the function performed by each LUT..Meuli, M.Soeken, M.Roetteler, G.DeMicheli 123 k -LUT based hierarchical reversible synthesis Automatic quantum circuit synthesis methods transform a high level Boolean function representationinto a quantum circuit, exploiting reversible circuits as intermediate representations. These circuits arecomposed by single target gates, that are generalizations of the multiple-controlled Toffoli gates. Asingle-target gate T f ( { x , . . . , x n } , x k ) is characterized by: a set of controls x , . . . , x n , a control function f : B n → B and a target x k . The value of x k is complemented if the function f ( x , . . . , x n ) evaluates to one.Efficient methods are known for the decomposition of these reversible gates into quantum operations [2,10, 12].Hierarchical methods for the synthesis of quantum circuits have shown the ability to synthesizelarge functions and enable to explore the trade-off between number of operations and number of qubits.Hierarchical means that the method starts from a multi-level representation of the function, i.e., a graph.Inputs to the function are stored on a set of existing qubits. Additional qubits are used to store intermediteresults computed by each node of the graph. Finally, the output results are available on some of theadditional qubits. Among the hierarchical reversible logic synthesis methods, LHRS [21] exploits a state-of-the-art area-oriented LUT mapper, called mf that is part of the logic synthesis framework abc [5] togenerate a LUT network that is used as starting representation for the synthesis flow.The flow of LHRS is shown in Fig. 2(a). The first step of the flow, i.e., the k -LUT mapping, has a largeimpact on the final result, as it defines: (i) the number of required qubits, and (ii) the complexity of eachsub-network. Fig. 3(a) show an input network that is transformed by the mapper into the 2-LUT networkin Fig. 3(b). In the successive step, the k -LUT network is transformed into a reversible circuit, a networkmade of single-target gates (STG network). In this reversible representation, each line corresponds to asingle qubit. This step is performed by exploiting the one-to-one correspondence between nodes of the k -LUT network and reversible single-target gates. It transforms the network in Fig. 3(b) into one of theSTG networks in Fig. 3(c) and (d). The Gray synthesis method [1, 19] (see Fig. 2(a)) decomposes eachsingle-target gate with control function f into a quantum circuit that consists of the following quantumoperations: CNOT, H , R z ( θ ) . The method is characterized by a direct dependence between nonzerocoefficients in the Hadamard-Walsh spectrum of the function f and number of CNOT and R θ gates tobe synthesized. This method is performed after the k -LUT mapping, this means that by modifying themapping we get some control on the characteristics of the control functions in the LUT network, that areinput to the Gray synthesis.In LHRS , k -LUT mapping is performed considering metrics as delay and area, that have no imme-diate correlation in this application; so when k -LUT mapping is used in the context of quantum circuitsynthesis, the classical metrics must be changed to context-related ones. In this work we address this crit-icality by integrating in ROS a new quantum-aware k -LUT mapper that aims at minimizing the numberof gates required to synthesize the quantum circuit of each LUT using the Gray synthesis method. Quantum circuits are required to be garbage free, that is, any intermediate result needs to be accessiblefrom the outputs. Otherwise, as many states can be entangled together, measurement of intermediateresults may compromise the computation. Recently, a method for quantum memory management hasbeen proposed that is based on solving instances of the reversible pebbling game [11]. This technique24 ROS:Resource-constrained Oracle Synthesis for Quantum Computers mappinginto qubits(Bennett)
AIG k -LUTnetwork STGnetwork quantumcircuit k-LUTmapping Graysynthesis (a) SAT-basedmemory management(pebbling)
XAG k -LUTnetwork STGnetwork quantumcircuit quantum-awarek-LUTmapping Graysynthesis (b) Figure 2: (a) state-of-the-art hierarchical synthesis framework; (b) proposed hierarchical synthesis frame-work. n n n n x x x f (a) n n n n x x x f (b) x x x n n n n n n n x x x f (c) x x x n n n n n n n n n x x x f (d) Figure 3: (a) a three-input multi-level logic network performing the Booelan function f ; (b) an exampleof a 2-LUT network for f ; (c) the reversible circuit for the 2-LUT network obtained using the Bennettclean-up strategy; (d) the reversible circuit for the 2-LUT network obtained using the quantum garbagemanagement clean-up strategy [11].can grant control on the number of qubits that are used in the clean-up process, exploiting a state-of-the-art SAT solver [16]. In [11], the authors show how the problem of uncomputing intermediate resultscorresponds to the reversible pebbling game.Consider Fig. 3(c), here the k -LUT network is mapped into qubits, and each node is transformed inits corresponding reversible gate. The intermediate result is stored on a qubit that was initialized to | i .After the result is computed, all the intermediate values n , n , and n must be uncomputed. This is doneby performing the same operation twice. The order in which nodes are computed and uncomputed is aclean-up strategy, in Fig. 3(c) the strategy used is called Bennett strategy [4]. The SAT-based methoddescribed in [11] is capable of finding clean-up strategies that reduce the number of required qubits bycomputing and uncomputing the same reversible operation more than once. An example is shown inFig. 3(d). Even if quantum computing is promising to beat its classical counterpart in many applications, quantumdevice technology is still developing and is fairly new with respect to standard CMOS technology. Withour tool we aim at providing the designer with the capability to tune the synthesis with respect to the.Meuli, M.Soeken, M.Roetteler, G.DeMicheli 125 it s S / B M / B M / PS / P S / P S : spectral mapper (new) M : mf mapper (state-of-the-art) P : memory management technique(state-of-the-art) B : Bennett (state-of-the-art) Figure 4: qualitative description of ROS’s capabilityavailable hardware.We propose ROS, a hierarchical synthesis framework built to leverage the quantum circuit cost, bothin terms of number of qubits and number of gates. ROS’s synthesis flow is shown in Fig. 2(b). Itintroduces two main contributions with respect to the state-of-the-art flow (see Fig. 2(a)). • First, it embeds a new k -LUT mapper that is used to decompose the initial functionality into LUTs,in such a way to minimize the cost of each LUT. Such cost is defined according to the complexity ofthe LUT function to be synthesized by the Gray algorithm. If we analyze the result of this mapperagainst the state-of-the-art mf mapper, we get in general more LUTs, each one corresponding tofewer gates. • Second, it exploits the quantum garbage management technique presented in [11] to control thenumber of qubits.We claim that by using those two techniques together with the Gray synthesis method, we can beatthe state-of-the-art results both in number of qubits and number of gates. Fig. 4 shows a qualitativedescription of the performance advantages we expect to obtain using ROS. In the plot, the state-of-the-art result is the one marked as M / B (corresponding to the LHRS synthesis framework). If we only applythe memory management technique in [11], but not the new mapper, we will obtain a circuit with fewerqubits and more gates, that correspond in the figure to M / P . If instead we embed into LHRS our quantumaware k -LUT mapper, but no quantum memory management, we can obtain a circuit with few gates butmore qubits: S / B . Only by combining both techniques ( S / P ), we can beat the state-of-the-art tool inboth qubits and gates. In fact, we can tune the approach to only improve qubit count by not increase gatecount, or vice versa. This qualitative description is supported by the results in Section 5. k -LUT mapping A main contribution of this work is to develop a k -LUT mapper designed to reduce the resources neededto synthesize the quantum circuit of each LUT. As explained in Section 2.4, LUT mapping is usedto decompose a logic design that is too large to be synthesized into a quantum circuit by the existingmethods. In this section, we describe how to perform this decomposition to facilitate the successivesynthesis steps.26 ROS:Resource-constrained Oracle Synthesis for Quantum Computers f f f f (a) XOR LUT f f f f f f f (b) Conventional mapping f f f f f f f (c) Improved mapping Figure 5: Mapping LUTs that represent the XOR function
An Xor-And-inverter Graph, or XAG, is input to the k -LUT mapping process. This is a graph whereeach node performs the XOR or the AND operation, and where edges can be complemented to performinversion. The choice of this particular data structure is not accidental, but reflects the fact that it isrelatively cheap to perform the XOR operation in fault tolerant quantum circuits. Only one CNOT gateis needed to perform the XOR between two qubits, and in general m − m -input XOR gate. If the result should be stored on a free ancilla line, m CNOTgates are needed in total.Once the input is defined, we first perform cut enumeration. This step consists of enumerating allpossible cuts for each node of the input graph, traversing the graph from the bottom to the top. Only thebest cuts are stored for each node, a technique called “priority cuts” to reduce the memory requirementof cut enumeration [15]. During cut enumeration each node is assigned to a set of p cuts that are orderedfollowing a user defined cost criteria. In our case, as we aim at integrating the mapper into a quantumsynthesis framework, we use as cost function the number of nonzero spectral coefficients of the functionperformed by the selected cut. As pointed out in the preliminaries, the Gray synthesis method generatessmaller quantum circuits when the input function presents a spectrum with many zeros. At the end ofthe cut enumeration step, each node of the XAG is assigned with an ordered set of p cuts, with the ordercriteria defined by the spectrum of the cut’s function. We chose XAG graphs as logic representation, due to the inexpensive implementation of the XOR oper-ation in fault tolerant quantum circuits. Following this idea we modify the mapping algorithm to identifyand select cuts that performs the parity function. They can be synthesized as multiple-input XOR gates.After we perform cut enumeration we refine the cuts, looking for multi-input XOR blocks. In fact, ifall leaves of the cuts have a fan-out size of 1, i.e., they only fan-in into the XOR gate, we can apply an.Meuli, M.Soeken, M.Roetteler, G.DeMicheli 127M/B S/B S/P_match_q S/P_match_g M/Pgates qubits gates qubits gates qubits gates qubits gates qubitsaddassoc4 1376 25 1029 34 1141 25 1371 22 1904 19addassoc5 2987 36 1586 49 1798 36 1804 31 5365 24addassoc6 2394 43 1445 58 1513 42 1729 35 8268 26addassoc7 3243 51 1941 70 2201 50 2361 44 4383 36addassoc8 3221 62 2018 79 2312 57 2430 49 4787 40addassoc9 3603 70 2385 89 2453 67 2773 56 5569 42addassoc10 4528 80 2835 97 3575 70 3549 58 6142 50multassoc4 6682 34 2751 60 3057 34 3193 33 10834 19multassoc5 10519 54 4811 104 5321 55 5321 55 16687 31multassoc6 17653 93 7395 172 8565 96 8565 96 22933 53multassoc7 25395 138 11099 240 15425 135 14607 128 37717 74multassoc8 32443 181 13781 323 20713 179 22997 166 51757 94multassoc9 37599 212 17881 394 34305 203 32489 200 66267 110multassoc10 47795 289 22843 525 41825 281 41081 262 101627 143multdistr4 4812 29 2368 54 3262 29 3694 25 5034 19multdistr5 9011 54 4569 94 5441 54 5441 54 22717 25multdistr6 13327 78 6092 143 7138 80 7138 80 15169 46multdistr7 18268 110 8771 200 13849 109 13849 109 21746 63multdistr8 26151 149 11888 276 17896 149 17520 143 39449 81multdistr9 30427 184 14477 332 22917 182 22445 181 43819 99multdistr10 37571 226 17808 414 29714 214 31570 219 55583 122S/P vs M/B average results -32.31% -1.86% -29.77% -8.38%Table 1: Comparison between
ROS and
LHRS alternative mapping strategy that leads to reduction of qubits and gates.Fig. 5 illustrates the improved mapping strategy for an XOR cut with three inputs. In Fig. 5(a) thisLUT is drawn as an XOR symbol. The conventional mapping, shown in Fig. 5(b), maps each child in toa clean ancilla, and then uses another clean ancilla to map the result of the XOR cut. The result of thatcut, f , can then be used by its parents in subsequent gates. We illustrate this fact by simply annotatingthe circuit line where it represents the value f . However, since in this case the child cuts f , f , and f are composed via the XOR operator, one can directly map them in to a single qubit without the need ofrequiring an additional ancilla for each child LUT, see Fig. 5(c).Note that the size of the XOR gates does not need to be bounded by the LUT size k . In order tobuild XOR blocks in XAGs, we first detect 2-input XOR gates. Afterwards, sub-trees of XOR gates aregrouped together. Finally, we adjust cut enumeration such that XOR cuts are assigned with cost 0, inorder to force the LUT mapping to prefer XOR blocks.28 ROS:Resource-constrained Oracle Synthesis for Quantum Computers We have implemented our algorithms into the hierarchical quantum synthesis framework caterpillar in C++. In this section we illustrate the efficiency of our proposed approach by synthesizing oracles,which can be used in algorithms such as Grover’s search algorithm [8], which is capable of computing asatisfying assignment for a quantum oracle optimally with a quadratic speedup.For our benchmarks we suppose that we want to perform equivalence checking between two designs.Equivalence checking is a well-known problem in logic synthesis that has been addressed by many logicsynthesis tools, as for example abc [5] or Formality R (cid:13) . We need to synthesize an oracle quantum circuitof the function f , where f is satisfied when the two graphs performs a different operation. The algorithmwould either prove that the two circuit are equivalent, or would provide the input set for which the twofunctions evaluate differently.Our benchmark consists of XAG graphs. Each graph represents an equivalence checking miter oftwo circuits that perform the same function but using a different network structure. The miter of twonetworks is a network built by joining their input sets and by computing the 2-input XOR between theiroutputs. Further, one or more injected faults (a node performing a different computation) are injected inone of the two circuits. We consider three type of benchmarks: addassoc , where the algorithm shouldverify the validity of the associative property of addition; multassoc , where the two designs should beequivalent thanks to the associativity of the multiplication, and multdistr , to prove the distributivity ofthe multiplication. Each benchmark is considered with bitwidths from w = w inputs and 1 output.Our experimental results are reported in Table 1. The first two columns show the results of the state-of-the-art (M/B) synthesis flow, that uses a classic k -LUT mapper and the Bennett strategy to deal withgarbage results ( LHRS ).As expected, data shows that by only changing the k -LUT mapper (S/B) we always reduce the num-ber of gates, paying in an increased number of qubits. On the other hand, by only applying the quantumgarbage management technique (M/P), the number of qubits is always reduced, and the number of gatesincreased.In the S/P_match_q experiment we have used ROS, setting the number of qubits to match M/B. Inmost of the cases we obtain an improvement in both qubits and gates, with the exception of multassoc5 , multdistr6 and multassoc6 . For the latter cases, the SAT solver that is used in the quantum garbagemanagement technique had reached our limit of 50000 conflicts. For this reason, we needed to slightlyincrease the number of qubits, still obtaining in all cases a reduction in gates with respect to M/B. ROS in this setting reduces the number of gates of 32.31% and the number of qubits of 1.86% on average.In the S/P_match_g experiment, we start from the results in S/P_match_q and try to beat them, bydecrementing the number of qubits, as long as the number of gates does not exceed the one in M/B. Alsohere ROS manages to obtain better results than the state-of-the-art flow both in gates and qubits. Gatesare reduced of 29.77% while qubits are reduced of 8.38% on average, with respect to M/B.Most of the synthesis runs completed within a few seconds, none required more than one minute inthe worst-case. https://github.com/gmeuli/caterpillar .Meuli, M.Soeken, M.Roetteler, G.DeMicheli 129 In this work we introduce ROS: a hierarchical quantum synthesis flow based on k -LUT networks. ROSexploits a k -LUT mapper that has been specifically designed for this application. This mapper is capableof generating LUTs that are easy to be synthesized by the Gray synthesis method, and leads to a quantumcircuit with fewer gates if compared with existing mappers, i.e. mf from abc . In addition, ROS exploitsa SAT-based quantum memory management technique to gain control over the number of qubits of thegenerated circuits. In our experiments we apply ROS for the synthesis of quantum oracles, which may beused in algorithms as the Grover’s algorithm. Experimental results prove the ability of ROS to break theborder of the pareto-point synthesis results, beating the existing framework in both qubits and number ofgates. Acknowledgments
This research was supported by the Swiss National Science Foundation (200021-169084 MAJesty).
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