Schottky Barrier Height Engineering In β -Ga 2 O 3 Using SiO 2 Interlayer Dielectric
Arkka Bhattacharyya, Praneeth Ranga, Muad Saleh, Saurav Roy, Michael A. Scarpulla, Kelvin G. Lynn, Sriram Krishnamoorthy
11 Schottky Barrier Height Engineering In β -Ga O Using SiO Interlayer Dielectric
Arkka Bhattacharyya, Praneeth Ranga, Muad Saleh, Saurav Roy, Michael A. Scarpulla, Kelvin G. Lynn, andSriram Krishnamoorthy
Abstract —This paper reports on the modulation of Schottkybarrier heights (SBH) on three different orientations of β -Ga O by insertion of an ultra-thin SiO dielectric interlayerat the metal-semiconductor junction, which can potentiallylower the Fermi-level pinning (FLP) effect due to metal-inducedgap states (MIGS). Pt and Ni metal-semiconductor (MS) andmetal-interlayer-semiconductor (MIS) Schottky barrier diodeswere fabricated on bulk n-type doped β -Ga O single crystalsubstrates along the (010), (-201) and (100) orientations andwere characterized by room temperature current-voltage (I-V)and capacitance-voltage (C-V) measurements. Pt MIS diodesexhibited 0.53 eV and 0.37 eV increment in SBH along the(010) and (-201) orientations respectively as compared to theirrespective MS counterparts. The highest SBH of 1.81 eV wasachieved on the (010)-oriented MIS SBD using Pt metal. TheMIS SBDs on (100)-oriented substrates exhibited a dramaticincrement ( > × ) in SBH as well as reduction in reverse leakagecurrent. The use of thin dielectric interlayers can be an efficientexperimental method to modulate SBH of metal/Ga O junctions. Index Terms —gallium oxide, Schottky contact, metal-insulater-semiconductor, Fermi-level pinning, power device
I. I
NTRODUCTION B ETA -Ga O is a transparent conducting oxide which hasemerged as a promising candidate for next generationpower electronic devices largely due to its wide band gap (E g ∼ β -Ga O is Arkka Bhattacharyya, Praneeth Ranga, Saurav Roy, and Sriram Krish-namoorthy are with the Department of Electrical and Computer Engineering,The University of Utah, Salt Lake City, UT, 84112, United States of America(e-mail: [email protected], [email protected] ).Michael A. Scarpulla is with the Department of Electrical and ComputerEngineering and the Department of Materials Science and Engineering,University of Utah, Salt Lake City, Utah 84112, USA.Muad Saleh is with the Materials Science & Engineering Program and theCenter for Materials Research, Washington State University, Pullman, WA,99164, United States of America.Kelvin G. Lynn is with the Materials Science & Engineering Program, Cen-ter for Materials Research, School of Mechanical and Materials Engineering,and the Department of Physics, Washington State University, Pullman, WA,99164, United States of America. Fig. 1. Overview of Schottky barrier heights extracted using I-V, C-V andinternal photoemission (IPE) measurements on four different orientations of β -Ga O using different metals as a function of metal workfunction. Themetal workfunction values were considered from reference [12]. currently restricted to unipolar power devices such as metal-semiconductor FETs, MOSFETs and rectifying diodes [2],[10], [11]. Schottky contacts with enhanced barrier heightsand low reverse leakage currents is crucial for high-powerdevice applications. Therefore, the optimization of metal-semiconductor (MS) Schottky contacts (SCs) on β -Ga O isof key importance for reliable functioning of these unipolardevices. It is of particular interest to investigate whether itis possible to obtain large Schottky barrier heights ( ∼ E g /2)that can potentially then be used to design Enhancement-modeMESFETs.In the last few years, formation of SCs on β -Ga O andtheir electrical properties were studied and investigated, mostof which involved SCs with various high workfunction metals,surface treatments and different metal deposition techniqueson different orientations of β -Ga O substrates [13]–[30]. Theanisotropic material properties of β -Ga O due to its highlyasymmetric monoclinic crystal structure has also attractedimmense research interest [10], [11]. A brief overview ofthe measured Schottky barrier heights (SBH) of SCs withhigh work function metals on various orientations of β -Ga O is shown in Figure 1. The (010) orientation exhibitslower oxygen-dangling bond density and higher surface band-bending compared to (-201) orientation [31], [32] and isexpected to exhibit larger SBH, but Yao et. al. [13] showed that a r X i v : . [ phy s i c s . a pp - ph ] J a n Fig. 2. Schematic of energy band diagram of (a) MS and (b) MIS Schottkyjunctions showing the lowering of MIGS with the insertion of SiO interfaciallayer and a possible enhancement of Schottky barrier height. higher barrier heights can be achieved on (-201) orientationwith surface treatments. Farzana et. al. [28] reported a rangeof SBH (1.28-1.97eV) using different metals suggesting thatthe classical Fermi level pinning effect (FLP) may not bethe dominant factor for SC formation on (010) β -Ga O SBDs, but there are other reports on (010) β -Ga O withlower reported barrier heights [18], [24]. Study on (100) and(001) β -Ga O is rather sparse and till date very low barrierheights have been reported for (100) β -Ga O [15], [17], [19],[20], [23], [25], [26], [30]. Furthermore, it is also observedfrom Figure 1 that the SBH on β -Ga O does not show anuniversal trend with the metal workfunction indicating thatsurface/interface states due to defects and crystal orientation,crystal quality and their passivation with different types ofsurface treatment or metal deposition techniques can play avery important role in determining the effective SBH.According to the Schottky-Mott rule, the SBH achieved ata SC is the difference between the metal work function andthe semiconductor electron affinity. However, the Schottky-Mott rule is rarely observed. The effective barrier heightthat is established at a metal-semiconductor interface is ac-tually governed by a combination of various factors suchas metal workfunction difference, interface states and theeffect of image force lowering [23]. The interface states ata metal-semiconductor junction are mostly mid-gap states thatoriginate from the metal wave functions decaying into thesemiconductor band gap and are called metal-induced gapstates (MIGS) [33]. The other contribution to the interfacestates come from the reconstruction of the dangling bonds,defects and localized impurities at the metal-semiconductorinterface [34]. Depending on the density of these interfacestates, the Fermi level gets pinned near one of the band edgesand thus play a very important role in determining the effectivebarrier height that can be measured. The weak dependenceof SBH on the metal workfunction has also been observedand studied in other semiconductor materials like Ge, Si, andInGaAs and is attributed to FLP caused by metal-inducedgap states or defects at the metal-semiconductor interface[34]–[38]. Many groups in the past have reported that theintroduction of a thin interfacial dielectric layer, both in-situand ex-situ, can act as a blocking layer to prevent the spillingof metal electron waves and thus can potentially lower theFLP effect due to MIGS [35]–[38] (Fig 2(b)). This providesa simple and elegant solution to engineer the effective barrierheight by reducing the contribution from MIGS. In this work, we investigate the modulation of Schottky barrier height ondifferent orientations of β -Ga O single crystal substrates withthe insertion of ultra-thin SiO dielectric layer at the metal-semiconductor interface.II. D EVICE F ABRICATION AND C HARACTERIZATION
The 5 mm × × β -Ga O substrateswere acquired from Novel Crystal Tech (Japan). The Zr-doped(100) β -Ga O single crystal bulk substrates were grownby vertical gradient freeze (VGF) method and the detailsare available in reference [39]. The (100)-oriented sampleswere prepared by sawing first and then cleaving along thecleavage plane (100) into samples of 3.5 × × dimensions and the substrate orientation was confirmed byXRD measurements and reported elsewhere [39]. On (010)oriented substrates, the electron concentration and mobilityfrom Hall measurements were measured to be 1.1 × cm − and 89 cm /Vs, respectively. For the (-201) oriented substrates,the electron concentration and mobility values measured were1.7 × cm − and 32 cm /Vs, respectively. From Hall effectmeasurements, the room temperature net electron concentra-tion and mobility were measured to be 1.2 × cm − and 78cm /Vs, respectively in the (100)-oriented samples. It shouldbe noted that the electron concentration is similar for thesamples along all the three orientations considered here for thisstudy. The electron concentrations and doping profile were alsofurther confirmed using capacitance-voltage measurements asdiscussed later in the paper.Six substrates, two of each orientation, were first cleanedusing conventional solvents (acetone, IPA and DI water)followed by dip in Piranha solution (98 % H SO : 32 % H O )-semiconductor (MIS) diodes. Series resistance effectwas dominant in the capacitance voltage measurements onthe (010) and (-201) SBDs necessitating formation of quasi-lateral diodes with concentric Ohmic-Schottky design with 5-30 µ m spacing between the Ohmic and Schottky pads. Forthe (010) oriented substrate, first an extra step of heavily-doped Ga O (100 nm thick, N D (Si) ∼ × cm − ) wasselectively grown in the ohmic contact regions by AgnitronAgilis MOCVD system using 500 nm thick SiO (PECVD)masks to realize good ohmic contacts. Then Ti/Au (50 nm/50nm) was sputtered in the Ohmic contact regions definedby photolithography and lift-off process followed by rapidthermal annealing at 450 o C in nitrogen for 1.5 minutes. Onthe (-201) oriented substrates, first Ti/Au (50 nm/50 nm)Ohmic contacts were sputter deposited and patterned usingphotolithography and lift-off process and no further processingwas needed to realize good ohmic contacts. Following this,SiO dielectric was deposited by ALD (discussed in the nextparagraph) on the (010) and (-201) MIS samples and the oxidein the contact region was etched using a quick dip (10 seconds)in diluted HF solution after patterning by standard opticallithography. Next, 150 µ m and 200 µ m diameter circular Pt/Au Fig. 3. Schematic of MIS diode structures on (a) (010), (b) (-201), and (100)oriented β -Ga O substrates with 3 nm SiO interlayer using Ni Schottkymetal (Pt MIS diodes had identical structures with Pt as anode instead ofNi). The respective MS diodes are similar in structure just without the SiO dielectric interlayer. (50 nm/50 nm) and Ni/Au (50 nm/50 nm) Schottky contactswere sputtered and e-beam evaporated respectively on the MSand MIS samples (both (010) and (-201)) after re-aligningto the ohmic contacts using standard photolithography. Forthe (100) oriented samples, SiO dielectric was first depositedby ALD on the front side of MIS sample and then Ti/Au(50nm/50nm) ohmic contacts were sputtered on the backsideof the sample. Then 150 µ m and 200 µ m diameter Pt/Au(50nm/50nm) and Ni/Au (50nm/50nm) Schottky contacts weresputter deposited and e-beam evaporated respectively on bothMS and MIS samples. The MIS diodes on all three substrateswere not subjected to any high temperature process afterthe ALD dielectric deposition. The processed MIS diodeschematics are shown in Figure 3. The current-voltage (I-V)characteristics and capacitance-voltage (C-V) measurements (1MHz) were performed in air at room temperature ( ∼ % H SO : 32 % H O flow) for 5 minutes. A 3nm thin SiO layerwas deposited on the three substrates for MIS processingat 200 o C using a Cambridge Fiji F200 ALD tool usingtris(dimethylamino)silane (3DMAS) precursor and O plasmasource. The oxide thickness was confirmed by performingoptical ellipsometry on a monitor Si wafer using a Woollam V-VASE spectroscopic ellipsometer tool. The measured thicknessof SiO layer was 3.5 nm on the Si wafer and the SiO formed on the Si wafer due to the remote plasma treatmentwas measured to be 4-5 ˚A. SiO thickness on Ga O ishence estimated to be 3 nm, and this is used as the interlayer Fig. 4. Linear J-V characteristics (200 µ m diameter pad size) of the Pt and NiMS and MIS SBDs on (a) (010), (b) (-201) and (c) (100) - oriented β -Ga O showing the increase in forward voltages with the insertion of ultra-thin SiO and the insets showing their corresponding log J-V characteristics. thickness for further analysis.III. RESULTS AND DISCUSSIONSThe current density-voltage (J-V) characteristics of all therepresentative Schottky diodes at RT are shown in Figure4. Both the metal-semiconductor (MS) and metal-interlayer-semiconductor (MIS) Schottky diodes exhibited highly recti-fying behavior with > ±
2V along the (010) and (-201) orientations (Fig. 4 (a), (b)).
TABLE ISUMMARY OF EXTRACTED SBH FROM J-V CHARACTERISTICS FOR ALL MS AND MIS SBD S USING TE MODELSubstrate Metal q Φ IVB,MS (eV) n MS q Φ IVB,MIS (eV) n MIS ∆ q Φ IVB (eV)(010) Pt 1.18 ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± q Φ IVB,MS , q Φ IVB,MIS = Schottky barrier heights (eV) and n MS , n MIS = ideality factors of MS and MIS diodes respectively from J-V characteristics. ∆ q Φ IVB = q Φ IVB,MIS - q Φ IVB,MS (eV).
The MS diodes on (100) substrates (Fig. 4(c)) were found to beless rectifying. The MIS SBDs showed an increased forwardvoltage compared to the MS diodes, along all the orientationsas expected, indicating that the SBH of MIS diodes might behigher than their respective bare metal MS counterparts, inaddition to the blocking of current due to the band offset atthe SiO /Ga O interface with the insertion of an insulator[40].For moderately-doped semiconductors, generally,thermionic emission (TE) is the dominant transport mechanismin ideal MS diodes [41]. The J-V characteristics of the MSSBDs and MIS SBDs were analyzed using the TE modelwhich can be expressed as J = A ∗∗ T e − qφeffBkT (cid:16) e qVnkT − (cid:17) (1)where, J o = A ∗∗ T e − qφeffBkT (2)where A ∗∗ is the effective Richardson constant, with a cal-culated theoretical value of 41.1 A cm − K − (for electroneffective mass of m ∗ e = 0 . m o ) [10], q is the elementarycharge, k is the Boltzmann constant, V is applied bias voltage, n is the ideality factor, Φ effB is the effective barrier height, J o is the reverse saturation current density, and T is the absolutetemperature. The effective barrier height is then calculated as, q Φ effB = kT ln (cid:18) A ∗∗ T J (cid:19) (3)and the ideality factor, n , is defined as, n = q . kT (cid:16) dlog ( J ) dV (cid:17) (4)The barrier heights and ideality factors extracted from theJ-V characteristics are summarized in Table I. The barrierheights for the MS SBDs were in the range 0.72 eV to1.27 eV with lowest value for Ni on (100) substrate and thehighest for Pt on (010) substrate. The extracted SBH values are comparable to most reports in the literature (Figure 1).The MS Pt and Ni diodes on the (100) oriented substrateexhibited lower barrier heights with higher values of n thanthe other two orientations which indicates higher degree ofcontribution from non-thermionic transport mechanisms. Thiseffect has been observed in other reports on floating zone(FZ), Czochralski (CZ) and EFG grown (100) β -Ga O bulkcrystals [21], [23], [42]. For the MIS SBDs, the extracted SBHwere in a range of 1.21 eV to 1.56 eV with Ni on (-201)being the lowest and Pt on (010) being the highest. Although,this may indicate an improvement in barrier heights with theinsertion of an SiO interlayer, but still these values are anunderestimation as we will see in subsequent discussions.TE model can underestimate the barrier heights for non-idealdiodes (n >
1) due to barrier height inhomogeneities at the MSjunction [41], [43].The MIS SBDs on all the orientations exhibited compar-atively higher n values which is expected and also has beenobserved in previously published reports in other semiconduc-tor systems [44], [45]. The presence of an intentional orunintentional interfacial layer could result in tunneling ofelectrons through the insulator and enhanced surface bandbending at the dielectric-semiconductor interface. Solving themetal-oxide semiconductor electrostatics taking into accountthe voltage drop across the thin oxide and also the interfacetrap charge, the ideality factor for non-ideal MIS Schottkydiodes on n-type semiconductor can be modeled as a functionof interface density of trap states, D it and also the interfaciallayer thickness as done by Card and Rhoderick [44], n = 1 + δ(cid:15) ox (cid:16) (cid:15) s W + qD it (cid:17) (5)where, n is the ideality factor extracted from the TE model, δ is the interlayer oxide thickness, (cid:15) ox is the permittivity of theoxide, (cid:15) s is the semiconductor permittivity, W is the depletiondepth inside the semiconductor, q is the elementary chargeand D it is the interface state density. This model, although, not very accurate when the interface state densities are veryhigh, it can be very effective for estimation of mean D it value, especially for ultra-thin oxides when conventional C-V measurement techniques, such as high-low method, quasi-static measurements become unviable because of very highdissipation losses even at very low forward bias while thedevice is moved from depletion to accumulation. The dualsweep I-V characteristics (-3V to 3V to -3V) of the MISSBDs show very low hysteresis for the (100), (010) and (-201)-oriented substrates indicating minimal charge trappingat the semiconductor-dielectric interface. However, the (-201)MIS SBDs exhibited comparably a little higher hysteresis thanother two orientations which can be attributed to the presenceof higher D it as previously reported [46]. Nevertheless, all theMIS diodes exhibited low hysteresis ( ∆ V < n to estimate D it in the MIS diodes.SBH values extracted from J-V characteristics in general,can underestimate the barrier height because of the barrierheight inhomogeneity and current conduction through local-ized low SBH regions. We performed C-V measurements onboth the MS and MIS diodes along the (010), (100) and(-201) orientations. First, we assume that the voltage dropacross thin dielectric SiO interfacial layer to be negligible.For a Schottky-diode under bias, the C-V relationship can beexpressed as [41], C = A(cid:15) s W = A (cid:118)(cid:117)(cid:117)(cid:116) q(cid:15) s N D (cid:16) V bi − V − kTq (cid:17) (6)and A C = 2 (cid:16) V bi − V − kTq (cid:17) q(cid:15) s N D (7)where, (cid:15) s is the semiconductor permittivity (for β -Ga O , (cid:15) s = 10 (cid:15) o [10], where (cid:15) o = permittivity of free space), V bi is the built-in potential, N D is the doping concentration inthe semiconductor, A is the area of the anode and W is thesemiconductor depletion width. V bi and N D can be extractedfrom the V-axis intercept and the slope of (A/C) -V plotsrespectively. Figure 5 shows the room temperature C-V (inset)and (A/C) -V plots of all the SBDs measured at 1MHz. Anyvariations in the (A/C) -V slopes can be attributed to slightfluctuation in the doping for various Ga O substrates used inthis work. However, the doping profiles were flat (Figure 5(d))for all the three orientations and the net electron concentrationswere similar ( ∼ × cm − ) and matched with the Hallmeasurements. The barrier height is then extracted using theexpression, q Φ B = qV bi + qV n + kT (8) qV n = E C − E F = kT ln (cid:18) N C N D (cid:19) (9)where, E C is the conduction band minima, E F is the Fermilevel and N C is the effective density of states in the conduction Fig. 5. (A/C) -V characteristics of the Pt and Ni MS and MIS SBDs on (a)(010), (b) (-201) and (c) (100) - oriented β -Ga O showing the increment inintercept voltages with the insertion of ultra-thin SiO and the insets showingtheir corresponding C-V characteristics. (d) Net carrier concentration vs depthprofile obtained from C-V measurements of representative devices along threeorientations of β -Ga O substrates used in this work.((010) EFG : 1.02 ± × cm − , (-201) EFG : 1.6 ± × cm − , (100) VGF : 1.4 ± × cm − ) TABLE IISUMMARY OF EXTRACTED SBH FROM C-V CHARACTERISTICS FOR ALL MS AND MIS SBD S Substrate Metal q Φ CVB,MS (eV) q Φ CVB,MIS (eV) q Φ CV,δB,MIS (eV) ∆ q Φ CVB (eV)(010) Pt 1.28 ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± q Φ CVB,MS , q Φ CVB,MIS = Schottky barrier heights (eV) of MS and MIS diodes respectively from C-V characteristics using general C-V method. q Φ CV,δB,MIS =Schottky barrier heights of MIS diodes from C-V method by Cowley. ∆ q Φ CVB = q Φ CV,δB,MIS - q Φ CVB,MS (eV). band which is calculated to be 4.97 × cm − for an electroneffective mass of . m o for β -Ga O [10].Although, the equation (7) in the C-V method can be avery accurate technique for Schottky barrier height extractionfor metal-semiconductor SBDs, it is not appropriate for MISSBDs [44], [45]. This is because it overestimates the V bi values for MIS structures even with very thin SiO layersbecause the dielectric constant of SiO is very low ( (cid:15) ox =3.9 (cid:15) o ) and so the voltage drop across the oxide cannot beconsidered negligible as assumed earlier. The effect of thepresence of an interfacial layer on the V bi extraction from(A/C) -V plots was well studied in the past which shows thatthe oxide layer voltage drop and interface trap charges if notaccounted for can lead to higher extracted values for V bi [44],[45]. Assuming the occupancy of the interface trap charges iscompletely governed by the semiconductor Fermi level and asthe variation of interface trap state density is not too dramatic(of the same order) within the semiconductor band gap, thecapacitance-voltage relationship for a reversed biased n-typeMIS SBD as modeled by Cowley [45] can be expressed as, A C = 2(1 + α ) q(cid:15) s N D (cid:20) (1 + α ) (cid:18) V bi − kTq (cid:19) + (cid:115) V (cid:18) V bi − kTq (cid:19) + V + V α ) (cid:35) (10)and, α = qD it δ(cid:15) ox and V = 2 q(cid:15) s N D δ (cid:15) ox where, δ is the interfacial oxide layer thickness ( ∼ ) and D it is a mean interface trap state density estimatedusing equation (5). The V-axis intercept voltage, V o from thelinear (A/C) -V plots is given by, V o = (1 + α ) V bi + (cid:112) V V bi + V α ) (11) The small correction of kT that arise due to mobile carriersnear the depletion region edge [45] was added to the barrierheight calculation like in equation (8). It can be considered thatV bi extracted from V-axis intercept of the (A/C) -V plot usingequation (11) to be the true V bi for all the MIS devices. TableII summarizes the MIS diode barrier heights extracted usingboth the general C-V method ( q Φ CVB,MIS ) and C-V methodwith correction proposed by Cowley ( q Φ CV,δB,MIS ). It can beseen that the general C-V method applied to MIS diodesoverestimated the V bi and hence the SBH values for all thedevices on three orientations by ∼ q Φ CVB,MS ) values were in the rangeof 0.71 eV - 1.5 eV, a bit higher than those from I-Vmeasurements, as expected. For the MS SBDs, the highestmeasured barrier height (1.5 eV) was on the (010)-orientedsubstrate using Ni as the Schottky metal. On the (-201) and(100)-oriented substrates, the MS Pt SBDs showed highermeasured barrier heights than the Ni SBDs. The (100)-orientedMS SBDs exhibited the lowest barrier heights compared to allother orientations (Pt : : β -Ga O has consistently exhibited lower barrier heights inliterature than the other two orientations (Figure 1).For the MIS SBDs, all the Pt MIS SBDs exhibited higherbarrier heights than Ni for their respective orientations. Thehighest barrier achieved is 1.81eV for the Pt MIS SBDs on(010) substrate. Although Pt MIS SBDs on (010) and (-201)-oriented substrates exhibited considerable increment inSBH (0.53 eV and 0.37 eV respectively), but the Ni SBDsexhibited a bit lower increment in SBH (0.04 eV and 0.02eV respectively). One possible reason could be that either theFLP effect due to MIGS were already low on Ni SBDs or themetal electron wave functions could still be penetrating intothe semiconductor bandgap through the thin SiO interfaciallayer. MIGS penetration through a high bandgap dielectric layer is highly unlikely [37], indicating that FLP effect wasindeed lower to begin with in the case of Ni diodes. ThePt and Ni MIS SBDs exhibited large improvement in theSBHs on the (100) oriented substrates with an incrementof 0.52eV and 0.61eV respectively (Pt : : β -Ga O [13], [24]. Apart fromFLP due to MIGS penetration, oxygen vacancy defect sitesat the surface of β -Ga O has also been predicted to pinthe Fermi-level at specific energy levels (1.3 eV, 1.6 eVand 2.2 eV) below the conduction band edge [14]. Gao et.al. experimentally demonstrated that remote oxygen-plasmatreatment of β -Ga O surface can lead to diffusion of activatedoxygen atoms into the lattice from the surface and thus,reduce oxygen-vacancy related defects [47]. Therefore, wehypothesize that inserting a high bandgap interfacial dielectriclayer (SiO ) blocks MIGS penetration and remote oxygenplasma pretreatment prior to dielectric deposition could pas-sivate oxygen vacancies at the interface which can result inenhanced Schottky barrier heights in β -Ga O .IV. C ONCLUSIONS
In this work, we demonstrate the enhancement of Schottkybarrier heights on three orientations of β -Ga O substrates byinsertion of ultra-thin SiO interfacial layer at the MS junction.Pt and Ni MS and MIS SBDs were fabricated on threedifferent orientations ((010), (-201) and (100)) of β -Ga O to investigate and compare orientation dependence on barrierheight modulation and these devices were characterized byroom temperature I-V and C-V measurements. Pt MIS SBDsshowed on average an increment of 0.37 - 0.53 eV comparedto their MS counterparts. (100)-oriented β -Ga O , in general,has lower barrier heights than the other two orientations.(100)-oriented MIS SBDs showed dramatic enhancement ofbarrier heights (1.5 × - 1.8 × ) and reduction of reverse leakagecurrent on this orientation due to significant enhancement ofSBH with the interlayer dielectric. A promising applicationof this technique can be the realization of Enhancement-modeMESFETs with low gate leakage.A CKNOWLEDGEMENT
This material is based upon work supported by the Air ForceOffice of Scientific Research under award number FA9550-18-1-0507 (Program Manager: Dr. Ali Sayir). Any opinions,finding, and conclusions or recommendations expressed in thismaterial are those of the author(s) and do not necessarilyreflect the views of the United States Air Force. This workwas performed in part at the Utah Nanofab sponsored by theCollege of Engineering and the Office of the Vice Presidentfor Research. We also thank Jonathan Ogle and Prof. LuisaWhittaker-Brooks at the University of Utah for providingaccess to equipment used in this work. R
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