TThe equations of the ideal latches
Abstract . The latches are simple circuits with feedback from the digitalelectrical engineering. We have included in our work the C element of Muller,the RS latch, the clocked RS latch, the D latch and also circuits containing twointerconnected latches: the edge triggered RS flip-flop, the D flip-flop, the JKflip-flop, the T flip-flop. The purpose of this study is to model with equationsthe previous circuits, considered to be ideal, i.e. non-inertial. The techniqueof analysis is the pseudoboolean differential calculus.
Keywords: latch, flip-flop, pseudo-boolean equations. B = { , } is the Boole algebra with two elements. The (normal) signals areby definition the functions x : R −→ B of the form x ( t ) = x ( τ − · ϕ ( −∞ ,τ ) ( t ) ⊕ x ( τ ) · ϕ [ τ ,τ ) ( t ) ⊕ x ( τ ) · ϕ [ τ ,τ ) ( t ) ⊕ ... where R is the time set, ϕ () : R → B is the characteristic function and0 ≤ τ < τ < τ < ... is an unbounded sequence. The equations of the(ideal) latches consist in the next system x ( t − · x ( t ) = x ( t − · u ( t ) x ( t − · x ( t ) = x ( t − · v ( t ) u ( t ) · v ( t ) = 0 (1.1)where u, v, x are signals and x is the unknown. The last equation of thesystem is called the admissibility condition (of the inputs). In order to solvethe system (1.1) we associate to the functions u, v the next sets U k , V k +1 a r X i v : . [ c s . G L ] A p r nd respectively numbers t k : U = { t | u ( t − · u ( t ) = 1 } , t = min U V = { t | v ( t − · v ( t ) = 1 , t > t } , t = min V U = { t | u ( t − · u ( t ) = 1 , t > t } , t = min U V = { t | v ( t − · v ( t ) = 1 , t > t } , t = min V ... and the next inclusions, respectively inequalities are true: U ⊃ U ⊃ U ⊃ ... V ⊃ V ⊃ V ⊃ ... ≤ t < t < t < ... For each of U k ( V k +1 ) we have the possibilities:- it is empty. Then t k ( t k +1 ) is undefined and all U k , V k +1 , t k of higherrank are undefined- it is non-empty, finite or infinite. t k ( t k +1 ) is definedIf U k ( V k +1 ) are defined for all k ∈ N , then the sequence ( t k ) is un-bounded.A similar discussion is related with the sets V (cid:48) k , U (cid:48) k +1 and respectivelynumbers t (cid:48) k : V (cid:48) = { t | v ( t − · v ( t ) = 1 } , t (cid:48) = min V (cid:48) U (cid:48) = { t | u ( t − · u ( t ) = 1 , t > t (cid:48) } , t (cid:48) = min U (cid:48) V (cid:48) = { t | v ( t − · v ( t ) = 1 , t > t (cid:48) } , t (cid:48) = min V (cid:48) U (cid:48) = { t | u ( t − · u ( t ) = 1 , t > t (cid:48) } , t (cid:48) = min U (cid:48) ... For solving the system (1.1) we observe that the unbounded sequence 0 ≤ t ”0 < t ”1 < t ”2 < ... exists with the property that u, v, x are constant in each ofthe intervals ( −∞ , t ”0 ) , [ t ”0 , t ”1 ) , [ t ”1 , t ”2 ) , ... where the first two equations of (1.1)take one of the forms (cid:26) x ( t − · x ( t ) = x ( t − x ( t − · x ( t ) = 0 (1.2) (cid:26) x ( t − · x ( t ) = 0 x ( t − · x ( t ) = x ( t −
0) (1.3) (cid:26) x ( t − · x ( t ) = 0 x ( t − · x ( t ) = 0 (1.4)2s u ( t ) , v ( t ) are equal with 1 ,
0; 0 ,
1; 0 , eq (1 . u ( t ) = 1 , v ( t ) = 0 eq (1 . u ( t ) = 0 , v ( t ) = 1 eq (1 . u ( t ) = v ( t ) = 0 t ∈ ( −∞ , t ”0 ) x ( t ) = 1 x ( t ) = 0 x ( t ) = 0 x ( t ) = 1 t ∈ [ t ” k , t ” k +1 ) x ( t ) = 1 x ( t ) = 0 x ( t ) = x ( t ” k − T able Theorem
Equation (1.1) is equivalent with the equation x ( t ) · u ( t ) · v ( t ) ∪ x ( t ) · u ( t ) · v ( t ) ∪ (1.5) ∪ ( x ( t − · x ( t ) ∪ x ( t − · x ( t )) · u ( t ) · v ( t ) = 1 Proof
The proof is elementary and it is omitted.Equation (1.5) contains three exclusive possibilities: x ( t ) · u ( t ) · v ( t ) = 1 ,x ( t ) · u ( t ) · v ( t ) = 1 , respectively ( x ( t − · x ( t ) ∪ x ( t − · x ( t )) · u ( t ) · v ( t ) = 1equivalent with (1.2), (1.3), (1.4).We solve the system (1.1). Case a) u (0 −
0) = 0 , v (0 −
0) = 0 x (0 −
0) = 0 and x (0 −
0) = 1 are both possible. In order to make a dis-tinction between the two solutions of (1.1) corresponding to the initial value0, respectively to the initial value 1 we shall note them with x , respectivelywith x (cid:48) .a.i) x (0 −
0) = 0a.i.1) U = ∅ the solution of (1.1) is x ( t ) = 0a.i.2) U (cid:54) = ∅ and ∃ ε > , x ( t ) = ϕ [ t , ∞ ) ( t ) for t < t + ε . This fact results by solving(1.4) for t < t and then (1.2) followed perhaps by a finite sequence of (1.4),(1.2), (1.4),. . . in some interval [ t , t + ε ). Furthermorea.i.2.1) V = ∅ the solution of (1.1) is x ( t ) = ϕ [ t , ∞ ) ( t ).a.i.2.2) V (cid:54) = ∅ and ∃ ε > , x ( t ) = ϕ [ t ,t ) ( t ) for t < t + ε . In some interval [ t , t + ε ),we solved (1.3) followed perhaps by a finite sequence of (1.4), (1.3), (1.4),. . .a.i.2.2.1) U = ∅ the solution of (1.1) is x ( t ) = ϕ [ t ,t ) ( t )a.i.2.2.2) U (cid:54) = ∅ and ∃ ε > , x ( t ) = ϕ [ t ,t ) ( t ) ⊕ ϕ [ t , ∞ ) ( t ) for t < t + ε .a.i.2.2.2.1) V = ∅ t < t (cid:48) the solution of (1.1) is x ( t ) = ϕ [ t ,t ) ( t ) ⊕ ϕ [ t , ∞ ) ( t )a.i.2.2.2.2) V (cid:54) = ∅ ...a.ii) x (cid:48) (0 −
0) = 1a.ii.1) V (cid:48) = ∅ the solution of (1.1) is x (cid:48) ( t ) = 1a.ii.2) V (cid:48) (cid:54) = ∅∃ ε > , x (cid:48) ( t ) = ϕ ( −∞ ,t (cid:48) ) ( t ) for all t < t (cid:48) + ε a.ii.2.1) U (cid:48) = ∅ the solution of (1.1) is x (cid:48) ( t ) = ϕ ( −∞ ,t (cid:48) ) ( t )a.ii.2.2) U (cid:48) (cid:54) = ∅∃ ε > , x (cid:48) ( t ) = ϕ ( −∞ ,t (cid:48) ) ( t ) ⊕ ϕ [ t (cid:48) , ∞ ) ( t ) for all t < t (cid:48) + ε ...We have drawn in Figures 1 and 2 the solutions x, x (cid:48) corresponding toCase a) in the situation when t < t (cid:48) , respectively when t > t (cid:48) (the equality t = t (cid:48) is impossible, because it implies u ( t ) = v ( t (cid:48) ) = 1, contradictionwith (1.1)). We observe the fact that x | [ t , ∞ ) = x (cid:48)| [ t , ∞ ) , respectively x | [ t (cid:48) , ∞ ) = x (cid:48)| [ t (cid:48) , ∞ ) thus after the first common value of the (distinct) solutions x, x (cid:48) theycoincide. Case b) u (0 −
0) = 1 , v (0 −
0) = 0the only possibility is x (0 −
0) = 14igure 2: Case a), t > t (cid:48) b.1) V (cid:48) = ∅ the solution of (1.1) is x ( t ) = 1b.2) V (cid:48) (cid:54) = ∅∃ ε > , x ( t ) = ϕ ( −∞ ,t (cid:48) ) ( t ) for all t < t (cid:48) + ε ... Case c) u (0 −
0) = 0 , v (0 −
0) = 1the only possibility is x (0 −
0) = 0c.1) U = ∅ the solution of (1.1) is x ( t ) = 0c.2) U (cid:54) = ∅∃ ε > , x ( t ) = ϕ [ t , ∞ ) ( t ) for t < t + ε ...We have proved the next Theorem If u ( t ) = v ( t ) = 0, the system (1.1) has two solutions x ( t ) = 0and x ( t ) = 1. If u (0 −
0) = v (0 −
0) = 0 but ∃ t > , u ( t ) ∪ v ( t ) = 1, then (1.1)has two distinct solutions corresponding to x (0 −
0) = 0 and x (0 −
0) = 1,that become equal at the first time instant t > u ( t ) ∪ v ( t ) = 1. Andif u (0 − ∪ v (0 −
0) = 1, then the solution is unique.5igure 3: The C element of MullerFigure 4: The symbol of the C element of Muller
We call the equations of the C element of Muller any of the next equivalentstatements: (cid:26) x ( t − · x ( t ) = x ( t − · u ( t ) · v ( t ) x ( t − · x ( t ) = x ( t − · u ( t ) · v ( t ) (2.1)and respectively x ( t ) · u ( t ) · v ( t ) ∪ x ( t ) · u ( t ) · v ( t ) ∪ (2.2) ∪ ( x ( t − · x ( t ) ∪ x ( t − · x ( t )) · ( u ( t ) · v ( t ) ∪ u ( t ) · v ( t )) = 1where u, v, x are signals, the first two called inputs and the last – state.Equations (2.1), (2.2) are the equations of a latch (1.1), (1.5) where u ( t ) isreplaced by u ( t ) · v ( t ) and v ( t ) is replaced by u ( t ) · v ( t ). It is observed thesatisfaction of the admissibility condition of the inputs. The analysis of (2.2)is obvious: x ( t ) is 1 if u ( t ) = v ( t ) = 1, x ( t ) is 0 if u ( t ) = v ( t ) = 0 and6igure 5: The RS latch circuit x ( t ) = x ( t − , x ( t ) keeps its previous value otherwise. The general formof equations (2.1), (2.2) for m inputs u , ..., u m is (cid:26) x ( t − · x ( t ) = x ( t − · u ( t ) · ... · u m ( t ) x ( t − · x ( t ) = x ( t − · u ( t ) · ... · u m ( t ) x ( t ) · u ( t ) · ... · u m ( t ) ∪ x ( t ) · u ( t ) · ... · u m ( t ) ∪∪ ( x ( t − · x ( t ) ∪ x ( t − · x ( t )) · u ( t ) · ... · u m ( t ) · ( u ( t ) ∪ ... ∪ u m ( t )) = 1 The equations of the RS latch are given by Q ( t − · Q ( t ) = Q ( t − · S ( t ) Q ( t − · Q ( t ) = Q ( t − · R ( t ) R ( t ) · S ( t ) = 0 (3.1)and equivalently by Q ( t ) · R ( t ) · S ( t ) ∪ Q ( t ) · R ( t ) · S ( t ) ∪ (3.2) ∪ ( Q ( t − · Q ( t ) ∪ Q ( t − · Q ( t )) · R ( t ) · S ( t ) = 1In (3.1), (3.2) R, S, Q are signals.
R, S are called inputs: the reset input andthe set input and Q is the state, the unknown relative to which the equationsare solved. These equations coincide with (1.1) and (1.5) but the notationsare different and traditional. We conclude the things that were discussedin section 1 by the next statements related with equation (3.2). At the RSlatch, Q ( t ) = 1 if R ( t ) = 0 , S ( t ) = 1; Q ( t ) = 0 if R ( t ) = 1 , S ( t ) = 0; and Q ( t ) = Q ( t − , Q keeps its previous value if R ( t ) = 0 , S ( t ) = 0 . The equivalent statements Q ( t − · Q ( t ) = Q ( t − · S ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · R ( t ) · C ( t ) R ( t ) · S ( t ) · C ( t ) = 0 (4.1)and C ( t ) · ( Q ( t ) · R ( t ) · S ( t ) ∪ Q ( t ) · R ( t ) · S ( t ) ∪∪ ( Q ( t − · Q ( t ) ∪ Q ( t − · Q ( t )) · R ( t ) · S ( t )) ∪ (4.2) ∪ C ( t ) · ( Q ( t − · Q ( t ) ∪ Q ( t − · Q ( t )) = 1are called the equations of the clocked RS latch. R, S, C, Q are signals:. thereset, the set and the clock input, respectively the state. The equations (4.1),(4.2) result from (1.1) and (1.5) where u ( t ) = S ( t ) · C ( t ) , v ( t ) = R ( t ) · C ( t ).The clocked RS latch behaves like an RS latch when C ( t ) = 1 and keeps thestate constant Q ( t ) = Q ( t −
0) when C ( t ) = 0 . We call the equations of the D latch any of the next equivalent statements (cid:26) Q ( t − · Q ( t ) = Q ( t − · D ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · D ( t ) · C ( t ) (5.1)and respectively C ( t ) · ( Q ( t ) · D ( t ) ∪ Q ( t ) · D ( t )) ∪ C ( t ) · ( Q ( t − · Q ( t ) ∪ Q ( t − · Q ( t )) = 1 (5.2) D, C, Q are signals: the data input D , the clock input C and the state Q . Onone hand, from (5.1) it is seen the satisfaction of the admissibility conditionof the inputs. And on the other hand (5.1), (5.2) result from the equationsof the clocked RS latch (4.1), (4.2) where R = S · C and we have used thetraditional notation D for the data input, instead of S . When C ( t ) = 1 , theD latch makes Q ( t ) = D ( t ) and when C ( t ) = 0 , Q is constant.9igure 10: The symbol of the D latchFigure 11: The edge triggered RS flip-flop circuit Any of the equivalent statements P ( t − · P ( t ) = P ( t − · S ( t ) · C ( t ) P ( t − · P ( t ) = P ( t − · R ( t ) · C ( t ) R ( t ) · S ( t ) · C ( t ) = 1 Q ( t − · Q ( t ) = Q ( t − · P ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · P ( t ) · C ( t ) (6.1)and respectively C ( t ) · ( Q ( t − · Q ( t ) ∪ Q ( t − · Q ( t )) · ( P ( t ) · R ( t ) · S ( t ) ∪∪ P ( t ) · R ( t ) · S ( t ) ∪ ( P ( t − · P ( t ) ∪ P ( t − · P ( t )) · R ( t ) · S ( t )) ∪ (6.2) ∪ C ( t ) · ( Q ( t ) · P ( t − · P ( t ) ∪ Q ( t ) · P ( t − · P ( t )) = 110igure 12: The symbol of the edge triggered RS flip-flopFigure 13: The D flip-flop circuitis called the equation of the edge triggered RS flip-flop. R, S, C, P, Q aresignals: the reset input R , the set input S , the clock input C , the next state P and the state Q . In (6.1), (6.2) the signals R, S, C, P and
P, C, Q satisfythe equations of a clocked RS latch and of a D latch and (6.2) represents theterm by term product of (4.2) with (5.2) written with these variables. Thetwo latches are called master and slave. The name of edge triggered RS flip-flop refers to the fact that Q ( t ) is constant at all time instances except C ( t − · C ( t ) = 1 , when Q ( t ) = P ( t −
0) = (cid:26) , if R ( t −
0) = 0 , S ( t −
0) = 10 , if R ( t −
0) = 1 , S ( t −
0) = 0 , this is the so called ’falling edge’ of the clock input. We call the equations of the D flip-flop any of the next equivalent conditions:11igure 14: The symbol of the D flip-flop P ( t − · P ( t ) = P ( t − · D ( t ) · C ( t ) P ( t − · P ( t ) = P ( t − · D ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · P ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · P ( t ) · C ( t ) (7.1)and respectively C ( t ) · ( Q ( t − · Q ( t ) ∪ Q ( t − · Q ( t )) · ( P ( t ) · D ( t ) ∪ P ( t ) · D ( t )) ∪ (7.2) ∪ C ( t ) · ( Q ( t ) · P ( t − · P ( t ) ∪ Q ( t ) · P ( t − · P ( t )) = 1 D, C, P, Q are signals, called: the data input D , the clock input C , the nextstate P and the state Q . We observe that the equations of the D flip-floprepresent the special case of edge triggered RS flip-flop when R = S · C and S was noted with D . The D flip-flop has the state Q constant except for thetime instants when C ( t − · C ( t ) = 1; then Q ( t ) = D ( t − The equivalent statements: P ( t − · P ( t ) = P ( t − · J ( t ) · Q ( t ) · C ( t ) P ( t − · P ( t ) = P ( t − · K ( t ) · Q ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · P ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · P ( t ) · C ( t ) (8.1)and C ( t ) · ( Q ( t − · Q ( t ) ∪ Q ( t − · Q ( t )) · ( P ( t ) · J ( t ) · Q ( t ) ∪ P ( t ) · K ( t ) · Q ( t ) ∪∪ ( P ( t − · P ( t ) ∪ P ( t − · P ( t )) · ( J ( t ) · K ( t ) ∪ J ( t ) · Q ( t ) ∪ K ( t ) · Q ( t ))) ∪ (8.2) ∪ C ( t ) · ( Q ( t ) · P ( t − · P ( t ) ∪ Q ( t ) · P ( t − · P ( t )) = 112igure 15: The JK flip-flop circuitFigure 16: The symbol of the JK flip-flopare called the equations of the JK flip-flop. J, K, C, P, Q are signals: the Jinput, the K input, the clock input C, the next state P and the state Q. Thefirst two equations of (8.1) (modeling the master latch) coincide with thefirst two equations of the edge triggered RS flip-flop where S ( t ) = J ( t ) · Q ( t ) ,R ( t ) = K ( t ) · Q ( t ) and the last two equations of (8.1) (modeling the slavelatch) coincide with the last two equations of the edge triggered RS flip-flop.We observe that the conditions of admissibility of the inputs of the masterand of the slave latch are fulfilled. To be compared (8.2) and (6.2). The JKflip-flop is similar with the edge triggered flip-flop, for example Q changesvalue only when C ( t − · C ( t ) = 1 . Let C ( t ) = 1; because Q ( t ) = Q ( t − Q is constant, in the reunion P ( t ) · J ( t ) · Q ( t ) ∪ P ( t ) · K ( t ) · Q ( t ) ∪∪ ( P ( t − · P ( t ) ∪ P ( t − · P ( t )) · ( J ( t ) · K ( t ) ∪ J ( t ) · Q ( t ) ∪ K ( t ) · Q ( t ))13igure 17: The T flip-flop circuitonly one of P ( t ) · J ( t ) · Q ( t ), P ( t ) · K ( t ) · Q ( t ) can be 1, thus P changes value atmost once and this was not the case at the edge triggered RS flip-flop. Let’smake now in the equations of the D flip-flop D ( t ) = J ( t ) · Q ( t ) ∪ K ( t ) · Q ( t ).We get C ( t ) · ( Q ( t − · Q ( t ) ∪ Q ( t − · Q ( t )) · ( P ( t ) · J ( t ) · Q ( t ) ∪ P ( t ) · K ( t ) · Q ( t ) ∪∪ P ( t ) · J ( t ) · Q ( t ) ∪ P ( t ) · K ( t ) · Q ( t )) ∪ (8.3) ∪ C ( t ) · ( Q ( t ) · P ( t − · P ( t ) ∪ Q ( t ) · P ( t − · P ( t )) = 1Equations (8.2) and (8.3) have similarities and sometimes the equation ofthe JK flip-flop is considered to be (8.3). The next equivalent statements: P ( t − · P ( t ) = P ( t − · Q ( t ) · C ( t ) P ( t − · P ( t ) = P ( t − · Q ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · P ( t ) · C ( t ) Q ( t − · Q ( t ) = Q ( t − · P ( t ) · C ( t ) (9.1)respectively C ( t ) · ( Q ( t − · Q ( t ) · P ( t ) ∪ Q ( t − · Q ( t ) · P ( t )) ∪ (9.2)14igure 18: The symbol of the T flip-flop ∪ C ( t ) · ( Q ( t ) · P ( t − · P ( t ) ∪ Q ( t ) · P ( t − · P ( t )) = 1are called the equations of the T flip-flop. C, P, Q are signals: the clockinput, the next state and the state. The conditions of admissibility of theinputs are fulfilled for the first two and for the last two equations from (9.1)(the master and the slave latch). At each falling edge C ( t − · C ( t ) = 1 ofthe clock input, the state Q of the T flip-flop toggles to its complementaryvalue, otherwise it is constant. The equations of the T flip-flop representthe next special cases: in the equations of the edge triggered RS flip-flop, S ( t ) = Q ( t ) , R ( t ) = Q ( t ); in the equations of the D flip-flop D ( t ) = Q ( t ); inthe equations of the JK flip-flop (any of (9.2), (9.3)) J ( t ) = 1 , K ( t ) = 1.
10 Conclusions
Digital electrical engineering is a non-formalized theory, where the latchesare fundamental circuits. In our work we have given the general form ofthe equations that model the ideal latches, together with the theorem thatcharacterizes the existence and the uniqueness of the solution. Furthermore,we have shown the manner in which this system of equations is particularizedin the case of the most well known latches and flip-flops.The bibliography dedicated to the latches is rich and descriptive (non-formalized). We have indicated at the references a source of inspiration thathas created some order in our thoughts.A possibility of continuing the present ideas is that of considering modelsof inertial latches, for example we can replace (1.1) with x ( t − · x ( t ) = x ( t − · (cid:84) ξ ∈ [ t − d,t ) u ( ξ ) x ( t − · x ( t ) = x ( t − · (cid:84) ξ ∈ [ t − d,t ) v ( ξ ) (cid:84) ξ ∈ [ t − d,t ) u ( ξ ) · (cid:84) ξ ∈ [ t − d,t ) v ( ξ ) = 015here d >