The feedback system for the longitudinal coupled-bunch instabilities in the J-PARC Main Ring
TTHE FEEDBACK SYSTEM FOR THE LONGITUDINALCOUPLED-BUNCH INSTABILITIES IN THE J-PARC MAIN RING
Yasuyuki Sugiyama ∗ , Masahito Yoshii, KEK/J-PARC, Tokai, Ibaraki, Japan.Fumihiko Tamura , JAEA/J-PARC, Tokai, Ibaraki, Japan. Abstract
The J-PARC Main Ring (MR) has achieved the deliveryof the 30 GeV proton beam with the beam power of 500kW to the neutrino experiment in May 2018. The longitu-dinal coupled-bunch instabilities have been observed in theMR for the beam power beyond 470 kW. Since more signifi-cant coupled-bunch oscillation was observed in higher beampower, the mitigation of the coupled-bunch instabilities isnecessary for the stable beam delivery with the beam powerbeyond 500 kW. A new feedback system was developed tosuppress the coupled-bunch instabilities. The feedback sys-tem consists of a wall current monitor, an FPGA-based feed-back processor, RF power amplifiers, and an RF cavity as alongitudinal kicker. The synchrotron sideband componentsof the beam signal picked up by the wall current monitor aredetected by the feedback processor and used for the feedbackcontrol. The single-sideband filtering technique is employedin the feedback processor to control each coupled-bunchmode separately. To accommodate the change of the syn-chrotron frequency during the acceleration, a synchrotronfrequency tracking CIC filter is used as a low pass filter in thesingle-sideband filter. We present the preliminary beam testresults to suppress the beam oscillation with the developedfeedback system.
INTRODUCTION
J-PARC MR
The Main Ring synchrotron (MR) [1] in the Japan ProtonAccelerator Research Complex (J-PARC) [2] is a high inten-sity proton synchrotron which accelerates protons from 3GeV to 30 GeV. The MR delivers the proton beams to theneutrino experiment by the fast extraction (FX). The param-eters of the MR and its RF system for the FX are shown inTable 1. Figure 1 shows the revolution frequency, f rev , andthe synchrotron frequency, f s , in the MR. During the accel-eration from 3 GeV to 30 GeV, the synchrotron frequency ischanging largely from 350 Hz at the injection to 30 Hz at theextraction along with the change of the revolution frequencyfrom 185 kHz to 191 kHz.The MR delivers the 30 GeV proton beam with the beampower of 500 kW, which corresponds to 2 . × protonsper pulse in every 2.48 s, to the neutrino experiment in May2018. During studies toward higher beam intensity, the lon-gitudinal bunch oscillation is appeared to be an issue toachieve higher beam intensities than 500 kW, and it is neces-sary to suppress the oscillation for stable beam accelerationat the beam power higher than 500 kW. ∗ [email protected] Table 1: Parameters of the J-PARC MR and its RF systemfor the FX.parameter valuecircumference 1567.5 menergy 3–30 GeVbeam intensity (achieved) 2 . × pppbeam power (achieved) 500 kWrepetition period 2.48 saccelerating period 1.4 saccelerating frequency f RF f rev h RF N b f rev and the synchrotronfrequency f s in the J-PARC MR from the injection to theextraction. [3] Coupled Bunch Oscillation
For M bunches, there are M modes of the CB oscillationwith the mode number n = ... M −
1. The CB modes canbe seen in the spectrum of the beam signal as synchrotronsidebands of the harmonic components [5]. The CB modesappear as the Upper synchrotron Side Bands (USBs) and theLower synchrotron Side Bands (LSBs). Below the acceler-ating frequency, the LSB and the USB with the CB mode n can be expressed as follows: f USB n = n f rev + m f s (1) f LSB n = ( M − n ) f rev − m f s , (2)where f rev is the revolution frequency, f s the synchrotronfrequency, and m the type of the synchrotron motion. The a r X i v : . [ phy s i c s . acc - ph ] O c t igure 2: The spectra of the synchrotron sidebands cor-responding to the coupled bunch oscillation mode for theJ-PARC MR [4].case with m = m = h =
11 are illustrated in Fig. 2.Based on the analysis of the longitudinal CB oscillation[4], strong CB oscillation of mode n = h = ,
10. The suppression of CBoscillation in this mode is a key to achieve the beam powerhigher than 500 kW.
THE LONGITUDINAL MODE-BY-MODEFEEDBACK SYSTEM RF AMPWall
Current
Monitor RF
CavityHarmonics
Sideband
Detection Feed backReference DACADC
Feedback processor
Beam
FPGA
SUMexisting
LLRF system
Figure 3: Block diagram of the longitudinal mode-by-modefeedback system [3].Figure 4: The frequency response of the impedance of theRF cavity [3].We developed a longitudinal mode-by-mode feedbacksystem to mitigate CB instabilities. Figure 3 shows the block diagram of the longitudinalmode-by-mode feedback system. The feedback system con-sists of a Wall Current Monitor (WCM), an FPGA-basedfeedback processor, RF power amplifiers, and an RF cavityas a longitudinal kicker. The beam signal is detected by aWCM and fed to a feedback processor.The CB oscillation components of the beam signal are de-tected by the feedback processor and used it for the feedbackcontrol. The feedback signal from the feedback processor isled to a high-level RF (HLRF) system consisting of poweramplifiers and an RF cavity.The RF cavity used for the acceleration in the MR is usedas a longitudinal kicker in the feedback system. Figure 4shows the frequency response of the impedance of the RFcavity used for the acceleration in the MR. The RF cavity hasimpedance large enough to generate the kick voltage for thefeedback in the frequency range for h = ,
10 component.Since the existing RF cavity is used as a longitudinalkicker in the feedback system, the feedback system utilizesthe existing HLRF system used in the MR. The feedbacksignal from the feedback processor is summed with the RFsignal from the current low-level RF (LLRF) system for theacceleration [6]. The summed signal is amplified by the RFpower amplifiers and fed into the RF cavity.
FEEDBACK PROCESSOR
We developed an FPGA-based longitudinal mode-by-mode feedback processor for the feedback system. Thefeedback processor was manufactured by Mitsubishi Elec-tric TOKKI Systems Corporation based on the MicroTCA.4architecture.
A/D-D/A AMC module • Developed by
Mitsubishi Electric TOKKI System Co.,Ltd . • • Analog signal through Zone3 (ClassA1.1) Connector • PCI-Ex and GbE through Zone1 AMC Connector • EPICS-IOC running on embedded Linux on Zync FPGA • Enables the remote control and the easy integration into the current control system.
PL(Programmable Logic)PS(Processing System)DDR3-SDRAM 1GBDDR3-SDRAM 1GBQSPI FLASH16MB MMCGEMSD cardPCIeOSC33.333MHz UART/USBTempSensorDual Cortex-A91GHz Mem.Ctl.Mem.Ctl. UARTSDIOwith DMADCM P1 OSC 125MHzPort 0,1Port 4-7DCM
J30
Trg,ITL RX/TX(20:17)DIO P/N(5..0)
Zone3Zone1
MicroUSBMicroUSB8bit SwitchLED GRN,RED GTXI/O Mem.Ctl.I/OI/O I/OZynq IPMIDAC(1..0)ADC(7..0)16bit*2 /JESD204B*8 /ADCDAC CLKCLK
Figure 4: Block Diagram of new A/D, D/A board. 2.3
MTCA.4 Zone3 ClassA1.1 のピンアサイン
MTCA.4 規格のカードにおける
Zone3 推奨コネクタのピンアサイン
Class A1.1 は次のとおりである。
Analog signal transmission zone: (cid:120)
10 channel AC-coupled differential input signals (cid:120)
10 channel DC-coupled differential input signals (cid:120) (cid:120) (cid:120) (cid:120) (cid:120)
Optional dual high-speed link 私たちの新しい
A/D ・ D/A ボードでは、推奨ピンアサインの内、 AC カップルの差動入力を 、 DC カップルの差動出力を 、 AC カップル差動クロック入力を 、 LVDS 入出力を 、別途
TCLK 出力を接続した。これは、
FPGA の外部ピンリソースの関係上必要最低限に集約したためである。
JESD204B 出力の
A/D 変換デバイスの採用
A/D ・ D/A 変換デバイスのサンプリング周波数が速くなり、パラレル信号ではディジタル入出力のサンプリングクロックとのタイミング調整が難しくなってきた。そのため米国の標準化団体
JEDEC にて、パラレルシリアル変換の符号化方式 を利用した伝送方式
JESD204B が策定された。これにより、 デコーダによるクロックデータリカバ リーでデータサンプリングのタイミングが保証される。また、シリアル化により信号線数を削減できることで実装面積を小さくすることができる。 今回採用した
A/D 変換 IC は JESD204B エンコーダを使ってディジタルデータを出力する、入力側の
FPGA には JESD204B デコーダをインプリメントした。設計期間を短縮するために
JESD204B デコーダは、
Xilinx 製の IP コアを採用したが、ここで少し問題が発生した。 Xilinx の開発ツールには従来から使われている
ISE と新しい
VIVADO の 種類があり、それぞれのツールに対応したバージョンの IP コアがある。 IP コアを利用した設計では、パラメータ設定用の Wizard に従い進めていく。
ISE 用に比べて新しい
VIVADO 用の IP コアは、設定できる項目が増えていた。 A/D 変換 IC の JESD204B のパラメータに合せて、まず使い慣れた
ISE で設計を始めた。
FPGA のコンフィグレーションデータを作成して、実機で動作確認を行ったが、正常に
A/D 変換 IC の出力を FPGA で取り込めなかった。次に、
VIVADO 用の IP コアを使って設計したところ、実機にて正常に取り込むことができた。 動作の違いが出た理由を探るために、 Wizard 操作にて自動生成された
ISE 用と VIVADO 用のソースコードを詳しく調べた。
FPGA の高速シリアルインタフェイスのハードブロックである
GTX に与える動作クロック用の設定が異なっていることが分かった。新しいボードの回路構成を踏まえ
ISE 用のソース内の動作クロック用の設定をハンドコーディングで修正した。その結果、
ISE 用の IP コアでも正常に A/D 変換 IC の出力が取り込むことができた。 されている。現在、前面のディジタル信号用のバックプレーンとは別に、μ RTM 用の背面からアクセスできる RF バックプレーンの開発が進められている。また、 Euro-XFEL などで
MTCA.4 を、 LLRF などへ適用が進められている [11] 。 例えば、 LLRF のフィードバック制御システムの場合、μ
RTM の基準信号発生モジュールに加速器のリファレンス信号を入力して、
PLL 等で LO 信号およびサンプリングクロック信号を生成する。これらを RF バックプレーン上の配線を使ってダウンコンバータμ RTM へ伝送する。ダウンコンバータモジュールではパネル面から入力される各ピックアップからの RF 信号を IF 信号に変換して、 Zone3 のコネクタ( ZD コネクタ)を介して伝送され前面の AMC に実装している
A/D 変換回路でデジタイズされる。その後、同じ
AMC 上の FPGA で信号処理をするもしくは、別の
CPU-AMC で演算処理をして
D/A 変換したベースバンド IQ 信号を Zone3 経由でアップコンバータのμ
RTM へ入力しパネル面から RF 信号を出力する。そして、アンプを経由してクライストロンをドライブする。 新しい A/D ・ D/A ボードの構成 私たちが開発した新しいボードを
Figure 3 に示す。
MTCA.4 の広い
RTM に RF 回路を実装して利用するために、 DESY が推奨している
Zone3 のコネクタピンアサイン「
ClassA1.1 」を採用した。 私たちが以前開発した
MTCA.4 規格準拠の
FMC キャリアボードと同じ
SoC FPGA 「 Zynq 」を採用して開発期間の短縮を図った。 つの FMC を実装できる機能をなくした代わりに
A/D ・ D/A 変換 IC を直に実装した。 FPGA 内蔵の
CPU ( ARM Cortex-A9 )で使うワークメモリ(
DDR3-SDRAM )は であ り、ブートメディアは、 SD Card および
QSPI Flash ROM を実装した。
FPGA 内のロジック回路から直接制御できるメモリ(
DDR3-SDRAM )も 実装した。前面パネルには、離れた場所のユニットと高速光通信できるように SFP モジュールを つ実装した。バックパネルに接続される AMC コネクタには
Gigabit Ethernet と PCI Express × 用の高速シリアルインタフェイスを接続した。諸元を Table 1 に、機能ブロックを
Figure 4 に示す。
A/D ・ D/A ボードの単体性能評価ができるように、ダウンコンバータや帯域制限フィルタ機能のあるμ
RTM の代わりに、パネル面の同軸コネクタから RF 信号を入力し平衡信号に変換後、 Zone3 のコネクタに接続する延長ボードを準備した。
AMC ZD コネクタ (Zone3)A/DD/AAMC コネクタ (Zone1) μ RTM RF コネクタ
SFP FPGA
Figure 3: MTCA.4 A/D, D/A Board Zone3 Class A1.1. Table 1: Specifications of New Control Board
FPGA Zynq XC7Z045-1FFG900C OS Xilinx Linux (EPICS-IOC) RAM DDR3-SDRAM 1GiB×2 (PL, PS) FPGA Configuration QSPI FLASH-ROM 16MiB, SD Card, Remote Update ADC 8ch, 16bit, 370MSPS max., BW 800MHz DAC 2ch, 16bit, 500MSPS max. Zone1 (AMC Connector) Port[0:1]:1000BASE-BX, Port[4:7]: PCI Express Gen2 Port[17:20]:M-LVDS, IPMB: IPMI v1.5 support Zone3 (ZD connector) Class A1.1(RFin×8ch,DCout×2ch,CLKin×1,DIO×6pair,TCLKout) SFP 2ports Switch 8bit DIP-switch Front Panel LED Hot swap status (blue), Error status (red), Running status (green) Size PCIMG MTCA.4 Double-Width Full Size 148.5*28.95*181.5 [mm] されている。現在、前面のディジタル信号用のバックプレーンとは別に、μ RTM 用の背面からアクセスできる RF バックプレーンの開発が進められている。また、 Euro-XFEL などで
MTCA.4 を、 LLRF などへ適用が進められている [11] 。 例えば、 LLRF のフィードバック制御システムの場合、μ
RTM の基準信号発生モジュールに加速器のリファレンス信号を入力して、
PLL 等で LO 信号およびサンプリングクロック信号を生成する。これらを RF バックプレーン上の配線を使ってダウンコンバータμ RTM へ伝送する。ダウンコンバータモジュールではパネル面から入力される各ピックアップからの RF 信号を IF 信号に変換して、 Zone3 のコネクタ( ZD コネクタ)を介して伝送され前面の AMC に実装している
A/D 変換回路でデジタイズされる。その後、同じ
AMC 上の FPGA で信号処理をするもしくは、別の
CPU-AMC で演算処理をして
D/A 変換したベースバンド IQ 信号を Zone3 経由でアップコンバータのμ
RTM へ入力しパネル面から RF 信号を出力する。そして、アンプを経由してクライストロンをドライブする。 新しい A/D ・ D/A ボードの構成 私たちが開発した新しいボードを
Figure 3 に示す。
MTCA.4 の広い
RTM に RF 回路を実装して利用するために、 DESY が推奨している
Zone3 のコネクタピンアサイン「
ClassA1.1 」を採用した。 私たちが以前開発した
MTCA.4 規格準拠の
FMC キャリアボードと同じ
SoC FPGA 「 Zynq 」を採用して開発期間の短縮を図った。 つの FMC を実装できる機能をなくした代わりに
A/D ・ D/A 変換 IC を直に実装した。 FPGA 内蔵の
CPU ( ARM Cortex-A9 )で使うワークメモリ(
DDR3-SDRAM )は であ り、ブートメディアは、 SD Card および
QSPI Flash ROM を実装した。
FPGA 内のロジック回路から直接制御できるメモリ(
DDR3-SDRAM )も 実装した。前面パネルには、離れた場所のユニットと高速光通信できるように SFP モジュールを つ実装した。バックパネルに接続され る AMC コ ネクタに は
Gigabit Ethernet と PCI Express × 用の高速シリアルインタフェイスを接続した。諸元を Table 1 に、機能ブロックを
Figure 4 に示す。
A/D ・ D/A ボードの単体性能評価ができるように、ダウンコンバータや帯域制限フィルタ機能のあるμ
RTM の代わりに、パネル面の同軸コネクタから RF 信号を入力し平衡信号に変換後、 Zone3 のコネクタに接続する延長ボードを準備した。
AMC ZD コネクタ (Zone3)A/DD/AAMC コネクタ (Zone1) μ RTM RF コネクタ
SFP FPGA
Figure 3: MTCA.4 A/D, D/A Board Zone3 Class A1.1. Table 1: Specifications of New Control Board
FPGA Zynq XC7Z045-1FFG900C OS Xilinx Linux (EPICS-IOC) RAM DDR3-SDRAM 1GiB×2 (PL, PS) FPGA Configuration QSPI FLASH-ROM 16MiB, SD Card, Remote Update ADC 8ch, 16bit, 370MSPS max., BW 800MHz DAC 2ch, 16bit, 500MSPS max. Zone1 (AMC Connector) Port[0:1]:1000BASE-BX, Port[4:7]: PCI Express Gen2 Port[17:20]:M-LVDS, IPMB: IPMI v1.5 support Zone3 (ZD connector) Class A1.1(RFin×8ch,DCout×2ch,CLKin×1,DIO×6pair,TCLKout) SFP 2ports Switch 8bit DIP-switch Front Panel LED Hot swap status (blue), Error status (red), Running status (green) Size PCIMG MTCA.4 Double-Width Full Size 148.5*28.95*181.5 [mm]
Zone 1
AMC connector Zone 3
ZD connectorRF I/O connector
Figure 5: Pictures of the longitudinal mode-by-mode feed-back processor. [7]Figure 5 shows a picture of the developed feedback proces-sor. The feedback processor consists of an Advanced Mez-zanine Card (AMC) and a Rear Transition Module (RTM).The general purpose AMC module [7] developed by Mit-subishi Electric TOKKI Systems Corporation is used in the evolutionfrequency,phaseSystemClock(144MHz)
PLLADC DACDDSBasebandDemod. BasebandMod SUM synchrotronfrequency,phaseBeamSignal12MHzMasterClock SystemClock(144MHz)16bitBeamSignal
Longitudinal Mode-by-Mode Feedback Module
ZynqFPGA
Single Sideband Feedback Block
RFoutput6 harmonic FB blocks
FBReferenceSSBDemod. SSBMod.
Figure 6: Block diagram of the longitudinal mode-by-mode feedback processor.
I signalto FB
CICCICCICCIC
SynchrotronFrequencyTracking CIC synchrotronphase signalPhaseOffset LUT CORDIC cossin synchrotronfrequencysignal synchrotronharmonicnumber m x32clock f -> f-fsf -> f+fs + ++ --+ ++ IQ I
USB Q USB I LSB Q LSB
Q signalto FB
USB/LSB
USBLSBUSBLSB hfrev BasebandQ signalhfrev BasebandI signal
Single Sideband demodulator
FeedbackOutputI signalFeedbackOutputQ signal
CORDIC cossin synchrotronphasesignal synchrotronharmonicnumber m f -> f-fsf -> f+fs +++--+++ IQ hf rev BasebandI signalhf rev
BasebandQ signal
USB/LSB
USBLSBUSBLSB
PIControlPIControl
ReferenceQ patternReferenceI pattern
Single Sideband modulatorFeedbackBlock +--+
Figure 7: Block diagram of the Single Sideband feedback block.system. The AMC has 8 ADC channels by 4 ADC chips,2 DAC channel with a DAC chip, and an FPGA. A XilinxZynq XC7Z045 SoC FPGA is used as an FPGA on the AMCmodule. In addition to signal processing, an EPICS IOCis implemented in the embedded Linux on the Zynq FPGAand used for remote management of the module. The RTMis used as the signal transition module for the AMC.Figure 6 shows the block diagram of the longitudinalmode-by-mode feedback processor. The feedback processorworks at a system clock of 144 MHz from the RTM module.The frequency and the phase signals are generated in theDirect Digital Synthesis (DDS) block.The digitized waveform of the beam signal is convertedinto the baseband I/Q signal of each harmonic component bya baseband modulator. The synchrotron sidebands for eachCB mode are detected by a single sideband demodulatorusing the single-sideband filter (SSBF) [8] technique. Thecontrol of each CB mode is achieved by the feedback con-trol of each synchrotron sideband component filtered by theSSBF. The outputs of the feedback control are converted tothe RF signal by the single sideband modulator and the base-band modulator. The RF signals are summed and convertedto the analog signal by the DAC. The feedback processorcan process six different harmonic components at the sametime. Single Sideband Feedback
The LSBs and USBs of the synchrotron sidebands in theharmonic component are detected separately by the SSBFto control the oscillation of each CB mode.Figure 7 shows the block diagram of the single-sidebandfeedback block implemented in the feedback processor.In the baseband I/Q signal of the harmonic component,the synchrotron sidebands located at f = ± m f s . By mixingthe baseband I/Q signals with the sine and cosine signal of f = ± m f s , the spectra are shifted so that the components of f = ± m f s locate at f = f = , ∓ m f s components are shifted tothe sideband with f = ∓ m f s , ∓ m f s , respectively.The I/Q signals of the LSB and USB are detected by apply-ing a narrow Low Pass Filter (LPF) to the mixed I/Q signals.The suppression of the baseband signal and unwanted side-bands at the LPF is key to detecting and controlling onlythe selected sideband signal. To accommodate the changein the synchrotron frequency during the cycle, we selecteda 2-stage frequency tracking CIC filter as a narrow LPFin the SSBF. The frequency tracking CIC filter proposedby J.C. Molendijk [9] is a CIC filter that changes its notchposition along with the frequency pattern. By setting the Texas Instruments ADC16DX370 16-bit 370-MSPS ADC Analog Devices AD9783 16-bit 500-MSPS DAC ynchrotron frequency pattern as the first notch frequencyof the filter, the filter can always suppress the baseband andunwanted sideband components while they change their po-sitions during the acceleration. The USB and LSB signalsare detected separately at the SSBF, and the signal of theselected sideband is used as the input signal to the feedbackblock.For the feedback control, a Proportional (P) and an Inte-gral (I) controller is implemented in the feedback logic.After the feedback control, the output I/Q signals fromthe feedback block are modulated to the baseband I/Q signalof the harmonic component after mixing with the sine andcosine signal of f = ± m f s .The sine and the cosine signals for mixing are generatedby the CORDIC. The phase offset to the CORDIC can be setseparately for the LSB and USB to compensate the phasefrequency response of the system. The Look Up Table (LUT)for the phase offset is addressed by the harmonics of thesynchrotron frequency. PRELIMINARY TEST RESULTS
The feedback performance of the developed feedback sys-tem was tested with the beam. In the beam test, one of theaccelerating RF cavities was used as a longitudinal kickerfor the feedback system. The cavity used for the feedbacksystem is only used as a longitudinal kicker without the ac-celerating RF signal from the existing LLRF system. Thebeam loading compensation by RF feedforward method [6]was disabled for the RF cavity.
Beam Excitation
The beam oscillation excited by the feedback system wasused as a controlled oscillation to test the response and theperformance of the feedback system.The excitation measurement was done with the 12-kWbeam low enough to get the stable beam without any longi-tudinal oscillation. The beam excitation was done by settingthe non-zero set point to the reference IQ pattern in thefeedback module. The USB of the harmonic component of h = n = n = n = Phase offset LUT adjustment
The phase frequency response of the feedback systemdue to delay in the cable and in the SSBF at the feedbackprocessor must be compensated to close the feedback loop.The phase frequency response of the feedback systemagainst the synchrotron frequency was obtained from thebeam excitation measurement. The phase frequency re-sponse of the system was calculated from the differencebetween the phase of excitation pattern and the phase of thedetected oscillation .Figure 10: Phase adjustment with the phase offset LUT.igure 10 shows the phase difference between the excita-tion pattern and the detected oscillation phase. The oscilla-tion of the phase difference suggests that the source of thephase response comes from the characteristics of the logicinside the feedback processor rather than the cable delay.After the adjustment of the phase offset LUT, the phase dif-ference was reduced down to less than ± Feedback test
After the phase LUT adjustment, we closed the FB loopand tested the feedback performance of the developed systemto damp the CB oscillation. The feedback performancewas tested against the excited beam oscillation. The sameconfiguration used in the LUT adjustment was used to excitethe beam.Figure 11: Oscillation amplitude of the CB mode n = n = SUMMARY AND OUTLOOK
We have developed a feedback system for the longitudinalcoupled-bunch instabilities in the J-PARC Main Ring. Thefeedback performance of the developed system was testedwith the beam oscillation excited by the feedback system.The phase frequency response of the feedback system againstthe synchrotron frequency was measured with the excitedbeam oscillation and compensated using a lookup table. Weconfirmed the damping of the excited beam oscillation byclosing the feedback loop even though the feedback gain wasnot optimized. We will investigate the best combination ofthe feedback gain of P-control and I-control and perform thebeam test to suppress the beam oscillation growing withoutthe excitation.
ACKNOWLEDGEMENTS
We would like to thank Heiko Damerau for fruitful dis-cussions on the feedback for the CB instabilities. We also would like to thank the Mitsubishi Electric TOKKI SystemsCorporation for their contribution, including the hardwareand the firmware development for the feedback processor.Finally, we would like to thank all members of the J-PARCaccelerator group for their supports.
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Progress of Theoreticaland Experimental Physics , vol. 2012, no. 1, p. 2B004, 2012.Available: http://ptep.oxfordjournals.org/content/2012/1/02B004[2] S. Nagamiya, “Introduction to J-PARC,”
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