The Metastable Behavior of a Schmitt-Trigger
TThe Metastable Behavior of a Schmitt-Trigger
Andreas Steininger and J¨urgen Maier and Robert Najvirt
Vienna University of Technology, 1040 Vienna, Austria { steininger, jmaier, rnajvirt } @ecs.tuwien.ac.at c (cid:13) Abstract —Schmitt-Trigger circuits are the method of choicefor converting general signal shapes into clean, well-behaveddigital ones. In this context these circuits are often used formetastability handling, as well. However, like any other positivefeedback circuit, a Schmitt-Trigger can become metastable itself.Therefore, its own metastable behavior must be well understood;in particular the conditions that may cause its metastability.In this paper we will build on existing results from Marino toshow that (a) a monotonic input signal can cause late transitionsbut never leads to a non-digital voltage at the Schmitt-Triggeroutput, and (b) a non-monotonic input can pin the Schmitt-Trigger output to a constant voltage at any desired (also non-digital) level for an arbitrary duration. In fact, the output caneven be driven to any waveform within the dynamic limits ofthe system. We will base our analysis on a mathematical modelof a Schmitt-Trigger’s dynamic behavior and perform SPICEsimulations to support our theory and confirm its validity formodern CMOS implementations. Furthermore, we will discussseveral use cases of a Schmitt-Trigger in the light of our results.
I. I
NTRODUCTION
It is a fundamental task in digital computation to discrimi-nate the analog voltage levels carried by the signal rails in thephysical implementation in two logical classes, namely thoserepresenting a logic HI and those representing a LO. Thatcan normally be managed by the conventional input stagesof logic gates. However, when there is a need for handlingless “clean” signals with intermediate voltage levels, slowtransitions, or large noise, special provisions are required. Thismay happen at interfaces or when external disturbances comeinto play, or in case of metastability of an internal bistableelement which can also be caused by clean but badly timedsignals. The standard solution for this is the use of a Schmitt-Trigger (S/T) circuit. Unlike a plain discriminator circuit thatuses just a single constant reference voltage V T for separatinginto HI (above V T ) and LO (below V T ) digital values, the S/Texhibits a hysteresis at its input by switching the referencevoltage between V H and V L (with V H > V L ) in dependenceof its current output state, with V H being applied when theoutput is LO and V L for a HI output . This facilitates stabilityagainst noisy input voltages in the proximity of the thresholdthat typically cause the discriminator to oscillate. This research was partially supported by the SIC project (grantP26436-N30) of the Austrian Science Fund (FWF). For the conceptual part of our analysis we consider a non-inverting S/T,while later, in context with the practical design we will study its invertingversion that is easier to implement.
Clearly, the original intention of the S/T, namely to dis-criminate a continuous input voltage space into two sub-spaces, does not imply a stateful behavior. However, thehysteresis behavior desired for noise immunity does. Thiscaused some uncertainty about whether a S/T can becomemetastable. Thanks to the results of researchers like Marino[1] and Chaney [2] it is today clear that a S/T, like any othercircuit relying on positive feedback, cannot be protected frommetastability and will therefore exhibit irregular behavior forsome input voltage traces. Still S/Ts are sometimes proposedfor filtering metastable outputs of bistable elements [3], orfor uniquely classifying the logic level of a node that isintentionally left floating for some time in order to leveragethe parasitic capacitance as a dynamic storage element [4], [5].So one may ask whether such approaches can actually work.In other cases (e.g. [6]), it is hoped that for input voltages withrestricted dynamics a S/T will never experience metastability.Again something to check for in more detail.In this paper we extend existing results – mainly those fromMarino [1] – to answer some of these questions that frequentlyplague designers in practice. To this end we will, after giving abackground in Section II, characterize the metastable behaviorof the S/T in detail and compare it to that of a typicalbistable element (e.g. latch) in Section III. Since metastabilityis usually a very rare phenomenon that eludes an experimentalevaluation, our aim is to give theoretically well foundedanswers and particularly identify those conditions under whichmetastability of the S/T can be ruled out for sure. Here wewill investigate different scenarios like monotonic and slowlychanging inputs. Next, in Section IV we will validate ourtheoretical results by selected SPICE simulations. In Section Vwe will investigate concrete use cases of a S/T in the light ofour findings. Finally, in Section VI we will conclude our paper.II. B
ACKGROUND
A. Metastability
Metastability is the phenomenon when a bistable elementpersists in an unstable equilibrium, the metastable state, fora prolonged time. The existence of a metastable state is afundamental property of every bi- or multistable system –between every two stable equilibria there necessarily is anunstable equilibrium. The difference lies in the behavior whenthe equilibrium state is slightly disturbed: The system wouldreturn to a stable state, however, upon the slightest disturbancefrom a metastable state, the latter is left in favor of either ofthe stable states. a r X i v : . [ c s . OH ] J un t is well understood [7] that every bistable element canbe brought to a metastable state in which it may rest for anunbounded time. The manifestation of the metastable state canbe oscillation or “creeping” [8]. In the creeping case, which ismore relevant here, we know that the classical bistable storageelements (latch, Muller C-element) drive their output at first toa specific “metastable” voltage level V meta , where it stays foran unbounded amount of time, before resolving to one of thestable saturation states. Due to their function V meta must be inbetween their regular HI and LO states, and, due to symmetryin the design, it is typically an intermediate voltage levelin the undefined range V xx . With an appropriately designedthreshold of the subsequent stage this creeping behavior canbe transformed into a so-called late transition where the outputof that stage shows a clean transition (i.e. fast crossing of theintermediate levels) but only after metastability has resolved.However, with a single threshold (i.e. without hysteresis) onealso introduces the risk of glitches [3].Metastability is a very undesired phenomenon, as V meta may, beyond the above-mentioned glitches, lead to different(“Byzantine”) interpretations by input stages it supplies (asthese will most likely have slightly different thresholds), whilea late transition can cause timing violations downstream.Unfortunately, in general it can not be avoided completely.Note that the above applies to bistable storage elements,whose metastable behavior is already well researched – wewill have to revisit this for the S/T. B. Feedback Circuits
The arrangement shown in Fig. 1 represents the fundamentallayout of a feedback circuit. A linear voltage amplifier withgain A receives as its input the sum of an external input voltageand its own output voltage multiplied with a factor of k . Its(static) transfer characteristic can be described by G = V out V in = − k − A (1)+ kA V in V out Fig. 1: Basic structure of a feedback circuitIn the case of k < we have negative feedback . For themoment, let us assume A = ∞ . Then the arrangement operatesas an amplifier with (positive) gain G of − /k . For k = − we feed back the full output voltage and obtain G = 1 , i.e. avoltage follower. For k = 0 we have no feedback, hence an open loop . This arrangement resembles the function of an idealdiscriminator whose output assumes the positive saturationvoltage M in case V in > and changes to the negativesaturation − M as soon as V in < . For simplicity of explanation we assume symmetric saturation voltages,i.e. +M and -M here. Although the quantitative results will differ in theasymmetric case, our reasoning and our basic conclusions will still hold.
With k > we realize positive feedback . Now every littlechange ε on the input produces a change on the output in thesame direction that gets fed back and thus further supports theoriginal input change by being added to ε . This self-supportingchain ultimately causes V out to run into positive or negativesaturation. In this situation the loop feeds back a voltage of V F B = M k (or − M k , respectively) that must be compensatedin the summation by the input voltage, i.e. V in < − M k (or V in > M k , respectively) to move the output to the otherdirection, where it again saturates. This resembles the functionof a Schmitt-Trigger with hysteresis V hyst = V H − V L = 2 M k . V in V out M − M (a) k = − V in V out M − M (b) k = 0 V in V out M − MV H V L (c) k = + Fig. 2: Transfer characteristic of a feedback circuitFig. 2 shows the characteristics V out over V in for differentselections of k . We observe that for negative feedback wehave a unique mapping from V in to V out , while for positivefeedback V out depends on the current state for V L ≤ V in ≤ V H , i.e. we have a hysteresis behavior. Note carefully thatthe saturation states are the only “truly” stable states of theS/T. The line described by Eq. 1 describes the metastablestates only. A very intuitive explanation of this fact is thatfor a given input voltage V L ≤ V in ≤ V H we can draw avertical line to find the corresponding steady-state values of V out . This line has three intersections with the characteristic,namely at the positive and negative saturation, as well as onein between. Since we know that the saturation states representtruly stable states, there must be a metastable state in between– irrespective of the implementation. The transient behavior,i.e. the transition from one saturation voltage to the oppositeone, depends on the dynamic characteristics of the circuitwhich are not considered in the basic model in Fig. 1.For a non-ideal amplifier with A < ∞ we obtain a reductionof the effective k by A (see Eq 1). In case of negative feedbackthis reduces the overall gain accordingly, and in case of theS/T it moves the thresholds towards a reduced hysteresis.The borderline case of discriminator operation now occurs for k = A . Apart from that shift in the value of G (that canbe compensated by appropriate dimensioning), all qualitativefindings from above, however, remain the same. In Fig. 2we would, e.g., simply have to replace all instances of k by k − A . Furthermore, a reference voltage can be added to thefeedback path to create a hysteresis that is no more centeredaround V in = 0 . Again, while this shift obviously changes thequantitative results, the qualitative findings still hold. C. Schmitt-Trigger Implementation
A straightforward implementation of the principle fromFig. 1 is by means of an operational amplifier (OpAmp). SincepAmps usually have a high gain, this implementation is closeto the ideal case of A → ∞ .For negative feedback the feedback path is simply connectedto the inverting input, thus effectively realizing the negativesign. For positive feedback the non-inverting input of theOpAmp must be used, which leaves only the inverting inputfor connecting V in . This means that from the view of the inputvoltage the function of the S/T circuit is inverting.In both cases a resistive voltage divider can establish | k | = R B R A + R B < , and the feedback path can be augmented with areference voltage source V R that will create a horizontal shiftof the characteristic. In case of positive feedback this resultsin a shift of the threshold voltages by an amount of (1 − k ) V R .In digital CMOS logic circuits OpAmps are expensive torealize. Therefore a different circuit structure has becomecommon, namely a kind of extended inverter stack withfeedback from the output, as shown in Fig. 3. V in V out V DD M M M M M M Fig. 3: Conventional CMOS S/T implementation (from [9])There are different variations to this basic scheme, targetingat low supply voltage [10] or adjustable thresholds [11], [12].In [9] a detailed mathematical analysis of this circuit is given.
D. Metastability Model for the Schmitt-Trigger
There has been (and sometimes still is) uncertainty whetheror under which circumstances a S/T is prone to metastability,as its function of classifying an input voltage (rather thanstoring data) appears combinational. However, as Fig. 2 andthe associated explanation in Sec. II-A show, every positivefeedback circuit must have a metastable state. Note, that thiscurve resembles a general model of a positive feedback circuitwithout being limited to a specific implementation.Fig. 4 shows how an RS-latch can be constructed from aS/T. This gives an intuition that the latter must have storagecapabilities. It also indicates that building a perfect S/T isequivalent to building a perfect RS-latch, which we know isimpossible [7].There has also been quite some debate on whether a S/T canbe applied to construct a synchronizer flip flop that is immuneagainst metastability (e.g. [13], [2]). This discussion has beenresolved in a paper by Marino [1] in which he proposes adynamic model for the S/T circuit as follows: He augments M P M N R P R N RS QV DD Fig. 4: RS-latch implementation based on a S/Tthe OpAmp realization with a low-pass ( R C ) at the output toaccount for its dominant time constant, and thus approximatesthe dynamic behavior in the model. He assumes another RCelement at the inverting input and a reference voltage V R toobtain thresholds that are not bound to be symmetric around0. A simplification of his model circuit used in this paper isshown in Fig. 5. To be more general, we will, compared toMarino’s circuit, drop the input RC element, and we use moreintuitive names ( V in for V and V out for V q ). − + V in R C V out R A R B V R Fig. 5: Dynamic model of the S/T inspired by Marino [1]As the saturation requires separate treatment, his solutioncomprises three regions, namely upper and lower saturation(Regions 1 and 3), as well as the “linear region” 2 betweenthem. Fig. 6 illustrates his solution. Note that, according tothe implementation of the model circuit, this diagram appliesto an inverting S/T. V in V out V in = R A V R + R B V out R A + R B − MA V in = R A V R + R B V out R A + R B + MA V out = γ V out = γ V out = γ REGION 1REGION 2 REGION 3
Fig. 6: Phase diagram for the S/T inspired by Marino [1]The dashed lines in the figure represent the borders betweenthe regions (the corresponding equations are shown as well).hey are derived by determining those values for the OpAmp’sdifferential input voltage for which it starts to saturate. Ul-timately, Marino obtains the following equations (for theirdetailed derivation please refer to the original paper):Region 1: dV out dt = V (cid:48) out = − τ ( V out − γ ) (2)This yields a decaying exponential function with time constant τ ≈ R C that asymptotically approaches the truly stable restpoint γ ≈ M .Region 2: dV out dt = V (cid:48) out = 1 τ ( V out − γ ) (3)This time we have a growing exponential function with timeconstant τ ≈ R C kA − that moves away from the metastablerest point γ ≈ V in − (1 − k ) V R k − A . Note that this rest point nowdepends on the input voltage.Region 3: dV out dt = V (cid:48) out = − τ ( V out − γ ) (4)Similar to Region 1 this yields a decaying exponential functionwith time constant that asymptotically approaches the trulystable rest point γ = − γ ≈ − M .Marino uses this model to show that a S/T can neither beused to build a perfect inertial delay element nor a perfectsynchronizer. Although his model clearly shows that a S/T mayindeed become metastable, in his argumentation he is mainlyconcerned with the question of whether it can be driven toproduce runt pulses or glitches at its output. He shows that thisis indeed possible, even if restrictions for the input are applied.He does, however, not consider other metastability effects liketransition delay or constant output voltage and under whichcircumstances these occur. Similarly, Nystr¨om and Martin [4]as well as Greenstreet [5] limit their discussions to the specialcase of monotonic input voltage only.In this paper we build on Marino’s model, but extendthe scope towards typical use cases, validate the model fora modern CMOS implementation, provide a more generaltreatment of the metastable behavior of a S/T, and give adeeper analysis of the case of monotonic input voltage thanin [4], [5].III. A NALYSIS OF M ETASTABLE B EHAVIOR
A. Peculiarities in the Schmitt-Trigger’s metastable behavior
Fig. 6 suggests that a S/T can assume different metastablepoints V meta ; in fact along the whole line γ . This is sub-stantially different from what is known for typical bistablestorage elements, whose (internal storage cell’s) metastableoutput voltage is confined to a single value in the V xx range.The metastable behavior of a latch cell has been first modeledby Veendrick [14], and his analysis forms the theoreticalfoundation of what we know about metastable behavior ofbistable storage elements today. So let us compare Marino’smodel with that used by Veendrick to spot the differences. In both models a linear amplifier is employed, and its dynamicbehavior is approximated by a first order low pass. So notsurprisingly the solutions are exponential functions in bothcases and hence similar. However there are two importantdifferences:1) For his latch circuit Veendrick assumes the input to bedecoupled (opaque state) and just studies the homoge-neous behavior, while Marino, for his S/T model needsto leave the input voltage connected all the time. Asa result, Marino’s solution shows a dependence of themetastable rest point on the input voltage in Region 2,rather than just a single metastable point.2) As a consequence of (1), Veendrick could concentratehis analysis on the proximity of the metastable point,while Marino had to consider the whole operating rangeand therefore needed the case separation.So (1) gives us an intuitive confirmation why the S/T has awhole range of metastable points. Conceptually, this appearsto be due to the fact that, having only one input, the S/Tderives its trigger for the state change from the amplitude ofthis single signal, making a constant observation necessary,while all bistable storage elements have two inputs and canhence decouple either of them temporarily. B. Regular operation
We will base most of our reasoning on the phase diagram(Fig. 6). So let us first observe the normal operation of theS/T there: We start in the positive saturation in Region 1 (forthe rest of the paper we will always consider the positive sat-uration as a starting point, while due to symmetry, equivalentarguments can be given for starting in the negative saturation)As we increase V in we move along γ until we reach V H . Upto this point we have no freedom in choosing the trajectory,and the shape of V in is irrelevant. Only after crossing V H theS/T will leave the stable state and start moving towards thenegative saturation. During this phase – and only then – wehave the opportunity to manipulate the trajectory and force theS/T back to the initial state, or maneuver it into a metastablestate. Here the shape of V in matters a lot. We will investigatemore details on that later. Once in the negative saturation, thesame procedure starts over in the other direction. C. Monotonic input
Let us again start on some point along γ . Exceeding V H then implies a positive slope of V in , and all trajectoriesreachable with a monotonic V in are hence within the half plane V in > V H where there is no metastable point (recall that thelatter are all located on γ ). In fact V in need not even bemonotonic, as long as it does not fall back to below V H .Fig. 7 shows the first derivative dV out /dt over the phasediagram according to Eq. 2 to 4. We have chosen A = 10 forthis plot, which is way too low for a typical OpAmp, but forhigher values Region 2 would be hard to recognize (its widthis just MA ). V (cid:48) out represents the speed at which the trajectoryis pulled upward ( V (cid:48) out > ) or downward ( V (cid:48) out < ) by theinternal dynamics of the circuit. We observe that if, starting . . . . . − . − . − . . . . V in [V] V o u t [ V ] − V o u t Fig. 7: Derivative of the output voltage over the phase diagramfrom positive saturation, we apply a step function to moveto an operating point very close to but above the threshold,say ( V in , V out ) = ( V H + ε, γ ) the downward speed V (cid:48) out isclose to zero, so V out will initially change very slowly. Thissuggests we obtain a slow output transition. To determine theduration of this transition, let us first assume our step inputtakes us right into Region 3, i.e. ε > MA . Then for constant V in = V H + ε , Eq. 4 predicts a decaying exponential functionfrom γ towards γ according to V out ( t ) = ( γ − γ ) · e − tτ + γ (5)Now we assume a threshold V th for the subsequent stageto recognize V out as being LO with V th = γ + σ · ( γ − γ ) ,with < σ < giving the proportion of the swing that V th is apart from the final value (that is reached asymptotically).This value will be reached with a delay of D III = τ · ln (cid:18) σ (cid:19) (6)after having applied the input step. Note that, as long as weremain within Region 3, this value is independent of V in (andhence ε ) and therefore stays the same, even if we apply largersteps. It is the minimum switching time of the S/T.For ε ∈ [0 , MA ] we start the trajectory in Region 2. Againwith constant V in it will move downward and cross theboundary to Region 3 at some point. Up to that point V out will follow a growing exponential function according to V out ( t ) = − ε + γ − MA k − A · e tτ + γ k − MA + εk − A (7)and the time needed for the trajectory to move throughRegion 2 becomes approximately D II = τ · ln (cid:18) MAε (cid:19) . (8)At the region boundary the decaying function from Eq. 5will take over. Fig. 8 shows a simulation result (for details onthe setup see Section IV) that illustrates the situation.The transition time is the sum of D = D II + D III (with asmall error due to D III actually being valid for the full swing). V o u t [ V ] = 205 = 65 = 21 = 9= 0.5 ε ε ε εε Fig. 8: Falling output transitions for different ε in mVThe simulation results for the CMOS implementation shownin Fig. 8 confirm that the simplified OpAmp model does agood job in predicting the behavior. In particular one can verifythat D II dominates, especially for small ε . It is interestingto note that using Veendrick’s model [14] for calculating therequired resolution time D meta of a latch from a metastablestate yields, similar to our result, a D meta proportional to themetastability time constant τ C and to ln ( V ∆ ) with V ∆ beingthe initial voltage disparity.The γ n lines are by definition the only places where V (cid:48) out becomes zero. So, due to the continuity of V (cid:48) out proven in [1],the sign of V (cid:48) out stays the same as long as we do not cross a γ n line. This can also be verified in Fig. 7. As a consequence wehave a strictly decreasing V out in the above cases of ε > ,even if the start may be arbitrarily slow. Although this canbe regarded as what is normally called a late transition inthe context of bistable elements, we have a fundamentallydifferent metastable behavior in the S/T: This late transition isdue to resolution of a metastable state that is associated witha clean HI level. In contrast, for bistable storage elements themetastable state is necessarily associated with resting at anintermediate voltage in the range V xx between the element’sclean HI and LO outputs, and the late transition is a secondaryeffect caused by applying a high or low threshold [3]. D. Producing a constant output voltage
Let us now study the possibility of driving the S/T intoan arbitrary metastable state: Assume we start again on γ .Once V in exceeds V H our operating point is right of γ ,and the internal dynamics of the S/T is moving us downward( V (cid:48) out < ). In order to reach a metastable operating point on γ we need to reduce V in fast enough to make the trajectoryintersect with γ before the negative saturation is reached. Dueto the inclination of γ the amount by which we have to reduce V in grows as V out moves downward. In addition, V (cid:48) out < becomes larger with the operating point’s distance from γ .So once that distance is large, it takes a highly dynamicchange in V in to reach a metastable point. Contrariwise, whenstaying close to γ right from the start, V (cid:48) out can be kept asmall as desired, leaving enough time for an arbitrarily slowchange in V in to reach a metastable point on γ at any desiredintersection point.As can be seen in Fig. 6, γ provides a one-to-one mappingbetween V in and V out . So with an appropriate choice of thefinal value of V in (i.e. once having the threshold crossingsaccomplished), any value of V out can be selected. Notice thatthis property allows us to freely select the metastable outputvoltage of the S/T based latch sketched in Fig. 4 by properadjustment of the voltage divider. E. Creating an arbitrary output shape
In principle, by appropriately navigating in the phase di-agram one can obtain any desired shape of V out : For everycurrent value of V out an appropriate V in can be applied toobtain the desired gradient V (cid:48) out (by crossing γ even thesign can be changed). However, with a limited range of V in only a limited range of V (cid:48) out can be covered (see Fig. 7); inother words, the dynamics of V out is naturally limited by thesystem dynamics. The second limitation is the dynamics of V in . Assume an operating point with a horizontal distance X and vertical distance of Y = α · X from γ , with α ≈ k − A being the slope of the latter. According to Eq. 3 V (cid:48) out has avalue of Yτ at this point. Moving the trajectory closer towards γ takes a V (cid:48) in larger (in absolute value) than V (cid:48) out α . So for agiven maximum gradient ˆ V (cid:48) in , we obtain a maximum allowedhorizontal distance from γ of | X | < τ · | ˆ V (cid:48) in | . Once theoperating point leaves this corridor around γ , there is no wayof preventing the trajectory from approaching the saturation of V out in a monotonic trace (For a more elaborate and formaltreatment see [1]). IV. E VALUATION
A. Setup and characteristic
To validate our analyses we implemented S/Ts based on anideal OpAmp, which matched the theoretical model perfectly,a commercial OpAmp (Type EL5165), which showed onlyminor deviations, and the CMOS circuit from Fig. 3 inHSPICE. As the latter is substantially different from Fig. 5we wanted to investigate whether Marino’s model sufficientlycovers its behavior. It was implemented using transistor pa-rameters of a standard inverter cell from an industrial 65 nmtechnology library, whereat despite a fF output load nointerconnect parasitics were considered. The resulting input-to-output characteristic is shown in Fig. 9. It matches thetheoretical model (Fig. 6) well, however γ turns out to benot straight but shows an increased slope at the ends. It wasdetermined point by point, in each case starting a transientanalysis with a preset pair of ˚ V out and ˜ V in . By sweepingthe value of ˜ V in we determined the matching ˚ V in for whichthe transient analysis showed stable behavior. The dots in thefigure represent V (cid:48) out , with gray dots for positive values andblack dots for negative ones, and with large dot size indicatinga large value. The large “corridor” around γ points to a wideRegion 2 and hence a low gain A . In addition, we observe a dependence of V (cid:48) out on γ in the upper right and lower leftcorner that is not present in the ideal model in Fig. 7. Thequalitative results from Section III, however, only require V (cid:48) out to be consistently positive (negative) on the left (right) side of γ and continuous, so they still hold.We also analyzed the CMOS circuit using transistor equa-tions to derive an analytical expression for γ (dashed linein Fig. 6). By searching for equilibrium states, i.e. where aconstant input leads to a constant output voltage, an explicitformula V out ( V in ) could be derived, assuming transistors M and M operate in their linear region and all others in thesaturation one. Unfortunately this assumption is only valid inthe middle of the metastable region; at the edges the transistors M and M respectively M and M start to enter their linearoperation region. For that reason the analytic expression, whilematching with Marino’s OpAmp model, does not fit well tothe real curve near V H and V L . in [V]0.00.20.40.60.81.01.2 V o u t [ V ] Fig. 9: Derivative of the output voltage over the phase diagram
B. Evaluation of the scenarios from Section III
Our claim was that monotonic input signals will alwayslead to strictly monotonic outputs. In the simulation shown inFig. 10 we verified the worst case by applying a ramp inputstopping at a constant input voltage close to V H , i.e. V H + ε (dark lines). One can clearly see that in both cases the outputtransitions are very steep (all with about the same transitiontime) but, as theory predicts, their delay varies significantlyeven for small changes in ε .Fig. 11 illustrates the observed dependence of the outputdelay on ε in a more global scope. This nicely confirms Eq. 8.Fig. 12 shows that it is indeed possible to force the S/Tto output arbitrary waveforms by means of non-monotonicinputs. In the first part, the figure shows regular operation todemonstrate the dynamics of the S/T as well as its thresholds.Starting at 20 ns, the S/T is driven to output a 100 MHzsine with 0.5 V swing. Note that this requires keeping theS/T metastable. Finally, the simulated S/T is driven intodeep metastablity with the input being constant from 58 nssimulation time. Here, the results of two simulations can beseen. In the first, metastability resolves to V DD , in the second,it resolves to GND .
10 20 30 40 50time [ns]0.00.20.40.60.81.01.2 v o l t a g e [ V ] V in V out Fig. 10: Late transitions caused by ramp input going slightlyabove V H In the phase plot, it can be seen that the generation of theslow (w.r.t. its regular switching speed) sine required to keepthe output close to the γ line. The resolution of the metastablestate can also be seen as vertical line segments at V in ≈ . V .This verifies the predictions from Sections III-D and III-E. Aconstant output voltage can either be generated as an arbitrarywaveform by actively controlling the input, or by forcing theS/T into perfect metastability. As before, small changes at V in lead to huge variations in the time progress of V out . The twooutput traces shown in the figure correspond to input tracesonly deviating in their final stable voltage by less than . µ V(not distinguishable in the figure). Clearly, if the appropriatevoltage is set with a sufficient precision, it can take an arbitrarytime for the metastability to resolve.Nevertheless, in these simulations we experienced that ittakes an extremely precise control of the voltage (nV) in orderto get close enough to γ such that slow inputs still createvisible metastability effects, as theory would predict.V. P RACTICAL U SE C ASES
A. Handling of intermediate voltages
Often a S/T is applied as a means for converting theintermediate voltage V meta produced by a metastable binarystorage element into a clean HI or LO, like e.g. in [3]. As wehave seen in our analysis in Section III-C this will actuallywork under two important conditions: (1) The input of the S/T must indeed be monotonic , at leastin the proximity of the thresholds. This can be easily accom-plished in a typical setting, where the (single!) intermediateoutput voltage V meta is near the middle of the supply range.With thresholds chosen in appropriate distance from V meta one can ensure that these are crossed only when metastabil-ity is already resolving, i.e. with an increasing exponentialfunction that is strictly monotonic (for details see [14], [15]).However, care must be taken that it is indeed the S/T thatdecides upon the classification of V meta . As soon as any otherstage (decoupling buffer, e.g.) is in between the metastability-producing element and the S/T, that element’s (single!) input
80 60 40 20 0 20 40 60 80 100 [mV]0510152025 l a t e t r a n s i t i o n d e l a y [ n s ] V in fallingV in rising ε Fig. 11: Observed dependence of output delay on ε threshold will typically classify V meta in an undesired way.More specifically, glitches can be produced [3], with the S/Thaving no chance to mitigate these. (2) A delay introduced by the S/T must be accommodatedin the timing of the subsequent logic. With properly selectedthresholds as outlined above we can assume steep inputtransitions, so the S/T will not by itself introduce the arbitraryresolution delay discussed in Section III-C. Still it may take anunbounded time until the metastability of the bistable storageelement resolves, during which the S/T observes a constant V meta at its input. As its threshold is crossed only after that,the S/T appears to produce a late transition. This is actually anintended behavior, useful for handling metastability in a valuesafe system, like a speed-independent design [3].Essentially, (2) is the reason why Chaney [2] and Kleemanet al. [15] correctly state that the use of S/Ts is not beneficialfor avoiding metastability in a synchronizer and even degradesthe performance. Marino [1], on the other hand, was concernedwith inputs not limited to monotonic slope. Therefore hisconclusion was, similarly, that the S/T is not useful in avoidingmetastability. As we have laid out, however, for the special ap-plication of filtering of intermediate voltages from a metastablebistable storage element in value safe environments, the S/Tcan be safely applied without any residual risk of metastability. B. Slow inputs
It is sometimes hoped [6] that limiting the dynamics ofthe input signal can prevent the S/T from getting metastable.The intuition is that the S/T will have accomplished its statechange before a (slow) change in the input voltage has hada chance to move the trajectory towards a metastable point.Our analysis in Section III-E has re-confirmed Marino’s resultthat one can always find a corridor around γ small enough toallow an appropriately controlled V in to still reach a metastablepoint, no matter how restricted its dynamics ( ˆ V (cid:48) in ) may be.However, as our simulation experiments showed, it takes anextremely precise control of V in to remain in a sufficientlynarrow corridor. So while limiting V (cid:48) in cannot safely rule outmetastability of the S/T, it does aid in making metastabilityless probable.
10 20 30 40 50 60 70 80time [ns]0.00.20.40.60.81.01.2 v o l t a g e [ V ] V in V out in [V]0.00.20.40.60.81.01.2 V o u t [ V ] Fig. 12: Simulation trace and phase diagram of an S/T driven to produce regular transitions, an arbitrary (here sine) waveformand to enter and resolve deep metastability
C. Handling slow monotonic inputs
We have given evidence in Section III-C that a S/T canmap arbitrarily slow monotonic inputs to steep, practically full-swing transitions. However, metastability can still occur andcause a seemingy sporadic transition during a period with anunchanging input voltage.One example of such an application is the S/T D-latchimplementation from [5], where the application requires han-dling glitches on the enable input. The input stack is a tri-state inverter that propagates the data input when the latchenable is high, and has a floating output (assumed constant)else. The resulting monotonic signal is fed into a S/T. Theauthor correctly recognizes that even in presence of glitcheson the enable input, the S/T would always correctly outputsteep transitions, albeit with an arbitrary delay.Another example is the integrator used in the synchronizerand clock to handshake circuits in [4]. Here a precharged highsignal is driven low (or vice versa) depending on the stateof an external, unstable input. It is also correctly argued thata S/T converts these monotonic inputs to steep transitions,however, the possibility that a signal driven slightly beyondthe S/T’s threshold and left at that constant voltage may causearbitrarily delayed output transitions, is not further pursued.The subsequent circuits, being delay insensitive, can toleratesuch delayed transitions, however one should be aware of thepossibility for such timing variations.VI. C
ONCLUSION
We have revisited existing results on S/T metastability, mostnotably those from Marino [1], and extended them to elaboratea general understanding of this effect and give well foundedanswers to a couple of practical questions. In this sense our keycontributions are to clearly pinpoint the differences betweenS/T metastability and that of bistable storage elements, toprovide simulation results from a realistic CMOS implemen-tation that back up theoretical results (shape of characteristic, V (cid:48) out over the phase diagram), to elaborate and validate afunction for the output delay, to give solid evidence for theappropriateness of using a S/T for metastability filtering in thevalue domain, and to elaborate on the benefits of limiting thedynamic range of V in . Limitations lie in idealizations made in the process of mod-eling, like the first-order approach for the dynamic behavior,ignoring parasitics, noise and the curved shape of the γ line.In our simulations we have found confirmation that the errorsthus introduced are acceptable and therefore the key effectsare well reflected in the model, but more details should beexplored here, especially for new technologies.R EFERENCES[1] L. R. Marino, “The Effect of Asynchronous Inputs on SequentialNetwork Reliability,”
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