The Waveform Digitiser of the Double Chooz Experiment: Performance and Quantisation Effects on PhotoMultiplier Tube Signals
Y. Abe, T. Akiri, A. Cabrera, B. Courty, J.V. Dawson, L.F.G. Gonzalez, A. Hourlier, M. Ishitsuka, H. de Kerret, D. Kryn, P. Novella, M. Obolensky, S. Perasso, A. Remoto, R. Roncin
aa r X i v : . [ phy s i c s . i n s - d e t ] J u l Preprint typeset in JINST style - HYPER VERSION
The Waveform Digitiser of the Double ChoozExperiment: Performance and Quantisation Effectson PhotoMultiplier Tube Signals
Y. Abe d , T. Akiri c , A. Cabrera a , B. Courty a , J. V. Dawson a ∗ , L. F. G. Gonzalez a , b ,A. Hourlier a , M. Ishitsuka d , H. de Kerret a , D. Kryn a , P. Novella a , M. Obolensky a ,S. Perasso a , A. Remoto a , e , R. Roncin a a Laboratoire Astroparticule et Cosmologie, 10 rue Alice Domon et Léonie Duquet, 75205 Paris,France b Universidade Estadual de Campinas-UNICAMP, Campinas, SP, Brazil c Duke University, Department of Physics, Durham, North Carolina, U.S.A d Department of Physics, Tokyo Institute of Technology, Tokyo, 152-8551, Japan e Laboratoire d’Annecy-le-Vieux de physique des particules, 9 Chemin de Bellevue, 74941Annecy-le-Vieux, FranceE-mail: [email protected] A BSTRACT :We present the waveform digitiser used in the Double Chooz experiment. We describe the hardwareand the custom-built firmware specifically developed for the experiment. The performance of thedevice is tested with regards to digitising low light level signals from photomultiplier tubes andmeasuring pulse charge. This highlights the role of quantisation effects and leads to some generalrecommendations on the design and use of waveform digitisers.K
EYWORDS : Waveform digitisers, Flash ADC, Quantisation, Digitisation, PhotoMultiplierTubes . ∗ Corresponding author. ontents
1. Introduction 12. Double Chooz Electronics 23. The Double Chooz waveform digitiser 3
4. FADC Testing 5
5. Digitisation 7
6. Simulation 127. Conclusion 12
1. Introduction
The growing usage of Waveform Digitisers in Experimental Physics applications has been madepossible by the progress of Flash ADC chip industry. It is driven by two motivations: first, insteadof recording separately some of the properties of the signal like timing, amplitude and charge,one can now use one single digitiser per channel to record the whole signal itself and derive itsproperties by software or in firmware; second, the event represented by the signal can easily bestored temporarily before the decision is taken to keep or reject it. In addition, recording signalprofiles allows to exploit Pulse Shape Discrimination techniques leading to a better understandingof background events, and gives the ability to discriminate better between physics and spurioussignals.The Double Chooz experiment measures the third neutrino mixing angle q using anti-neutrinosemitted from a nuclear power plant [1, 2]. The detector uses liquid scintillators [3] observed by390 ten-inch low background PhotoMultiplier Tubes (PMT) (Hamamatsu R7081 [4, 5, 6]) for theneutrino target, and 78 eight-inch PMTs (Hamamatsu R1408 [7]) for the muon veto. The PMTsare operated in high gain mode since the number of photons impacting on each individual PMT islow. For an event, the charge contained in each PMT waveform is measured and the total charge– 1 – igure 1. Electronics for the single channel test. observed by all PMTs is used to determine the energy deposited. The energy range of the neutrinosignal begins below 0.7 MeV for the positron interaction and extends up to 10 MeV to well containthe gamma rays resulting from neutron capture by Gadolinium. In practice, data is recorded from300 keV on the low energy side. On the high energy side, the detector response is linear to approx-imate 50 MeV which allows sampling of important backgrounds. In this energy range, each PMTsignal contains from zero to ∼
50 photoelectrons. Cosmic ray muons crossing the detector depositeven higher energies, saturating the waveform digitiser channels described in this article resultingin an overall non-linear energy response which extends up to ∼
600 MeV. The recording of thePMT waveforms is therefore an important factor in the overall energy response of the detector.In this article, we give a general description of the electronics chain involved in the digitisa-tion of the PMT signals (Section 2); then discuss the Flash ADC hardware and describe the mainfeatures of the firmware written specifically for the experiment (Section 3). Before being installedat the experimental site, a series of tests were made on each waveform digitiser card to ensure theirgood working condition [8]. The results of one such test, testing the linearity of all channels, arereported in Section 4.1. The response to PMT signals was explored with tests of a single channelmock-up of the full Double Chooz electronics chain. Signals cannot be perfectly recorded; thereare undesirable effects such as high frequency noise (Section 4.2), ADC non-linearity, and digiti-sation effects which can produce subtle biases on the measurement of pulse charge. In Section 5,we discuss the sources of bias on the measurement of pulse charge. We show that these effects canbe well reproduced by simulation, and also measured in-situ with a suitable light calibration sys-tem. We also discuss the working conditions necessary to minimise their effects. Finally Section 6shows results from a detailed simulation of a waveform digitiser.
2. Double Chooz Electronics
Figure 1 is a diagram of the single channel electronics. The PMTs are operated at a gain of 10 , thefast signal is decoupled from the PMT HV cable by a custom-built HV splitter. The signal from thePMT is amplified by the Double Chooz amplifier with a gain of ∼ ∼
35 mV. The analog RMS noise level was measuredas ∼
3. The Double Chooz waveform digitiser
Table 1.
Main characteristics of the Double Chooz waveform digitiser
Time resolution 2 nsTime precision < m A / 3.9 mVDynamic range 8-bit / 20mA / 1VDifferential Non-Linearity Typical maximum of |0.16| LSBwith limits ± ± Mi Byte ) which is divided into 1024 circular memory buffers or pages . Asophisticated control logic divides memory access periodically in two different time slots, one forwrite and one for read, only delaying the pending read or write accesses.The data stream is continuously written into one page until the arrival of a trigger signal. Whenthe trigger occurs, the page is frozen and the acquisition continues without dead time by writinginto the following empty page. The pages are unfrozen by the means of VME commands. All Mi ≡ × ∼ . × – 3 –ages are permanently accessible for reading through the VMEbus. The memory can be seen as atransparent FIFO: events enter the FIFO instantly on trigger and are removed instantly by a VMEcommand. In the mean time, they can be inspected and read randomly (transparency of the FIFO).If the read-out program was not able to unfreeze the pages fast enough, so that the FIFO becomesfull, dead-time would occur. This condition is detectable by software which would then raise awarning or an exception.The front-panel clock input is used for the synchronisation of multiple cards with the DataAcquisition clock. Multiple cards can therefore be triggered simultaneously by NIM signals. Alsoon the front-panel are 16 programmable LVDS Input/Outputs.The VME capabilities of the board which are implemented in the firmware include the fastestVME64x transfer protocol, 2eSST, at a maximum speed of 320 Mi Byte / s . Geographical Address-ing, available in VME64x, greatly facilitates the management of a large number of boards, allowingto automate board detection and address assignments. The synchronisation happens in two steps:1.
Card synchronisation:
The Trigger System distributes a 62.5 MHz (16 ns period) clock anda synchronous trigger signal. The clock is distributed as LVDS and the trigger as NIM.2.
Channel synchronisation:
An onboard PLL produces a 500 MHz (2 ns period) clocksynchronous with the external 62.5 MHz. The trigger signal is distributed to each of fourmemory-management logical units (one per two channels), which all switch pages at thesame time, on edges of the 62.5 MHz clock.The 62.5 MHz clock gives the actual pace of the board logic. Every 16 ns, eight FADC samples(eight measurements of the input current), done at 2 ns intervals, are stored in the SRAM memory.The maximum waveform length available is 4 m s (2 kiB per channel). The trigger point of eachboard is completely flexible, similar to the horizontal time-offset on an oscilloscope, a configurabledelay can be added to move the trigger point from the end of the waveform to the start, in steps of16 ns. The Double Chooz Trigger generates information about the triggering conditions and calculatesthe event number. Synchronous to the trigger, this trigger data is passed to the Waveform Digitiserboards through the 16-bit LVDS input connector present on the front-panel. This information,together with the number of clock ticks since the previous trigger and an internal trigger counter,are stored by the Waveform Digitisers and one set is kept for each page. This constitutes the event metadata ; it can be read from the VME, and used to categorise the event types and differentiatedata handling. Phase-Locked Loop – 4 – .3 Real-Time Signal Counting
As the FADC is continuously digitising it can also be setup to monitor the signal rate on eachchannel. This is achieved by setting (by software) a threshold on each channel such that whenit is crossed by a signal, a positive square pulse of firmware-determined width and amplitude isgenerated. All such signals from each channel are combined and the result is sent to the LEMOoutput on the front panel through a 16-bit DAC, with an amplitude which is set in the firmware byselecting which 4 bits out of the 16 are used. In this way the number of channels simultaneouslyfiring is coded into the amplitude of an analog signal. This information per card could be used toform the system-wide Trigger condition. This is the basis of a future enhancement to the DoubleChooz Trigger system.
4. FADC Testing
The main objective of the Double Chooz waveform digitiser is to record scintillator pulses and re-construct the contained charge. In this section we describe the behaviour of the waveform digitiser,with particular emphasis on the sources of bias on the charge measurement.FADCs convert analog waveforms to digital form, by using a linear voltage ladder with com-parators at each rung to compare input voltages to successive reference voltages. The output ofthe comparators are fed into a digital encoder which outputs binary values. The terms ’ADC code’or ’ADC count’ will be used hereafter to denote these output values 0 to 255 for the 8-bit FADC.The analog voltage to digital code (or ADC) transfer function is not perfect since it relies on realelectronic components. An assessment of the linearity of all 67 FADC cards was made and is re-ported in Section 4.1. This gives a general limit on the achievable linearity performance for a singlechannel.We note the presence of a low amplitude high frequency noise shown in Section 4.2, whichcould also affect the charge measurement.The choice of dynamic range, signal amplitude and noise level, has an impact on the overallcharge linearity achievable. This is an important issue for the 8-bit FADC. This is discussed inSection 5 and illustrated with tests with a single channel of the Double Chooz electronics, includingPMT pulsed with an LED. Measurements of the gain with different light levels, gains and noiselevels, were made using the well known photostatistics technique described in[12].
There are two values important in the definition of the linearity of an ADC; the first, is the Differ-ential Non-Linearity (DNL), and the second is the Integral Non-Linearity (INL). These parametersdetermine the voltage-to-ADC transfer function, how an analog voltage input is converted to adigital code (or ADC value).The DNL is the measure of the deviation from the ideal step size of 1 ADC count (or LeastSignificant Bit). The DNL for each ADC count can be positive (so the step size is larger than ideal)or negative (so the step is smaller than ideal). The INL is the cumulative effect of the
DNL . Itis the difference between the FADC and an ideal voltage-to-ADC transfer function. For a gooddiscussion of FADC linearity see for example [13, 14].– 5 – ypical DNL per FADC Channel (LSB) N u m be r o f E n t r i e s Typical INL per FADC Channel (LSB) N u m be r o f E n t r i e s Figure 2.
Non-Linearity measurements of all channels. On the left, the typical DNL per channel and onthe right, the typical INL per channel.
Measurements of the DNL for each code of 536 FADC channels were made using a simplehistogram method. A 1V 12 bit DAC, provided by one FADC card, was used as a controllablesource of DC voltage giving 4096 incremental steps of 244 m V, into the input of each FADCchannel. For each voltage input, a waveform of 1024 samples was recorded. The input voltagesspan a range between 2mV and 1.02V, allowing measurements of a large fraction of each FADCchannel range (from ADC code 20 to 245). The short step voltage (244 m V) resulted in the repeatedsampling of all ADC codes in the measured range. The 4096 waveforms recorded were used tomake a histogram of the sampled ADC codes. A perfect FADC would show a uniform samplingof all ADC codes, distortions to the histogram indicates a variation in the code width. In this waythe DNL per code was estimated. As the INL is the cumulation of each DNL per code, the INL percode was calculated from this data.Each FADC channel was assessed by calculating the standard deviation of the obtained DNLand INL values, as shown in Figure 2. The average of each histogram is used to estimate the typicalvalue of the FADC chip. The maximum DNL and INL values for each channel were also found toassess the extremes. In our sample of cards, we find that the typical DNL value is ∼ ∼ ± INL of 0.3 LSBwith limits at ± The input noise to the FADC for the Double Chooz electronics is low, with a measured RMS of ∼ igure 3. Averaged waveforms showing repeated patterns which correspond to the frequencies and harmon-ics of the FADC clocks. and has been observed in many experiments. The magnitude of these signals vary from channel tochannel and from card to card.
5. Digitisation
In the digitisation of an analog waveform, two discretisations occur:1. sampling: discretisation of the time2. quantisation: discretisation of the amplitudeIf certain conditions are met on both the sampling and quantisation, then the analog signal canbe perfectly reconstructed from the digitised waveform. In this case of no-distortion, measurementsof parameters such as the integrated pulse charge on the digital waveform yield consistent results asif they had been made with the original analog signal. The condition for sampling was described byShannon in 1948 and is known as the Sampling Theorem. Far less well publicised is the conditionon the quantisation which was developed by Widrow in the late 1950s [16].For the application of Double Chooz, the use of FADCs to record scintillator pulse shapes fromPMTs, the speed of the PMTs and scintillator coupled with the bandwidth limitation of the Front-End Amplifier and FADC (<200 MHz) ensures that the condition of the Sampling Theorem is met(sampling at 500 MHz). The Quantisation condition, however, requires attention to the amplitude(and form) of the signal and the analog noise level.During operation of the Double Chooz far detector, it was observed that each time the DCoffset of the FADCs was re-adjusted, not only the pedestal values changed slightly (which wasexpected), but also the determined gain of each channel appeared to change. Also an unexpectednon-linear energy response was found for each individual channel. We performed extensive studies,both experimental and by simulation, of the effects in play, and found that the dominant effect wasnot ADC non-linearity, but quantisation-induced non-linearity.– 7 –he charge contained in a signal is calculated by summing the difference between consecutivecurrent samples and the determined baseline. The photoelectron signal is extremely variable andthe noise induced by the quantisation of the pulse shape is relatively small. The baseline, however,is observed to be extremely stable such that any bias on its knowledge results in a systematic biason the charge. The correct determination of the baseline is linked to the analog noise level. Whenthe noise is large, in comparison to the ADC step (or 1 LSB), the baseline can be well determined.Conversely, when the noise level is low, the baseline position is not well known. Good quantisationof the baseline, we find, is extremely important. The following describes this effect in more detail.
Widrow derived two Quantisation Theorems (QT1 and QT2) linking the signal Probability DensityFunction and the quantisation step size q which for a Flash ADC would be the voltage (or current)difference between two successive digital values: the ADC step (1 LSB). The first theorem, QT1,describes the conditions for which there is an unique relation between the statistical descriptions ofthe input and output signals of the quantiser. The second, QT2, is a looser condition which, if met,ensures that at least the moments of the quantised variable are equal to the moments of the sum ofthe input variable and a uniformly distributed noise. For a good discussion on this subject see [17].When measuring the signal baseline with a Flash ADC, the signal is the DC offset plus theanalog noise, which, in this case, is observed to be Gaussian noise, with a standard deviation s noise .If s noise is larger than the quantisation step q then QT1 is fulfilled, and complete reconstruction ofthe waveform baseline can be made from the digitised version. If s noise > q then QT2 is fulfilled,and the estimated mean and variance of the pedestal are equivalent to the input mean and variance.If QT2 is not fulfilled, the estimated mean and variance of each waveform baseline will bebiassed. In this case, the real DC offset of the baseline will not be equal to the true offset, and themeasured noise level will also be wrong.The derivations for these biases for several distributions including the Gaussian case can befound in [18]. Here, are reproduced the equations related to the digital and analog mean andvariance of a Gaussian distribution. The bias observed is related to the analog RMS noise level( s n ) expressed as a fraction of the quantisation step q , and the true offset of the waveform e q . Theobserved digitised mean offset ( m e ( e q ) ) is: m e ( e q ) = p e − p s n sin ( p e q ) , s n ≥ . s = + s n − e − p s n (( s n + p ) cos ( p e q ) − p e − p s n sin ( p e q )) , s n ≥ . e q . The distortion on the waveform is different for a signal (such as a photoelectron orscintillation pulse) than for the baseline. Observable signals use more ADC codes to describe them,and are inherently variable. So that we can consider that the main cause of bias on the measurementof pulse charge occurs due to the waveform baseline (or pedestal). This bias is simply proportionalto the number of samples used to integrate the signal and the relative value of this bias depends on– 8 – igure 4. Example of a DAC scan of a Flash ADC channel crossing 8 consecutive ADC codes. On the left,the estimated pedestal mean is shown as a function of the input DC offset (DAC) which is proportional toDC offset voltage and on the right, the waveform RMS. the signal amplitude. If the signal amplitude is high, this bias can be small. Conversely if the signalamplitude is low, then this bias can be significant.A mismatch between the analog signal, in gain and noise level, and the quantisation step ofa waveform digitiser can lead to a significant non-linearity on the measurement of pulse charge.A tell-tale sign of this problem is the effect described in 5: a shift in the DC offset, which ismost often caused by power cycling of the electronics, results in an apparent shift in the measuredsingle photoelectron gain. The first phase of running of the Double Chooz far detector, suffers fromthis digitisation problem which is now experimentaly validated with measurements from a singlechannel test setup.
Firstly the DC offset is incremented using the 16-bit controllable DAC whose value is proportionalto DC voltage. For each DAC value the mean and RMS of the acquired waveforms are plottedin Figure 4. Oscillatory patterns are observed for the estimated pedestal mean, as expected fromEquation 5.1, and the measured RMS, which oscillates according to Equation 5.2.To test the charge performance, we considered two scenarios; the first is the standard DoubleChooz electronics and gain, with an RMS noise level of 1.2 mV and a typical mean single photo-electron amplitude of 35 mV, the second is with a factor of two higher gain and with a RMS noiselevel of 3 mV. A FADC card is triggered by the pulse generator each time the LED illuminates.The mean number of photons per shot is tuned so that all pulses are well-contained within the 8-bitrange, and no signals are saturated. For each LED setting, the DC offset (controlled by the 16-bitDAC) is shifted and 25,000 events are recorded. The DC offset is moved such that the waveformbaseline crosses 3 complete ADC codes. Data was taken for different levels of LED illumination.Figure 5 shows two example waveforms of low light-level signals taken under the two conditionsof gain and noise.The RMS noise levels were measured, and are shown in Figure 6. At high gain and high noise,a small variation of the baseline noise level is observed with DC offset, which is most likely due tothe variation of code size (DNL). For the low gain and low noise scenario, a large cyclic varation,corresponding to the transition of the ADC codes, of the RMS noise level is observed.– 9 – ime Samples (2ns) A DC C ode Low Gain and Low Noise Level
Time Samples (2ns) A DC C ode High Gain and High Noise Level
Figure 5.
Examples of waveforms for the case of low gain and low noise (left) and for higher gain andhigher noise conditions (right).
Mean Pedestal Position (ADC)206 206.5 207 207.5 208 208.5 209 R M S N o i se L eve l ( L S B ) R M S N o i se L eve l ( L S B ) Figure 6.
RMS Noise levels at different DC offsets. Left, the higher analog noise level used for the highgain runs. Right, the lower noise case, where a clear oscillatory trend is observed overlaid with the expectedtrend assuming a real RMS noise level of 0.33 LSB.
Figure 7 shows the measured gains for these two conditions. Under good running conditions,the measured gain is expected to be consistent for all values of the DAC offset. The Kuiper testwas used, as it is sensitive to cyclic variations, to search for deviations from the expectation thatthe gain is constant with a significance level of 0.05. For the high gain and high noise level case,the measured gains are consistent for all values of the DC offset and vary little with light level. Inthe low gain and low noise case, however, large cyclic variations, corresponding to the transitionsof ADC code, are observed in the measured gain, at low light levels, becoming less prominent withincreasing light levels.For the low gain and low noise case, as the signals become larger, the bias on the baselinebecomes less significant in comparison to the contained charge, and the oscillations dampen. Theshape of the oscillations, the position of minima and maxima, is complicated by the variation of thecode size (DNL) and also by the presence of correlated high frequency noise. It is clear that a strongcharge non-linearity is present whose magnitude (and sign) is dependent on the pedestal position(DC offset). In this case, the gain measured at the single photoelectron level can be significantlydifferent to that measured at higher light levels.– 10 – ean Pedestal Position (ADC)206 206.5 207 207.5 208 208.5 209 E s t i m a t e d G a i n high light level (22pe)low light level (1.8 pe) Mean Pedestal Position (ADC)206 206.5 207 207.5 208 208.5 209 E s t i m a t e d G a i n high light level (38 pe)low light level (0.75 pe) Figure 7.
Gain measurements at different DC offsets and light levels. Left, the high gain and higher analognoise level, resulting in consistent gain measurements for all light levels (filled circles and triangles withmeans of ∼
22 and 1.8 photoelectrons per LED shot respectively). Right, the lower gain and noise case,where a clear oscillatory trend is observed with a greater amplitude for lower light levels (filled circles andstars with means of ∼
38 and 0.75 photoelectrons respectively).
Mean Pedestal Position (ADC)205.5 206 206.5 207 207.5 208 A pp a r e n t G a i n Single Photoelectron20 Photoelectrons
Mean Number of Photoelectrons0 2 4 6 8 10 12 14 16 18 20 22 A pp a r e n t G a i n Pedestal position: 207.25Pedestal position: 207.75
Figure 8.
Example from simulation. Left, variation of apparent gain as a function of pedestal position for1 photoelectron (filled squares) and 20 photoelectrons (points). Right, the variation of apparent gain withincreasing number of photoelectrons. Here, shown for two values of pedestal position, 207.25 (filled circles)and 207.75 (filled squares). – 11 – . Simulation
The described effects can be well reproduced by simulation. Waveforms are generated, first inan analog sense (in volts) and then ’digitised’ using a voltage-to-ADC transfer function whichrepresents a typical FADC. The FADC behaviour can be chosen to be perfectly linear or imperfectie using measured DNL values or with randomly chosen code widths (whilst obeying the typicalvalues of maximum INL and DNL of the FADC chip as measured in Section 4.1). The analog partof the simulation was tuned to represent the behaviour of the PMT and Front-End Amplifier, withtypical RMS noise levels. Also included was the high frequency clock noise, using the observedpatterns shown in Section 4.2. Single photoelectrons were generated such that the mean gainas observed by the FADC is ∼
36 LSB x 2ns. The single photoelectron charge distribution wasassumed to be Gaussian with sigma of 35%. The temporal form of the single photoelectron isgiven by a Landau distibution, with parameters tuned to match the actual time profile of a singlephotoelectron. The LED pulse profile was generated assuming a square pulse.Figure 8 shows an example of the simulation results. Here, a perfectly linear FADC wassimulated with an analog noise level of 1 mV and the high frequency noise amplitude of 0.4 mV(approximately 0.1 LSB). A clear oscillation in gain is found for low light levels which diminishesin strength for higher light levels. Fixing the waveform pedestal position and plotting the measuredgain as a function of increasing number of photoelectrons shows clearly the charge non-linearity,shown here for two extreme pedestal positions. Depending on the pedestal position, the measuredgain can either increase or decrease with increasing light level. Increasing the RMS noise level to2 mV, as predicted by QT 2, reduces the charge biases to insignificant levels.
7. Conclusion
The waveform digitiser of the Double Chooz experiment was presented. In all 66 cards dividedinto 5 VME crates are required to form the data acquisition system of the experiment. A dedicatedfirmware allows the synchronous running of these cards, operating with no deadtime at triggerrates of ∼
150 events/s. This firmware also has a flexible readout capability, allowing on-the-flydecision making on the read-out duration of the waveforms. These functions are ideal for rareevent searches, such as neutrino reactor experiments, where the rate of the signals of interest aredominated by the rate of background events.The general linearity of the card was assessed through measurements of the Differential Non-Linearity and Integral Non-Linearity of 67 eight-channel FADC cards. These measurements aidedin a more specific study of the systematic biases on the determination of the pulse charge fromsignals from a PMT tube.The use of an 8-bit FADC operated in a high dynamic range was described, where signals varyper channel from 1 to ∼
50 photoelectrons. Sources of systematic bias were shown for the casewhere the signal amplification and analog noise level is low. In this regime, biases from clock-correlated noise, quantisation and intrinsic non-linearity of the FADC chip (DNL and INL) areimportant. These effects were found to be well reproducable by simulation. Problems, that canoccur if the analog signal and noise level are not correctly matched to the digitisation step, wereexplored. We show, the gain and noise level required to adequately eliminate these problems.– 12 –t is interesting to note that the Sampling Condition (from the Sampling Theorem) is generallytaken into account into the design of a waveform digitiser, but the Quantisation condition is not. Itis an error to consider that noise is always a bad thing. Noise is a dithering agent, and, as such, isnecessary. We recommend that manufacturers provide a means to enable/disable, or, even better,adjust a source of Gaussian noise to add to the analog input signal, so as to give the possibility toreach a baseline RMS equal to 0.5 LSB.
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