Vertical Field-Effect Transistor Based on Wavefunction Extension
Adam Sciambi, Matthew Pelliccione, Michael P. Lilly, Seth R. Bank, Arthur C. Gossard, Loren N. Pfeiffer, Ken W. West, David Goldhaber-Gordon
aa r X i v : . [ c ond - m a t . m e s - h a ll ] J u l Vertical Field-Effect Transistor Based on Wavefunction Extension
A. Sciambi,
1, 2
M. Pelliccione,
1, 2
M. P. Lilly, S. R. Bank,
4, 5
A. C.Gossard, L. N. Pfeiffer, K. W. West, and D. Goldhaber-Gordon
7, 2 Department of Applied Physics, Stanford University, Stanford CA 94305-4045 USA SIMES, SLAC National Accelerator Laboratory,2575 Sand Hill Road, Menlo Park, CA 94025 USA Center for Integrated Nanotechnologies, Sandia National Laboratories, Albuquerque, New Mexico 87185, USA Materials Department, University of California Santa Barbara, Santa Barbara CA 93106 USA Electrical and Computer Engineering Department,University of Texas at Austin, Austin TX 78758 USA Department of Electrical Engineering, Princeton University, Princeton NJ 08544 USA Department of Physics, Stanford University, Stanford CA 94305-4045 USA (Dated: August 29, 2018)We demonstrate a mechanism for a dual layer, vertical field-effect transistor, in which nearly-depleting one layer will extend its wavefunction to overlap the other layer and increase tunnel current.We characterize this effect in a specially designed GaAs/AlGaAs device, observing a tunnel currentincrease of two orders of magnitude at cryogenic temperatures, and we suggest extrapolations of thedesign to other material systems such as graphene.
Quantum transistors, those that rely on quantum me-chanical transport processes for operation, have becomean important research direction as conventional transis-tors are hindered by the emergence of those same ef-fects at the nanoscale. In this vein, we present herea novel mechanism for a vertical field-effect transistor,wherein the adjustable subband energy of a planar quan-tum well modifies the vertical extent and overlap of itsbound wavefunction with another parallel well. Unlikepast quantum transistors that utilize tunnel resonances ofaligned subbands or single electron levels in quantumdots, this simple design is not sensitive to lateral dimen-sions and should be operable down to the few-nanometerscale in suitable materials. We call the resulting devicethe Wavefunction Extension Transistor (WET).Within a quantum well containing a single subband,the out-of-plane momentum and characteristic lengthscale for barrier penetration for bound electrons is solelydetermined by the height of the barrier above the bot-tom of the subband, together with the effective mass, aproperty of the quantum well material. In a WET, thisbarrier normally inhibits tunneling, but its height can bereduced by electrostatically raising the well containingthe subband (Fig 1a). The rate of exponential decay ofthe subband wavefunction into the barrier scales roughlyas the square root of the effective barrier height, so re-ducing the height nearly to zero causes a subband wave-function to greatly extend toward the opposing well (Fig1b). Such spreading leads to an increase in wavefunctionoverlap and tunneling. Substantial tuning of wavefunc-tion extension and overlap is enabled by (1) having awide potential barrier separating the two wells to max-imize the effect of wavefunction decay, and (2) havingthe barrier height as low as possible to maximize currentwhile ensuring energy levels in the two wells can be sep-arately manipulated. This need for a low and wide bar-rier means wavefunction extension has not been observedin more conventional bilayer quantum well systems with high, narrow barriers, strongly-coupled wells, or highinterlayer biases. Modulating wavefunction overlap hasbeen proposed before for a field-effect tunnel transistor, but in the context of laterally shaping wavefunctions us-ing multiple side gates.In this paper, we simulate and experimentally char-acterize a proof-of-principle transistor designed accord- B a n d E n e r g y ( m e V ) -50 E n e r g y ( m e V ) Ψ ( z ) ( a r b u n i t s ) Potential Profile Bound States (a) (b) -9 meV e-z/(8nm)e-z/(24nm) (c) E = -9 meV E = -1 meV E = -9 meV E = -1 meV −40 0 40−20−10010 z (nm) −40 0 400 z (nm) BarrierWell Well 2nd Well -1 meV G a A s ( D r a i n ) G a A s A l G a A s A l G a A s G a A s + + + + + + + + + + + + + + G a A s ( S o u r c e ) A l G a A s ( D r a i n ) ( S o u r c e ) ( D r a i n ) ( S o u r c e ) ( D r a i n ) ( S o u r c e )( S o u r c e ) ( D r a i n )( D r a i n )( D r a i n ) ( S o u r c e ) ( D r a i n ) ( S o u r c e )( S o u r c e ) l o w % A l G a A s A l G a A s Heterostructure Layering and Band Structure n m n m n m n m n m n m n m n m n m S o u r c e G a t e D r a i n G a t e FIG. 1. (a) Potential profile of a shallow barrier next to arectangular well that is raised so the energy E of its boundsubband edge goes from -9 meV to -1 meV. (b) Simulatedwavefunctions corresponding to the two subband energies,with the raised subband having a greatly extended wavefunc-tion. (c) WET composition, consisting of a GaAs/AlGaAsheterostructure with gates and dielectric on either side. Aself-consistent simulation of the conduction band edge for thestructure is shown below, with the source gate varying thesubband edge of the source quantum well from -9 meV to -1meV and extending its associated wavefunction. ing to this scheme: we measure at 4.2K the tunnelingbetween source and drain layers epitaxially grown in aGaAs/AlGaAs heterostructure (Fig 1c, top), as a func-tion of voltages on top and back gates. In this type ofstructure, simply bringing a layer near depletion usingsurface gates should dramatically increase wavefunctionoverlap (Fig 1c, bottom) and the related vertical tun-nel conductance, as indeed we observe empirically. Thisputs the WET into a very small subset of transistors where the conductance is tuned using a gate located out-side the channel region, with the source or drain inter-vening between gate and channel. After characterizingthe GaAs/AlGaAs device, we conclude by proposing thata WET operating at room temperature with improvedswitching characteristics could be constructed based ontwo parallel layers of graphene. We note here that boththe GaAs device and the proposed graphene device areorders of magnitude from the current densities and on-off ratios of commercial transistors. That said, we be-lieve that this novel mechanism of current-modulationmight be useful as new materials and fabrication tech-niques arise.In order to optimize the tunable tunneling inour GaAs/AlGaAs device, we use self-consistent one-dimensional Schr¨odinger-Poisson solvers to guide ourdesign of a pair of GaAs/AlGaAs quantum wells sepa-rated by a wide, low-energy barrier. We estimate tunnelrates using Bardeen’s formalism, which calculates theoverlap of wavefunctions constrained to opposing sides ofthe barrier. This yields a tunneling matrix element be-tween wells of equal subband energy that scales roughlyas T ( E ) ∝ p | E | e − w √ m | E | / ¯ h , where E is the (nega-tive) energy of the subband edge relative to the barrier, w is the width of the wide barrier, and m is the effectivemass of an electron in the barrier. Following optimization, we focus on the structureshown in Fig. 1c, which we have labeled H1 and use forall measurements unless otherwise noted. The structurecontains a pair of two-dimensional (2D) electron layerseach residing in a 20 nm-wide GaAs well, and separatedby a 140 nm-wide, Al . Ga . As barrier. The bilayersystem is sandwiched between 80 nm Al . Ga . As spac-ers that are delta-doped near their midpoint, and thenbetween 22 nm GaAs caps. After growth in an MBEsystem, this heterostructure was found to have sourceand drain layer densities of 3.1 and 2.9 × cm − withmobilities of 3 and 1 × cm /Vs, respectively, all at4.2K. The densities are within 10% of their simulatedvalues.The 2.0% Al barrier, measured precisely duringgrowth with reflection high-energy electron diffraction(RHEED), was found empirically to be the ideal balancebetween large barrier modulation and large tunnel cur-rent. For a 1.0% barrier, we observe that the two wellsare not decoupled and for a 3.0% barrier, the minutetunneling is difficult to measure. Determining this opti-mal percentage from first principles is difficult since thebarrier position relative to the Fermi energy can vary by more than 10 meV depending on the exact well shape.Our simulation predicts that the 2.0% barrier is too high(7 meV above E F ) to measure the strong gate modu-lation of tunnel conductance described later. With thisdisparity in mind, we have adjusted the Al concentrationto 0.5% in simulation, and we use this value to demon-strate wavefunction extension in Fig 1c. This shallowerbarrier is predicted to be around 1 meV above E F .To determine tunneling between layers, we employfront and back depletion gates (DGs, Fig 2a) to limitaccess of the sample contacts to only one layer each.In this way, modulation of tunneling by the source anddrain gates can be measured by simply applying a biasbetween the contacts. Backside lithography is accom-plished by first fabricating the front side of a samplechip with mesas, contacts, alumina gate dielectric, andgates, and then epoxying that chip face down to a secondGaAs substrate. The original substrate is mechanicallythinned to 30 µ m, and then chemically etched to 400nm using selective removal of etch-stop layers grown intoheterostructure. After etching, only the mesa remainsof the original substrate, with bare epoxy supporting it aswell as features off the mesa like the frontside gates andsubsequently-added backside gates (Fig 2b). With theflipped sample in mind, we refer to the original backsidequantum well as the source and the original frontside wellas the drain. The source and drain gates areas are 200 µ m , allowing accurate measurements of tunnel modula-tion between source and drain by excluding backgroundtunneling or tunneling induced by fringe fields.The measurement itself is performed with the applica-tion of a 100 µ V AC excitation driven at 152 Hz betweenthe source and drain layers while a lock-in measures thedifferential tunneling conductance. We confirmed that
Drain LayerSource Layer Tunneling
Source Gate DGDrain Gate
400 nm DG (a) (b) SourceDG DrainDGSource &Drain GatesEpoxy on SubstrateSource Contact50 μm EpoxyDrain ContactTunnelRegion C o n t a c t C o n t a c t C o n t a c t Mesa GaAs substrate
FIG. 2. (a) Schematic of WET device (not to scale), with de-pletion gates (DG) limiting access of the contacts to the tun-neling region. (b) Photograph of the finished sample with theGaAs mesa, outlined in purple, supported by epoxy. Hook-shaped protrusions in the mesa are visible where gates over-lap, included to ensure continuity during gate deposition overthe mesa step. the bias between the two layers was set by this AC exci-tation: the gate dielectric ensures that the measured ACcurrent was always many orders of magnitude larger thanany DC gate leakage current. Additionally, we find thatinterlayer biasing up to tens of mV minimally impacts thedensities of the layers, by less than 5 × cm − /mV asdetermined from Shubnikov-de Haas oscillations.As expected, tunneling measurements as a functionof source and drain gate voltages reveal a pair of con-ductance ridges (Fig 3a, dotted lines) at 4.2K associatedwith near-depletion in the respective layers. Approachingthese ridges from the high-density side, the tunnel con-ductance increase confirms the predicted wavefunctionextension. These ridges differ from the resonances oftenseen in tunneling between low-dimensional systems wheretheir energy-momentum dispersions coincide. Such reso-nances are absent here (Fig 3a, gray line where densitiesare matched), possibly due to elastic scattering in theinterlayer that creates momentum transfer.For comparison, we show a density-matched tunnelingresonance from a similar structure (H2) with a narrower70 nm barrier (Fig 3b – this structure was thinned only to10 µ m and so required proportionally larger source gatevoltages.) In this heterostructure, the near-depletionridges are also apparent, though mostly obscured bydensity-matched resonant tunneling (gray line). In aregime lacking interlayer scattering, the WET could op-erate without impact from energy-momentum constraintsif the two layers were set to equal densities and then de-pleted simultaneously. On Fig 2b, this represents movingfrom the upper right corner along the gray line towardsthe tunnel maximum near the plot center. Alternatively,the constraints could be lifted by tunneling from a regioncomparable in size to the Fermi wavelength ( λ F ), wherea large lateral momentum spread yields access to anymomentum state in the other layer. Lifting of momen-tum constraints in tunneling is why the vertical, tunnel-resonant transistor mentioned earlier fails to operate be-low a minimum device size.On the main heterostructure H1, the greatest relative tunnel increase occurs when tuning either gate throughthe tunnel maximum at ( V sg , V dg ) = (-0.57V, -0.57V).The corresponding source and drain gate sweeps, repre-sented by the dotted lines in Fig 3a, show tunneling growby a factor of 16 and 76, respectively (Fig 3c). Althoughthe sweeps are not identical, their lineshapes are simi-lar as expected from the symmetry in the heterostruc-ture. Any quantitative difference likely comes from themechanical and chemical processing that the source layersees while the drain layer is protected face-down in epoxy.The greater induced tunneling from the drain gate rep-resents a change in effective conductivity from 9 nS to600 nS/ µ m . The actual tunneling increase is probablylarger than the measured conductance enhancement; asa layer is depleted, the growing tunnel conductance iseventually overcome by a low series sheet conductivity.This explains the apparent turnover of gate-modulatedtunneling in Fig 3c. By independently measuring sheet (c) -0.6 -0.4 -0.2 0110100 d I / d V C o n d u c t . ( μ S ) Gate Voltages V dg , V sg (V) (a) H1 Tunnel Conductance -0.6 -0.4 -0.2 0-0.6-0.4-0.20
Source Gate V sg (V) D r a i n G a t e V d g ( V ) dI/dV (μS) (b) H2 Tunnel Conductance -40 0 40 80-0.3-0.2-0.100.1
Source Gate V sg (V) D r a i n G a t e V d g ( V ) dI/dV (μS) ×76×16(V sg )(V dg ) H1 Tunnel Conductance
FIG. 3. (a) Tunneling conductance as a function of source anddrain gate voltages in the main heterostructure H1. Density-matched bilayer resonances (around gray line) are absent,but barrier-modulated tunnel increases along dotted lines arestrong. (b) A different heterostructure H2 with resonant tun-neling is shown for comparison. The axes of (a) and (b) arechosen so that both layers are depleted at the lower left cor-ner, with a star added for reference where each layer has acarrier density of 2 × cm − . (c) Cuts along dotted linesin (a) reveal the large tunnel increases. All data were takenat 4.2K. resistance, we can estimate that the true tunnel conduc-tance increases by at least another order of magnitude.The tunnel signal will not be obscured in this way ifone combines smaller-area gates and higher-mobility het-erostructures.The robustness of wavefunction extension is demon-strated by its persistence even when a substantial bias isapplied between layers. Here, we choose to focus on theeffect of the drain gate rather than the source gate dueto the drain gate’s greater influence on tunneling. Wemeasure the increase in tunneling from a nearly-depleteddrain layer compared to an ungated drain layer, as a func-tion of source-drain bias. For a positive source-drain bias,the relative gate-induced increase in current is unchangedfor biases up to several mV, and some modulation is visi-ble up to many tens of mV (Fig 4a). Low negative biaseswork similarly (Fig 4b), though wavefunction extensionvanishes earlier at high negative bias (10 mV). This isprobably because electrons begin to tunnel into the ex-cited states of the drain regardless of its lowest subbandenergy (schematic: Fig 4b, inset). For positive bias, thedrain subband is always the highest accessible level, so itaffects tunneling for higher biases (Fig 4a, inset).From Fig 4a, we can also calculate the transconduc-tance, which peaks at 50 nS/ µ m at V sd = 40mV at4.2K. Here, the units of transconductance are per arearather than per length, because of the unusual geome-try of the transistor. For comparison, MOSFETs can U n g a t e d U n g a t e d N e a r l y - d e p l e t e d N e a r l y - d e p l e t e d (b)(a) -0.1 -1 -10 -10010 -4 -2 T unne l C u rr en t ( μ A ) T unne l C u rr en t ( μ A ) sd (mV) Source-Drain Bias V sd (mV) ds -4 -2 s d FIG. 4. Current modulation by the drain gate as a functionof (a) positive and (b) negative source-drain bias. The insetsdepict a possible explanation for the difference in modulationfor large positive and negative biases. achieve transconductances of 11-30 mS/ µ m with drivesof around 70-200 mV at room temperature. To oper-ate a WET at room temperature with higher transcon-ductances, the effective barrier height needs to be mademuch larger while keeping the absolute barrier low. Thiscan be accomplished by increasing E F of the source anddrain layers. GaAs heterostructures are limited to Fermienergies of tens of meV. In contrast, graphene, a singleatomic layer of graphitic carbon, has been gated to car-rier densities up to 3 × cm − , which correspondsto E F = 0.9 eV. This is 90 times larger than in ourGaAs/AlGaAs heterostructure, with the additional ad-vantage that graphene can be serially deposited andetched so that individual layers can be contacted with-out depletion gates. Furthermore, graphene is extremelythin, allowing for larger capacitances and transconduc-tances with more closely-spaced gates.Although graphene field-effect transistors have alreadybeen reported with large on-off current ratios at roomtemperature, such devices rely on nanoconstrictionsto open bandgaps and have been predicted to havelow yields for the near future because of difficult de-vice fabrication. A graphene WET would not needprecise lateral definition, and would instead depend onits more easily controlled vertical layer structure (Fig5a). We have modeled (but not fabricated) a grapheneWET containing two graphene sheets, doped to an easily-achievable E F = 0 . × cm − )and separated by a slightly n -doped silicon barrier. Thebarrier height is chosen so that there exists no excitedinterlayer subband below ten times room temperaturethermal energy (250 meV). The graphene double layer isinsulated on each side by a thin layer of high-k dielec-tric (HfO ), and equal voltage is applied to top and backgates to match layer densities and energy-momentum dis-persions. (Such a device should also have a high negativedifferential resistance should the top and bottom gatesbe differently biased.)For a 5 nm-wide barrier and 2 nm top and back gatedielectrics, the layer wavefunctions significantly extendwhen the subbands are raised (Fig 5b). To estimate howgating might accomplish this, the density of states (DOS)of graphene must be considered. Unlike the constant DOS of the 2D GaAs heterostructure, graphene’s DOSnominally drops to zero as it is depleted due to its lineardispersion. This introduces problems of quantum capac-itance near zero DOS, which weakens the effect ofa gate on E F as compared to that expected from theconventional geometric capacitance (Fig 5c). (This issuecould potentially be alleviated by using bilayer graphene,which has a constant DOS near the K point.) Despite theshrinking DOSs, the tunnel current still increases withnegative gate bias, almost to depletion, due to the expo-nentially increasing tunnel coupling (Fig 5d).We have chosen the device parameters such that tun-nel modulation is at the room-temperature thermal limitof 60 mV/decade over five decades. For a source-drainbias of 100 mV, where we have offset tunnel gate voltagesto account for the bias-induced dispersion mismatch, wefind that we should be able to obtain transconductanceson the order of 10 µ S/ µ m over a 0.3V gate range. (Noteagain that transconductance scales with channel arearather than channel width, due to the geometry of thetransistor.) If the tunnel barrier is made thicker (6 nmvs. 5 nm) the subthreshold slope can beat the thermallimit, provided phonon-assisted processes do not domi-nate, at the cost of somewhat reduced maximum conduc-tance. We neglect the effect of spatial inhomogeneities indensity, because the fluctuations are on the order ofthe thermal energy and because the disorder that givesrise to these fluctuations continues to be reduced withimprovements in fabrication technology. As mentioned previously, the original GaAs/AlGaAsWET is not practical for room-temperature operation,but does have an attractive potential application at (d) Zero-bias Conductance m V / d e c -0.3 -0.2 −0.1 010 -10 -8 -6 -4 -2 Gate Voltage V g (V) C o n d u c t a n c e ( S / μ m ) d = n m d = n m Si Substraten- Si (5 nm) HfO (2 nm) (a) Graphene WET HfO (2 nm) Gate Gate (c) Gate Coupling S o u r c e D r a i n Graphene Band(b) E = - 0.40 eV E = - 0.03 eV z (nm) G e o m . G e o m . + Q u a n t . -0.3 -0.2 -0.1 000.20.4 F e r m i E n e r g y ( e V ) E n e r g y ( e V ) Gate Voltage V g (V) −4 −2 0 2 4−3036 FIG. 5. (a) Schematic of a graphene WET (two graphenelayers marked by dotted red lines) and (b) plot of the conduc-tion band with simultaneously varied subband wavefunctions(shaded). (c) Quantum capacitance, due to a discrete densityof states, weakens the effect of the gate, but the device still isable to match 60 mV/decade over several decades (d). low temperature. Using a scanned gate rather thana lithographically-patterned gate on a WET structurewould allow local tunneling into complex, spatially-organized electron phases that sit at buried interfacesand are otherwise locally inaccessible. In this context,we have recently found empirically that the source anddrain layers almost completely screen the effect of theirrespective gates on the opposing 2D layers, that non-equilibrium spectroscopy can be performed, and thattunneling spatial resolution should be on order of λ F . In summary, we have used a bilayer GaAs/AlGaAs het-erostructure to demonstrate the soundness of the simpleWET principle. The behavior of the tunnel modulationas a function of gate voltage and bias is understood qual-itatively, and should permit the creation of WETs withuseful specifications, using other materials. Furthermore,the GaAs/AlGaAs heterostructure as grown could serveas a tool for probing interesting physics. Again, althoughthe WET design is not yet fully competitive with conven- tional transistors, wavefunction extension combined withnew materials and fabrication techniques could lead to anew class of quantum transistors based on vertical trans-port in heterostructures.We thank C.X. Liu for theoretical discussions. Thiswork is supported by DOE-BES, DMS&E at SLAC (DE-AC02-76SF00515), with the original concept developedunder the Center for Probing the Nanoscale (NSF NSECGrant No. 0425897) and a Mel Schwartz Fellowship fromthe Stanford Physics Department. This work was per-formed, in part, at the Center for Integrated Nanotech-nologies, a DOE-BES user facility at Sandia NationalLabs (DE-AC04-94AL85000). The work at Princetonwas partially funded by the Gordon and Betty MooreFoundation as well as the National Science FoundationMRSEC Program through the Princeton Center for Com-plex Materials (DMR-0819860). A.S. acknowledges sup-port from NSF, and M.P. from the Hertz Foundation,NSF, and Stanford. D.G.-G. recognizes support from theDavid and Lucile Packard Foundation V. R. Kolagunta, D. B. Janes, G. L. Chen, K. J. Webb,M. R. Melloch, and C. Youtsey, Appl. Phys. Lett. , 374(1996). J. B. Khurgin and D. Yang, J. of Appl. Phys. , 3218(1998). J. A. Simmons, M. A. Blount, J. S. Moon, S. K. Lyo, W.E. Baca, J. R. Wendt, J. L. Reno, and M. J. Hafich, J. ofAppl. Phys. , 5626 (1998). M. A. Kastner, Rev. Mod. Phys. , 849 (1992). J. P. Eisenstein, L. N. Pfeiffer, and K. W. West, Phys. Rev.Lett. , 3804 (1992). H.C. Manoharan, Y. W. Suen, M. B. Santos, and M.Shayegan, Phys. Rev. Lett. , 1813 (1996). M. Heiblum and M. V. Fischetti, IBM J. Res. and Develop. , 530 (1990). R. J. Baker,
CMOS Circuit Design, Layout, and Simula-tion , 3rd ed. (Wiley-IEEE Press, New York, NY, 2010). Simulations used code by G. L. Snider, Univeristy of NotreDame, and by C.X. Liu, Tsinghua University. J. Bardeen, Phys. Rev. Lett. , 57 (1961). R. Clerc, A. Spinelli, G. Ghibaudo, and G. Pananakakis,J. of Appl. Phys. , 1400 (2002). Heterostructure H1 and H2 were grown by L.N.P. andK.W.W. J. P. Eisenstein, L. N. Pfeiffer, and K. W. West, Appl.Phys. Lett. , 2324 (1990). M. V. Weckwerth, J. A. Simmons, N. E. Harff, M. E. Sher-win, M. A. Blount, W. E. Baca, and H. C. Chui, Supper- lattices Microstruct. , 561 (1996). K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y.Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A. Firsov.Science , 666 (2004). Density up to 4 × cm − has been achieved in grapheneusing electrolytic gates, though this approach would not beviable for practical devices. D. K. Efetov, P. Kim, Phys.Rev. Lett , 256805 (2010). S. Kim, I. Jo, J. Nah, Z. Yao, S. K. Banerjee, and E. Tutuc.arXiv:1010.2113v1 (2010). M. Y. Han, B. ¨Ozyilmaz, Y. Zhang, and P. Kim, Phys.Rev. Lett. , 206805 (2007). X. Li, X. Wang, L. Zhang, S. Lee, and H. Dai, Science ,1229 (2008). A. K. Geim, Science L. A. Ponomarenko, R. Yang, R.V. Gorbachev, P. Blake,A. S. Mayorov, K. S. Novoselov, M. I. Katsnelson, and A.K. Geim, Phys. Rev. Lett. , 136801 (2010). A. Hazeghi, J. A. Sulpizio, G. Diankov, D. Goldhaber-Gordon, and H.S. Philip Wong, Rev. Sci. Instrum. ,053904 (2011). J. Martin, N. Akerman, G. Ulbricht, T. Lohmann, J. H.Smetr, K. von Klitzing, and A. Yacoby, Nature Phys. ,144 (2008). Y. Zhang, V. W. Brar, C. Girit, A. Zettl, and M. F. Crom-mie, Nature Phys. , 722 (2009). E. Rossi and S. Das Sarma, Phys. Rev. Lett. , 166803(2008). C. R. Dean, A. F. Young, I. Meric, C. Lee, L. Wang, S. Sor-genfrei, K. Watanabe, T. Taniguchi, P. Kim, K. L. Shepardand J. Hone, Nature Nano., , 722 (2010). A. Sciambi, M. Pelliccione, S. R. Bank, A. C. Gossard, D.Goldhaber-Gordon, Appl. Phys. Lett.97