Wideband Full-Duplex Wireless via Frequency-Domain Equalization: Design and Experimentation
Tingjun Chen, Mahmood Baraani Dastjerdi, Jin Zhou, Harish Krishnaswamy, Gil Zussman
TTo appear in Proc. ACM MobiCom’19 1
Wideband Full-Duplex Wireless via Frequency-Domain Equalization: Design and Experimentation
Tingjun Chen † , Mahmood Baraani Dastjerdi † , Jin Zhou ‡ , Harish Krishnaswamy † , Gil Zussman † † Electrical Engineering, Columbia University ‡ Electrical and Computer Engineering, University of Illinois at Urbana-Champaign{tingjun@ee, b.mahmood, harish@ee, gil@ee}.columbia.edu, [email protected]
ABSTRACT
Full-duplex (FD) wireless can significantly enhance spec-trum efficiency but requires tremendous amount of self-interference (SI) cancellation. Recent advances in the RFICcommunity enabled wideband RF SI cancellation (SIC) in integrated circuits (ICs) via frequency-domain equalization(FDE), where RF filters channelize the SI signal path. Un-like other FD implementations, that mostly rely on delaylines, FDE-based cancellers can be realized in small-form-factor devices . However, the fundamental limits and higherlayer challenges associated with these cancellers were notexplored yet. Therefore, and in order to support the integra-tion with a software-defined radio (SDR) and to facilitateexperimentation in a testbed with several nodes, we designand implement an FDE-based RF canceller on a printed cir-cuit board (PCB). We derive and experimentally validatethe PCB canceller model and present a canceller configu-ration scheme based on an optimization problem. We thenextensively evaluate the performance of the FDE-based FDradio in the SDR testbed. Experiments show that it achieves95 dB overall SIC (52 dB from RF SIC) across 20 MHz band-width, and an average link-level FD gain of 1 . × . We alsoconduct experiments in: (i) uplink-downlink networks withinter-user interference, and (ii) heterogeneous networks withhalf-duplex and FD users. The experimental FD gains in thetwo types of networks confirm previous analytical results.They depend on the users’ SNR values and the number ofFD users, and are 1.14 × –1.25 × and 1.25 × –1.73 × , respectively.Finally, we numerically evaluate and compare the RFIC andPCB implementations and study various design tradeoffs. KEYWORDS
Full-duplex wireless, frequency-domain equalization, wide-band self-interference cancellation, software-defined radios
Full-duplex (FD) wireless – simultaneous transmission andreception on the same frequency channel – can significantlyimprove spectrum efficiency at the physical (PHY) layer andprovide many other benefits at the higher layers [35, 41]. Themain challenge associated with FD is the extremely strong (a)
Antenna CirculatorFDE-based PCB Canceller NI USRP 2942Sub-20 Controller (b)
FD BS HD/FD User 1HD/FD User 2 (c)Figure 1: (a) The frequency-domain equalization- (FDE-) based wide-band RF canceller implemented using discrete components on aPCB, (b) the implemented FDE-based FD radio, and (c) the experi-mental testbed consisting of an FD base station (BS) and 2 users thatcan operate in either half-duplex (HD) or FD mode. self-interference (SI) signal that needs to be suppressed, re-quiring 90–110 dB of SI cancellation (SIC).Recent work leveraging off-the-shelf components andsoftware-defined radios (SDRs) has established the feasibil-ity of FD wireless through SI suppression at the antennainterface, and SIC in analog/RF and digital domains [12,20, 25, 32, 34]. However, RF cancellers achieving widebandSIC (e.g., [12, 34]) rely on transmission-line delays, whichcannot be realized in small-form-factor nodes and/or inte-grated circuits (ICs) due to the required length for generatingnanosecond-scale time delays and the lossy nature of thesilicon substrate. A compact IC-based design is necessary for supportingFD in hand-held devices (e.g., handsets and tablets) [35, 44,48, 49]. Specifically, recent advances in the RFIC communityallowed achieving wideband RF SIC in IC implementationsbased on the technique of frequency-domain equalization(FDE) [48]. In contrast to the delay line-based approaches(which are essentially performing time-domain equalization),the FDE-based RF canceller utilizes tunable, reconfigurable, For instance, obtaining a nanosecond delay in silicon typically requires a15 cm-long delay line. a r X i v : . [ ee ss . SP ] D ec o appear in Proc. ACM MobiCom’19 2high quality factor 2 nd -order bandpass filters (BPFs) withamplitude and phase controls to emulate the frequency-selective antenna interface. In general, tunable, high qualityfactor BPFs are perhaps as hard to implement on an IC asnanosecond-scale delay lines. However, N -path filters repre-sent an exciting advance that has enabled their implementa-tion in nanoscale CMOS over the past few years [27, 40].While major advances have been made at the IC level,existing work (e.g., [48]) has several limitations: (i) the funda-mental limits of the achievable RF SIC based on the techniqueof FDE have not been fully understood, (ii) configurationschemes for this new type of RF canceller need to be devel-oped in order to achieve optimized and adaptive RF SIC inreal-world environments, and (iii) the system-level perfor-mance of such IC-based FD radios has not been evaluated indifferent network settings. Therefore, in this paper we focuson FDE-based RF cancellers.Since interfacing an RFIC canceller to an SDR presentsnumerous technical challenges, we design and implementan FDE-based RF canceller using discrete components on aprinted circuit board (PCB). This canceller appears in Fig. 1(a)(we refer to it as the PCB canceller ) and it emulates its RFICcounterpart. This FDE-based PCB canceller facilitates theevaluation of the canceller configuration scheme and theexperimentation using SDRs in a network with multiple FDnodes. Moreover, the PCB canceller is more robust and stablethan its IC counterpart and as such can be integrated in the fu-ture in the open-access ORBIT [1] and COSMOS [3] testbedsto allow the community to experiment with wideband com-pact FD wireless. For example, our previous narrowband
RFcanceller emulating its RFIC counterpart [47] is implementedon a PCB and is integrated in the ORBIT testbed [2, 17].We present a realistic model of the PCB canceller. We thenpresent its configuration scheme based on an optimizationproblem, which allows efficient adaption of the canceller toenvironmental changes. The PCB canceller model is experi-mentally validated and is shown to have high accuracy. Weimplement an FDE-based FD radio by integrating the PCBcanceller with an NI USRP SDR, as depicted in Fig. 1(b). ThisFD radio achieves 95 dB overall SIC across 20 MHz real-timebandwidth, enabling an FD link budget of 10 dBm averageTX power level and −
85 dBm RX noise floor. In particular,52 dB RF SIC is achieved, from which 20 dB is obtained fromthe antenna interface isolation.We also evaluate the performance and robustness of theFDE-based FD radio at the link-level in terms of packet re-ception ratio (PRR) and FD throughput gain, in both line-of-sight (LOS) and non-line-of-sight (NLOS) settings. The The PCB canceller design is available at [4]. A preliminary version of the system was demonstrated in [19]. results show that the FDE-based FD radio achieves an aver-age FD link throughput gain of 1.85 × –1.91 × . Moreover, thelink SNR difference when the radio operates in half-duplex(HD) and FD modes is less than 1 dB.Using our testbed (see Fig. 1(c)), we extensively evaluatethe network-level FD gain and confirm analytical results intwo types of networks: (i) UL-DL networks consisting of oneFD base station (BS) and two half-duplex (HD) users withinter-user interference (IUI), and (ii) heterogeneous HD-FDnetworks consisting of one FD BS and co-existing HD andFD users. For UL-DL networks, we show experimentally thatthe throughput gain is between 1.14 × –1.25 × compared to1.22 × –1.3 × predicted by analysis. We discuss the relationshipbetween the FD gain and UL and DL SNR values, as wellas the IUI levels. For heterogeneous HD-FD networks, wedemonstrate via experiments the impact of different userSNR values and the number of FD users on the FD gain. Forexample, in a 4-node network consisting of an FD BS and 3users with various user locations and SNR values, medianexperimental FD gains of 1.25 × and 1.52 × can be achievedwhen one and two users become FD-capable, respectively.To the best of our knowledge, this is the first experimentalstudy of FD gains in such networks using a testbed com-posed of both HD and FD radios. The results demonstratethe practicality and performance of FDE-based FD radios,which are suitable for small-form-factor devices. The resultscan also serve as building blocks for developing higher layer(e.g., MAC) protocols.Finally, we numerically evaluate the FDE-based cancellersbased on measurements and validated canceller models. Wecompute achievable RF SIC under practical constraints anddiscuss various canceller design tradeoffs. We also comparethe performance of the RFIC and PCB cancellers. We showthat our optimized canceller configuration scheme achives anorder of magnitude higher RF SIC than the heuristic schemeused in the RFIC canceller [48].To summarize, the main contributions of the paper are:1. We present the design, implementation, modeling, andvalidation of the FDE-based PCB canceller, as well as anoptimized canceller configuration scheme;2. We experimentally evaluate the performance of our FDE-based FD radio with the PCB canceller and the optimizedcanceller configuration, including the achieved overallSIC and link-level FD gain;3. We experimentally evaluate the FD throughput gain invarious network settings with different user capabilities(i.e., HD or FD) and user SNR values.The rest of the paper is organized as follows. Section 2reviews related work. In Section 3, we present the problemformulation and RF canceller designs. We present the design,implementation, and model of the FDE-based PCB canceller,o appear in Proc. ACM MobiCom’19 3 Table 1:
Nomenclature | z | , ∠ z Amplitude and phase of a complex value z = x + jy ( x , y ∈ R ),where | z | = (cid:112) x + y and ∠ z = tan − (cid:0) yx (cid:1) B Total wireless bandwidth/desired RF SIC bandwidth K , k Total number of frequency channels and channel index f k Center frequency of the k th frequency channel M Number of FDE taps in an FDE-based RF canceller H SI ( f k ) Frequency response of the antenna interface H P ( f k ) Frequency response of the FDE-based PCB canceller H P i ( f k ) Frequency response of the i th FDE tap in the PCB canceller A P i , ϕ P i Amplitude and phase controls of the i th FDE tap in the PCB can-celler C F , i , C Q , i Digitally tunable capacitors that control the center frequencyand quality factor of the i th FDE tap in the PCB canceller as well as the optimized canceller configuration scheme inSection 4. The canceller model is experimentally validatedin Section 5. The performance of the FDE-based FD radiois experimentally evaluated in Sections 6. In Section 7, wenumerically evaluate the FDE-based cancellers, and comparethe RFIC and PCB implementations. We conclude and discussfuture directions in Section 8.
Extensive research related to FD wireless is summarizedin [41], including implementations of FD radios and systems,analysis of rate gains, and resource allocation at the higherlayers. Below, we briefly review the related work.
RF Canceller and FD Radio Designs.
RF SIC typically involvestwo stages: (i) isolation at the antenna interface, and (ii) SICin the RF domain using cancellation circuitry. While a sep-arate TX/RX antenna pair can provide good isolation andcan be used to achieve cancellation [6, 8, 20, 31, 32, 39], ashared antenna interface such as a circulator is more ap-propriate for single-antenna implementations [12, 23] andis compatible with FD MIMO systems. Existing designs ofanalog/RF SIC circuitry are mostly based on a time-domaininterpolation approach [12, 34]. In particular, real delay lineswith different lengths and amplitude weighting [12] andphase controls [34] are used and their configurations areoptimized to best emulate the SI channel. This essentiallyrepresents an RF implementation of a finite impulse response(FIR) filter. Based on the same RF SIC approach, several FDMIMO radio designs are presented [8, 10, 14, 22]. FD relayshave also been successfully demonstrated in [11, 13, 15, 29].Moreover, SIC can be achieved via digital/analog beamform-ing in FD massive-antenna systems [7, 26]. The techniquesutilized in these works are incompatible with IC implemen-tations, which are required for small-form-factor devices.In this paper, we focus on an FDE-based canceller, whichbuilds on our previous work towards the design of such anRFIC canceller [48]. However, existing IC-based FD radios(e.g., [48]) have not been evaluated at the system-level indifferent network settings.
RF SICanceller NI USRP and LabVIEWAntenna andCirculator H SI ( f ) H ( f ) or H FDE ( f ) Figure 2:
Block diagram of an FD radio.
FD Gain at the Link- and Network-level.
At the higher layers,recent work focuses on characterizing the capacity regionand rate gains, as well as developing resource allocation algo-rithms under both perfect [5, 9] and imperfect SIC [24, 28, 37].Similar problems are considered in FD multi-antenna/MIMOsystems [26, 38, 46]. Medium access control (MAC) algo-rithms are studied in networks with all HD users [16, 21]or with heterogeneous HD and FD users [18]. Moreover,network-level FD gain is analyzed in [39, 42, 43, 45] and ex-perimentally evaluated in [31, 33] where all the users are HDor FD. Finally, [30] proposes a scheme to suppress IUI usingan emulated FD radio.To the best of our knowledge, this is the first thorough studyof wideband RF SIC achieved via a frequency-domain-based ap-proach (which is suitable for compact implementations) that isgrounded in real-world implementation and includes extensivesystem- and network-level experimentation . In this section, we review concepts related to FD wirelessand RF canceller configuration optimization. We also presentdifferent RF canceller designs and specificaully the design ofthe FDE-based RF canceller. Summary of the main notationis provided in Table 1.
Fig. 2 shows the block diagram of a single-antenna FD ra-dio using a circulator at the antenna interface. Due to theextremely strong SI power level and the limited dynamicrange of the analog-to-digital converter (ADC) at the RX, atotal amount of 90–110 dB SIC must be achieved across theantenna, RF, and digital domains. Specifically, (i) SI suppres-sion is first performed at the antenna interface, (ii) an RF SIcanceller then taps a reference signal at the output of theTX power amplifier (PA) and performs SIC at the input ofthe low-noise amplifier (LNA) at the RX, and (iii) a digital SIcanceller further suppresses the residual SI.Consider a wireless bandwidth of B that is divided into K orthogonal frequency channels. The channels are indexedby k ∈ { , . . . , K } and denote the center frequency of the k th o appear in Proc. ACM MobiCom’19 4channel by f k . We denote the antenna interface response by H SI ( f k ) with amplitude | H SI ( f k )| and phase ∠ H SI ( f k ) . Notethat the actual SI channel includes the TX-RX leakage fromthe antenna interface as well as the TX and RX transferfunctions at the baseband from the perspective of the digitalcanceller. Since the paper focuses on achieving wideband RFSIC, we use H SI ( f k ) to denote the antenna interface responseand also refer to it as the SI channel . We refer to
TX/RX isola-tion as the ratio (in dB, usually a negative value) between theresidual SI power at the RX input and the TX output power,which includes the amount of TX/RX isolation achieved byboth the antenna interface and the RF canceller/circuitry.We then refer to
RF SIC as the absolute value of the TX/RXisolation. We also refer to overall SIC as the total amountof SIC achieved in both the RF and digital domains. The an-tenna interface used in our experiments typically provides aTX/RX isolation of around −
20 dB.
Ideally, an RF canceller is designed to best emulate the an-tenna interface, H SI ( f k ) , across a desired bandwidth, B = [ f , f K ] . We denote by H ( f k ) the frequency response of anRF canceller and by H res ( f k ) : = H SI ( f k ) − H ( f k ) the residualSI channel response . The optimized RF canceller configurationis obtained by solving (P1) : (P1) min: K (cid:205) k = | H res ( f k )| = K (cid:205) k = | H SI ( f k ) − H ( f k )| s.t.: constraints on configuration parameters of H ( f k ) , ∀ k . The RF canceller configuration obtained by solving (P1) minimizes the residual SI power referred to the TX output.As described in Section 1, one main challenge associatedwith the design of the RF canceller with response H ( f k ) to achieve wideband SIC is due to the highly frequency-selective antenna interface, H SI ( f k ) . Moreover, an efficientRF canceller configuration scheme needs to be designed sothat the canceller can adapt to time-varying H SI ( f k ) . Delay Line-based RF Cancellers.
An RF canceller design in-troduced in [12] involves using M delay line taps. Specifi-cally, the i th tap is associated with a time delay of τ i , whichis pre-selected and fixed depending on the selected circu-lator and antenna, and an amplitude control of A i . Sincethe Fourier transform of a delay of τ i is e − π f τ i , an M -tapdelay line-based RF canceller has a frequency response of We use discrete frequency values { f k } since in practical systems, theantenna interface response is measured at discrete points (e.g., per OFDMsubcarrier). However, the presented model can also be applied to cases withcontinuous frequency values. H SI ( f ) H i FDE ( f ), i = 1, 2 H FDE ( f ) (a) Decreasing A i Increasing f c,i Increasing Q i Increasing f i (b)Figure 3: (a) Block diagram of an FDE-based RF canceller with M = FDE taps, and (b) illustration of amplitude and phase responses ofan ideal nd -order BPF with amplitude, phase, center frequency, andquality factor (i.e., group delay) controls. H DL ( f k ) = (cid:205) Mi = A i e − j π f k τ i . The configurations of the am-plitude controls, { A i } , are obtained by solving (P1) with H ( f k ) = H DL ( f k ) . In [12], an RF canceller of M =
16 de-lay line taps is implemented. In [34], a similar approachis considered with M = ϕ i , on each tap, resulting in an RF canceller model of H DL ( f k ) = (cid:205) i = A i e − j ( π f k τ i + ϕ i ) . As mentioned in Section 1,although such cancellers can achieve wideband SIC, this ap-proach is more suitable for large-form-factor nodes than forcompact/small-form-factor implementations. Amplitude- and Phase-based RF Cancellers.
A compact designthat is based on an amplitude- and phase-based RF cancellerrealized in an RFIC implementation is presented in [47]. Thiscanceller has a single-tap with one amplitude and frequencycontrol, ( A , ϕ ) , which can emulate the antenna interface, H SI ( f k ) , at only one given cancellation frequency f by set-ting A = | H SI ( f )| and ϕ = ∠ H SI ( f ) . The same design isalso realized using discrete components on a PCB (withoutusing any length delay lines), and is integrated in the ORBITtestbed for open-access FD research [17]. However, this typeof RF cancellers has limited RF SIC perfromacne and band-width, since it can only emulate the antenna interface at asingle frequency. An FDE-based RF Canceller.
One compact design to achievesignificantly enhanced performance and bandwidth of RFSIC is based on the technique of frequency-domain equaliza-tion (FDE) and was implemented in an RFIC [48]. Fig. 3(a)shows the diagram of an FDE-based canceller, where parallelreconfigurable bandpass filters (BPFs) are used to emulatethe antenna interface response across wide bandwidth. Wedenote the frequency response of a general FDE-based RFcanceller consisting of M FDE taps by H FDE ( f k ) = M (cid:205) i = H FDE i ( f k ) , (1)where H FDE i ( f k ) is the frequency response of the i th FDE tapcontaining a reconfigurable BPF with amplitude and phasecontrols. Theoretically, any m th -order RF BPF ( m = , , . . . )can be used. Fig. 3(b) illustrates the amplitude and phase of ao appear in Proc. ACM MobiCom’19 5 ( R Q ) ( R Q ) PCB Bandpass Filter (BPF)
Figure 4:
Block diagram of the implemented M = FDE taps in thePCB canceller (see Fig. 3(a)), each of which consists of an RLC band-pass filter (BPF), an attenuator for amplitude control, and a phaseshifter for phase control. nd -order BPF with different control parameters. For example,increased BPF quality factors result in “sharper” BPF ampli-tudes and increased group delay. Since it is shown [27, 48]that a 2 nd -order BPF can accurately model the FDE N -pathfilter, the frequency response of an FDE-based RFIC cancellerwith M FDE taps is given by H I ( f k ) = M (cid:205) i = H I i ( f k ) = M (cid:205) i = A I i · e − jϕ I i − jQ i · (cid:0) f c , i / f k − f k / f c , i (cid:1) . (2)Within the i th FDE tap, H I i ( f k ) , A I i and ϕ I i are the amplitudeand phase controls, and f c , i and Q i are the center frequencyand quality factor of the 2 nd -order BPF (see Fig. 3(b)). In theRFIC canceller, f c , i and Q i are adjusted through a reconfig-urable baseband capacitor and transconductors, respectively.As Fig. 3(b) and (2) suggest, one FDE tap features four de-grees of freedom (DoF) so that the antenna interface, H SI ( f k ) ,can be emulated not only in amplitude and phase, but alsoin the slope of amplitude and the slope of phase (i.e., groupdelay) . Therefore, the RF SIC bandwidth can be significantlyenhanced through FDE when compared with the amplitude-and phased-based RF cancellers. In this section, we present our design and implementation ofan FDE-based canceller using discrete components on a PCB(referred to as the
PCB canceller ). Recall that the motivationis to facilitate integration with an SDR platform, the experi-mentation of FD at the link/network level, and integrationwith open-access wireless testbeds. We then present a realis-tic PCB canceller model, which is later validated (Section 5)and used in the experimental and numerical evaluations(Sections 6 and 7).
Fig. 1(a) and Fig. 3(a) show the implementation and blockdiagram of the PCB canceller with 2 FDE taps. In particular, a reference signal is tapped from the TX input using a couplerand is split into two FDE taps through a power divider. Then,the signals after each FDE tap are combined and RF SICis performed at the RX input. Each FDE tap consists of areconfigurable 2 nd -order BPF, as well as an attenuator andphase shifter for amplitude and phase controls. We refer tothe BPF here as the PCB BPF to distinguish from the one in theRFIC canceller (2). The PCB BPF (with size of 1 . × When compared to the N -path filterused in the RFIC canceller [48] that consumes certain amountof DC power, this discrete component-based passive RLCBPF has zero DC power consumption and can support higherTX power levels. Moreover, it has a lower noise level thanthe RFIC implementation.The PCB BPF center frequency in the i th FDE tap can be ad-justed through the capacitor, C F , i , in the RLC resonance tank.In order to achieve a high and adjustable BPF quality factor,impedance transformation networks including transmission-lines (T-Lines) and digitally tunable capacitors, C Q , i , are intro-duced. In our implementation, C F , i consists of two parallelcapacitors: a fixed 8 . .
12 pF. For C Q , i , we use the Peregrine Semi-conductor PE64102 digitally tunable capacitor (5-bit) with aresolution of 0 .
39 pF. In addition, the programmable attenua-tor has a tuning range of 0–15 . . Ideally, the PCB BPF has a 2 nd -order frequency response fromthe RLC resonance tank. However, in practical implementa-tion, its response deviates from that used in the FDE-basedRFIC canceller (2). Therefore, there is a need for a valid modeltailored for evaluating the performance and optimized config-uration of the PCB canceller. Based on the circuit diagram inFig. 4, we derive a realistic model for the frequency responseof the PCB BPF, H B i ( f k ) , given by H B i ( f k ) = R − s (cid:104) j sin ( βl ) Z Y F , i ( f k ) Y Q , i ( f k ) + cos ( βl ) Y F , i ( f k ) + ( βl ) Y Q , i ( f k ) + j sin ( βl )/ Z + . j sin ( βl ) Z ( Y Q , i ( f k )) − sin ( βl ) Z Y F , i ( f k )( Y Q , i ( f k )) (cid:105) − , (3) We select 900 MHz around the Region 2 902–928 MHz ISM band as theoperating frequency but the approach can be easily extended to other bands(e.g., 2 . The details can be found in Appendix 10. o appear in Proc. ACM MobiCom’19 6where Y F , i ( f k ) and Y Q , i ( f k ) are the admittance of the RLCresonance tank and impedance transformation networks, i.e., (cid:26) Y F , i ( f k ) = / R F + j πC F , i f k + /( j πL F f k ) , Y Q , i ( f k ) = / R Q + j πC Q , i f k + /( j πL Q f k ) . (4)In particular, to have perfect matching with the source andload impedance of the RLC resonance tank, R S and R L are setto be the same value of R Q = Ω (see Fig. 4). β and Z are thewavenumber and characteristic impedance of the T-Line withlength l (see Fig. 4). In our implementation, L F = .
65 nH, L Q = .
85 nH, βl ≈ .
37 rad, and Z = Ω .In addition, other components in the PCB canceller (e.g.,couplers and power divider/combiner) can introduce extraattenuation and group delay, due to implementation losses.Based on the S-Parameters of the components and measure-ments, we observed that the attenuation and group delayintroduced, denoted by A P0 and τ P0 , are constant across fre-quency in the desired bandwidth. Hence, we empirically set A = − . τ = . A P i and ϕ P i , the PCB canceller with two FDE taps is modeled by H P ( f k ) = A P0 e − j π f k τ P0 (cid:20) (cid:205) i = A P i e − jϕ P i H B i ( f k ) (cid:21) , (5)where H B i ( f k ) is the PCB BPF model given by (3). As a result,the i th FDE tap in the PCB canceller (5) has configurationparameters { A P i , ϕ P i , C F , i , C Q , i } , featuring 4 DoF. Based on (P1) , we now present a general FDE-based cancellerconfiguration scheme that jointly optimizes all the FDE tapsin the canceller. Although our implemented PCB cancellerhas only 2 FDE taps, both its model and the configurationscheme can be easily extended to the case with a largernumber of FDE taps, as described in Section 7.The inputs to the FDE-based canceller configurationscheme are: (i) the PCB canceller model (5) with given num-ber of FDE taps, M , (ii) the antenna interface response, H SI ( f k ) , and (iii) the desired RF SIC bandwidth, f k ∈ [ f , f K ] .Then, the optimized canceller configuration is obtained bysolving (P2) . (P2) min : K (cid:205) k = (cid:12)(cid:12) H Pres ( f k ) (cid:12)(cid:12) = K (cid:205) k = (cid:12)(cid:12) H SI ( f k ) − H P ( f k ) (cid:12)(cid:12) s.t.: A P i ∈ [ A Pmin , A Pmax ] , ϕ P i ∈ [− π , π ] , C F , i ∈ [ C F,min , C F,max ] , C Q , i ∈ [ C Q,min , C Q,max ] , ∀ i . The RFIC canceller presented in [48] is configured based on heuristics. InSection 7, we show that the optimized configuration scheme can significantlyimprove the RFIC canceller performance. Table 2:
Four ( C F , C Q ) configurations used in the validations. Highest Q-Factor Lowest Q-FactorHighest Center Freq. Set 1: ( C F,min , C Q,min ) Set 3: ( C F,min , C Q,max ) Lowest Center Freq. Set 2: ( C F,max , C Q,min ) Set 4: ( C F,max , C Q,max ) Note that (P2) is challenging to solve due to its non-convexity and non-linearity, as opposed to the linear pro-gram used in the delay line-based RF canceller [12]. This isdue to the specific forms of the configuration parameters in(5) such as (i) the higher-order terms introduced by f k , and(ii) the trigonometric term introduced by the phase control, ϕ P i . In addition, the antenna interface response, H SI ( f k ) , isalso frequency-selective and time-varying.In general, it is difficult to maintain analytical tractabilityof (P2) (i.e., to obtain its optimal solution in closed-form).However, in practice, it is unnecessary to obtain the globaloptimum to (P2) as long as the performance achieved bythe obtained local optimum is sufficient (e.g., at least 45 dBRF SIC is achieved). In this work, the local optimal solutionto (P2) is obtained using a MATLAB solver. The detailedimplementation and performance of the optimized cancellerconfiguration are described in Section 6.2. Validation of the PCB BPF.
We first experimentally validatethe PCB BPF model, H B i ( f k ) , given by (3). The ground truthis obtained by measuring the frequency response (using S-Parameters measurements) of the PCB BPF using a test struc-ture, which contains only the BPF, to avoid the effects of othercomponents on the PCB. The measurements are conductedwith varying ( C F , C Q ) configurations and the result of eachconfiguration is averaged over 20 measurement instances. The BPF center frequency is measured as the frequency withthe highest BPF amplitude, and the BPF quality factor is com-puted as the ratio between the center frequency and the 3 dBbandwidth around the center frequency.The PCB BPF has a fixed quality factor of 2.7, achieved byusing only the RLC resonance tank. By setting C Q = C Q,max and C Q = C Q,min (see Section 4.1), the measured lowest andhighest achievable BPF quality factors are 9.2 and 17.8, respec-tively. This shows an improvement in the PCB BPF qualityfactor tuning range of 3.4 × –6.6 × , achieved by introducingthe impedance transformation networks. Similarly, by set-ting C F = C F,max and C F = C F,min , the PCB BPF has a centerfrequency tuning range of 18 MHz.Fig. 5 presents the modeled and measured amplitude andphase responses of the PCB BPF with 4 ( C F , C Q ) configura-tions (see Table 2) which cover the entire tuning range of theBPF center frequency and quality factor. The results show We drop the subscript i , since both PCB BPFs behave identically. o appear in Proc. ACM MobiCom’19 7
850 875 900 925 950
Frequency (MHz) -20-15-10-50 A m p li t ude ( d B ) Set 1 model Set 1 meas Set 2 model Set 2 meas Set 3 model Set 3 meas Set 4 model Set 4 meas
850 875 900 925 950
Frequency (MHz) -150-120-90-60-30030 P ha s e ( deg ) Figure 5:
Modeled and measured amplitude and phase responses ofthe implemented PCB BPF under different ( C F , C Q ) configurationsindicated in Table 2. that the PCB BPF model (3) matches very closely with themeasurements at the highest BPF quality factor value (Sets 1and 2). In particular, the maximum differences between themeasured and modeled amplitude and phase are 0 . . ( C F , C Q ) configurations within their tuning ranges. Validation of the PCB Canceller.
We use the same experi-ments as in the PCB BPF validation to validate the PCBcanceller model with 2 FDE taps, H P ( f k ) , given by (5). Weconsider two cases for controlled measurements: (i) only oneFDE tap is active, and (ii) both FDE taps are active. Notethat the programmable attenuators only have a maximalattenuation of only 15 . A P1 ) with varying values of ( C F , , C Q , ) whilesetting the second FDE tap with the lowest amplitude (i.e.,highest attenuation value of A P2 ). Fig. 6 shows the modeledand measured amplitude and phase responses of the PCBcanceller in this case, i.e., only the first FDE tap is active.At the highest BPF quality factor value (Sets 1 and 2), themaximum differences between the modeled and measuredamplitude and phase are 0 . . A P1 and lowest attenuation value of A P2 . The measurementsare repeated with different { A P i , ϕ P i , C F , i , C Q , i } settings for i = ,
2, and all the results demonstrate the same level ofaccuracy of the PCB canceller model (5).
In this section, we discuss the integration of the PCB can-celler described in Section 4 with an SDR testbed. Then, we
850 875 900 925 950
Frequency (MHz) -30-25-20-15-10 A m p li t ude ( d B ) Set 1 model Set 1 meas Set 2 model Set 2 meas Set 3 model Set 3 meas Set 4 model Set 4 meas
850 875 900 925 950
Frequency (MHz) -180-90090180 P ha s e ( deg ) Figure 6:
Modeled and measured amplitude and phase responses ofthe PCB canceller, where only the first FDE tap is active, under dif-ferent ( C F , C Q ) configurations indicated in Table 2. present extensive experimental evaluation of the FDE-basedFD radio at the node, link, and network levels. FDE-based FD Radio and the SDR Testbed.
Figs. 1(b) and 1(c)depict our FDE-based FD radio design (whose diagram isshown in Fig. 2) and the SDR testbed. A 698–960 MHz swivelblade antenna and a coaxial circulator with operating fre-quency range 860–960 MHz are used as the antenna interface.We use the NI USRP-2942 SDR with the SBX-120 daughter-board operating at 900 MHz carrier frequency, which is thesame as the operating frequency of the PCB canceller. Asmentioned in Section 4.1, our PCB canceller design can beeasily extended to other operating frequencies. and the an-tenna interface. The USRP has a measured noise floor of −
85 dBm at a fixed receiver gain setting. We implemented a full OFDM-based PHY layer usingNI LabVIEW on a host PC. A real-time RF bandwidth of B =
20 MHz is used through our experiments. The basebandcomplex (IQ) samples are streamed between the USRP andthe host PC through a high-speed PCI-Express interface. TheOFDM symbol size is 64 samples (subcarriers) with a cyclic-prefix ratio of 0.25 (16 samples). Throughout the evaluation, { f k } K = k = is used to represent the center frequency of the 52non-zero subcarriers. The OFDM PHY layer supports variousmodulation and coding schemes (MCSs) with constellationsfrom BPSK to 64QAM and coding rates of 1/2, 2/3, and 3/4,resulting in a highest (HD) data rate of 54 Mbps. The digitalSIC algorithm with a highest non-linearity order of 7 is alsoimplemented in LabVIEW to further suppress the residual SIsignal after RF SIC. In total, our testbed consists of 3 FDE-based FD radios,whose performance is experimentally evaluated at the node,link, and network levels. Regular USRPs (without the PCB This USRP receiver noise floor is limited by the environmental interferenceat around 900 MHz. The USRP has a true noise floor of around −
95 dBm atthe same receiver gain setting, when not connected to an antenna. We consider a general OFDM-based PHY but do not consider the specificframe/packet structure defined by the standards (e.g., LTE or WiFi PHY). The digital SIC algorithm is based on Volterra series and a least-squareproblem, which is similar to that presented in [12]. We omit the details heredue to limited space. o appear in Proc. ACM MobiCom’19 8
Subcarrier Index -0.1-0.0500.050.1 A m p li t ude ( m W ) (a) Subcarrier Index -60-40-20020 P o w e r ( d B m ) TX signalRX signal w/ RF SIC modelRX signal w/ RF SIC meas (b)Figure 7: (a) Real and imaginary parts of the optimized PCB cancellerresponse, H P ( f k ) , vs. real-time SI channel measurements, H SI ( f k ) ,and (b) modeled and measured RX signal power after RF SIC at
10 dBm
TX power. An average
52 dB
RF SIC across
20 MHz is achievedin the experiments. canceller) are also included in scenarios where additionalHD users are needed.
Optimized PCB Canceller Configuration.
The optimized PCBcanceller configuration scheme is implemented on the hostPC and the canceller is configured by a SUB-20 controllerthrough the USB interface. For computational efficiency, thePCB canceller response (5) (which is validated in Section 5and is independent of the environment) is pre-computed andstored. The detailed steps of the canceller configuration areas follows.1. Measure the real-time antenna interface response, H SI ( f k ) , using a preamble (2 OFDM symbols) by dividingthe received preamble by the known transmitted pream-ble in the frequency domain;2. Solve for an initial PCB canceller configuration usingoptimization (P2) based on the measured H SI ( f k ) and thecanceller model (5) (see Section 4.3). The returned config-uration parameters are rounded to their closest possiblevalues based on hardware resolutions (see Section 4.1);3. Perform a finer-grained local search and record the opti-mal canceller configuration (usually ~
10 iterations).In our design, the optimized PCB canceller configuration canbe obtained in less than 10 ms on a regular PC with quad-coreIntel i7 CPU via a non-optimized MATLAB solver. Optimized PCB Canceller Response and RF SIC.
We set up anFDE-based FD radio running the optimized PCB cancellerconfiguration scheme and record the canceller configuration,measured H SI ( f k ) , and measured residual SI power after RFSIC. The recorded canceller configuration is then used tocompute the PCB canceller response using (5). Assuming that the canceller needs to be configured once per second, thisis only a 1% overhead. We note that a C-based optimization solver and/oran implementation based on FPGA/look-up table can significantly improvethe performance of the canceller configuration and is left for future work.
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Frequency (MHz) -100-80-60-40-20020 P o w e r ( d B m ) TX signal RX signal w/ RF SIC RX signal w/ dig SIC RX noise floor 52 dB RF SIC 43 dB digital SIC
Figure 8:
Power spectrum of the received signal after SIC in the RFand digital domains with
10 dBm average TX power,
20 MHz band-width, and −
85 dBm receiver noise floor.
Fig. 7(a) shows an example of the optimized PCB cancellerresponse, H P ( f k ) , and the measured antenna interface re-sponse, H SI ( f k ) , in real and imaginary parts (or I and Q). Itcan be seen that H P ( f k ) closely matches with H SI ( f k ) withmaximal amplitude and phase differences of only 0 . . H SI ( f k ) ) and measured RX signal power after RF SICat 10 dBm TX power. The results show that the FDE-basedFD radio achieves an average 52 dB RF SIC across 20 MHzbandwidth, from which 20 dB is obtained from the antennainterface isolation. Similar performance is observed in vari-ous experiments throughout the experimental evaluation. Overall SIC.
We measure the overall SIC achieved by theFDE-based FD radio including the digital SIC in the samesetting as described above, and the results are presented inFig. 8. It can be seen that the FDE-based FD radio achievesan average 95 dB overall SIC across 20 MHz, from which52 dB and 43 dB are obtained in the RF and digital domains,respectively. Recall from Section 6.1 that the USRP has noisefloor of −
85 dBm, the FDE-based RF radio supports a maximalaverage TX power of 10 dBm (where the peak TX power cango as high as 20 dBm). We use TX power levels lower thanor equal to 10 dBm throughout the experiments, where allthe SI can be canceled to below the RX noise floor.
We now evaluate the relationship between link SNR and linkpacket reception ratio (PRR). We setup up a link with twoFDE-based FD radios at a fixed distance of 5 meters withequal TX power. In order to evaluate the performance of ourFD radios with the existence of the PCB canceller, we setan FD radio to operate in HD mode by turning on only itstransmitter or receiver. We conduct the following experimentfor each of the 12 MCSs in both FD and HD modes, witho appear in Proc. ACM MobiCom’19 9
HD Link SNR (dB) L i n k P RR (a) Code rate 1/2
HD Link SNR (dB) L i n k P RR BPSK HDBPSK FDQPSK HDQPSK FD16QAM HD16QAM FD64QAM HD64QAM FD (b)
Code rate 3/4
Figure 9:
HD and FD link packet reception ratio (PRR) with varyingHD link SNR and modulation and coding schemes (MCSs). varying TX power levels. In particular, the packets are sentover the link simultaneously in FD mode or in alternatingdirections in HD mode (i.e., the two radios take turns andtransmit to each other). In each experiment, both radios senda sequence of 50 OFDM streams, each OFDM stream contains20 OFDM packets, and each OFDM packet is 800-Byte long.We consider two metrics. The
HD (resp. FD) link SNR ismeasured as the ratio between the average RX signal powerin both directions and the RX noise floor when both radiosoperate in HD (resp. FD) mode. The
HD (resp. FD) link PRR is computed as the fraction of packets successfully sent overthe HD (resp. FD) link in each experiment. We observe fromthe experiments that the HD and FD link SNR and PRR valuesin both link directions are similar. Similar experiments andresults were presented in [50] for HD links.Fig. 9 shows the relationship between link PRR values andHD link SNR values with varying MCSs. The results showthat with sufficient link SNR values (e.g., 8 dB for BPSK-1/2and 28 dB for 64QAM-3/4), the FDE-based FD radio achievesa link PRR of 100%. With insufficient link SNR values, theaverage FD link PRR is 6 .
5% lower than the HD link PRRacross varying MCSs. This degradation is caused by the linkSNR difference when the radios operate in HD or FD mode,which is described later in Section 6.4. Since packets aresent simultaneously in both directions on an FD link, thisaverage PRR degradation is equivalent to an average FD linkthroughput gain of 1 . × under the same MCS. Experimental Setup.
To thoroughly evaluate the link level FDthroughput gain achieved by our FD radio design, we conductexperiments with two FD radios with 10 dBm TX power,one emulating a base station (BS) and one emulating a user.We consider both line-of-sight (LOS) and non-line-of-sight(NLOS) experiments as shown in Fig. 10. In the LOS setting,the BS is placed at the end of a hallway and the user is movedaway from the BS at stepsizes of 5 meters up to a distanceof 40 meters. In the NLOS setting, the BS is placed in a labenvironment with regular furniture and the user is placedat various locations (offices, labs, and corridors). We placethe BS and the users at about the same height across all the m TX Power10 dBm (a)
LOS deployment and an FD radio in a hallway
BSUser m (b) NLOS deployment and an FD radio in a lab environment
Figure 10: (a) Line-of-sight (LOS), and (b) non-line-of-sight (NLOS)deployments, and the measured HD link SNR values (dB).
25 30 35 40 45 50
HD Link SNR (dB) S NR D i ff e r en c e ( d B ) (a) LOS Experiment
HD Link SNR (dB) S NR D i ff e r en c e ( d B ) (b) NLOS Experiment
Figure 11:
Difference between HD and FD link SNR values in the (a)LOS, and (b) NLOS experiments, with
10 dBm
TX power and 64QAM-3/4 MCS. experiments. The measured HD link SNR values are alsoincluded in Fig. 10. Following the methodology of [12], foreach user location, we measure the link SNR difference , whichis defined as the absolute difference between the average HDand FD link SNR values. Throughout the experiments, linkSNR values between 0–50 dB are observed.
Difference in HD and FD Link SNR Values.
Fig. 11 shows themeasured link SNR difference as a function of the HD linkSNR (i.e., for different user locations) in the LOS and NLOS ex-periments, respectively, with 64QAM-3/4 MCS. For the LOSexperiments, the average link SNR difference is 0 . .
16 dB. For the NLOS experiments, theaverage link SNR difference is 0 .
63 dB with a standard devia-tion of 0 .
31 dB. The SNR difference has a higher variance inthe NLOS experiments, due to the complicated environments(e.g., wooden desks and chairs, metal doors and bookshelves,etc.). In both cases, the link SNR difference is minimal anduncorrelated with user locations, showing the robustness ofthe FDE-based FD radio. In this work, we emulate the BS and users without focusing on specificdeployment scenarios. The impacts of different antenna heights and userdensities, as mentioned in [36], will be considered in future work. o appear in Proc. ACM MobiCom’19 10
BPSK QPSK 16QAM 64QAM
Constellation S NR D i ff e r en c e ( d B ) (a) SNR Difference (dB) CD F BPSK QPSK 16QAM 64QAM (b)Figure 12:
Difference between HD and FD link SNR values with
10 dBm
TX power under varying constellations: (a) mean and stan-dard deviation, and (b) CDF.
Impact of Constellations.
Fig. 12 shows the measured linkSNR difference and its CDF with varying constellations and3/4 coding rate. It can be seen that the link SNR differencehas a mean of 0 .
58 dB and a standard deviation of 0 . FD Link Throughput and Gain.
For each user location in theLOS and NLOS experiments, the HD (resp. FD) link through-put is measured as the highest average data rate across allMCSs achieved by the link when both nodes operate in HD(resp. FD) mode . The FD gain is computed as the ratio be-tween FD and HD throughput values. Recall that the maximalHD data rate is 54 Mbps, an FD link data rate of 108 Mbpscan be achieved with an FD link PRR of 1.Fig. 13 shows the average HD and FD link throughputwith varying 16QAM-3/4 and 16QAM-3/4 MCSs, where eachpoint represents the average throughput across 1,000 packets.The results show that with sufficient link SNR (e.g., 30 dB for64QAM-3/4 MCS), the FDE-based FD radios achieve an exact link throughput gain of 2 × . In these scenarios, the HD/FDlink always achieves a link PRR of 1 which results in themaximum achievable HD/FD link data rate. With mediumlink SNR values, where the link PRR less than 1, the averageFD link throughput gains across different MCSs are 1 . × and 1 . × for the LOS and NLOS experiments, respectively.We note that if higher modulation schemes (e.g., 256QAM)are considered and the corresponding link SNR values arehigh enough for these schemes, the HD/FD throughput canincrease (compared to the values in Fig. 13). However, con-sidering such schemes is not required in order to evaluatethe FDE-based cancellers and the FD gain. We now experimentally evaluate the network-level through-put gain introduced by FD-capable BS and users. The userscan significanlty benefit from the FDE-based FD radio suit-able for hand-held devices. We compare experimental resultsto the analysis (e.g., [37]) and demonstrate practical FD gainin different network settings. Specifically, we consider twotypes of networks as depicted in Fig. 14: (i)
UL-DL networks
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HD Link SNR (dB) L i n k T h r oughpu t ( M bp s ) Avg gain: 1.91x (a)
LOS Experiment
HD Link SNR (dB) L i n k T h r oughpu t ( M bp s ) Avg gain: 1.85x (b)
NLOS Experiment
Figure 13:
HD and FD link throughput in the (a) LOS, and (b) NLOSexperiments, with
10 dBm
TX power and 16QAM-3/4 and 64QAM-3/4MCSs. g U L = d B g U L = d B g U L = d B g I U I g D L FD BSHD User 1HD User 2 g Self (a) g g FD BSFD User 1FD User 2 g Self g Self g Self (b) g g g FD BSFD User 1FD User 2 g Self g Self g Self
HD User 3 (c)Figure 14:
An example experimental setup for: (a) the UL-DL net-works with varying γ UL and γ DL , (b) heterogeneous 3-node networkwith one FD BS and 2 FD users, and (c) heterogeneous 4-node net-works with one FD BS, 2 FD users, and one HD user. with one FD BS and two HD users with inter-user interfer-ence (IUI), and (ii) heterogeneous HD-FD networks with HDand FD users. Due to software challenge with implementinga real-time MAC layer using a USRP, we apply a TDMA set-ting where each (HD or FD) user takes turn to be activatedfor the same period of time. We first consider UL-DLnetworks consisting of one FD BS and two HD users (indexed1 and 2). Without loss of generality, in this setting, user 1transmits on the UL to the BS, and the BS transmits to user2 on the DL (see Fig. 14(a)).
Analytical FD gain . We use Shannon’s capacity formula r ( γ ) = B · log ( + γ ) to compute the analytical throughput of a link under bandwidth B and link SNR γ . If the BS is onlyHD-capable, the network throughput in a UL-DL networkwhen the UL and DL share the channel in a TDMA mannerwith equal fraction of time is given by r HDUL-DL = B ( + γ UL ) + B ( + γ DL ) , (6)where γ UL and γ DL are the UL and DL SNRs, respectively. Ifthe BS is FD-capable, the UL and DL can be simultaneouslyactivated with an analytical network throughput of r FDUL-DL = B log (cid:18) + γ UL + γ Self (cid:19) + B log (cid:18) + γ DL + γ IUI (cid:19) , (7)where: (i) (cid:16) γ DL + γ IUI (cid:17) is the signal-to-interference-plus-noiseratio (SINR) at the DL HD user, and (ii) γ Self is the resid-ual self-interference-to-noise ratio (XINR) at the FD BS. Weset γ Self =
10 15 20 25 30 35 40
DL SNR, DL (dB) I U I, I U I ( d B ) (a) γ UL =
10 dB
10 15 20 25 30 35 40
DL SNR, DL (dB) I U I, I U I ( d B ) (b) γ UL =
15 dB
10 15 20 25 30 35 40
DL SNR, DL (dB) I U I, I U I ( d B ) (c) γ UL =
20 dBFigure 15:
Analytical (colored surface) and experimental (filled cir-cles) network throughput gain for UL-DL networks consisting ofone FD BS and two HD users with varying UL and DL SNR val-ues, and inter-user interference (IUI) levels: (a) γ UL =
10 dB , (b) γ UL =
15 dB , and (c) γ UL =
20 dB . The baseline is the network through-put when the BS is HD.
Table 3:
Average FD Gain in UL-DL Networks with IUI.
UL SNR, γ UL Analytical FD Gain Experimental FD Gain
10 dB 1 . × . ×
15 dB 1 . × . ×
20 dB 1 . × . × floor (which can be achieved by the FDE-based FD radio, seeSection 6.2). The analytical FD gain is then defined as theratio (cid:0) r FDUL-DL / r HDUL-DL (cid:1) . Note that the FD gain depends on thecoupling between γ UL , γ DL , and γ IUI , which depend on theBS/user locations, their TX power, etc.
Experimental FD gain . The experimental setup is depictedin Fig. 14(a), where the TX power levels of the BS and user1 are set to be 10 dBm and −
10 dBm, respectively. We fixthe location of the BS and consider different UL SNR valuesof γ UL = / /
20 dB by placing user 1 at three differentlocations. For each value of γ UL , user 2 is placed at 10 differentlocations, resulting in varying γ DL and γ IUI values.Fig. 15 shows the analytical (colored surface) and exper-imental (filled circles) FD gain, where the analytical gainis extracted using (6) and (7), and the experimental gain iscomputed using the measured UL and DL throughput. It canbe seen that smaller values of γ UL and lower ratios between γ DL and γ IUI lead to higher throughput gains in both analysisand experiments. The average analytical and experimentalFD gains are summarized in Table 3. Due to practical rea-sons such as the link SNR difference and its impact on linkPRR (see Section 6.3), the experimental FD gain is 7% lowerthan the analytical FD gain. The results confirm the analy-sis in [37] and demonstrate the practical FD gain achievedin wideband UL-DL networks without any changes in thecurrent network stack (i.e., only bringing FD capability tothe BS). Moreover, performance improvements are expectedthrough advanced power control and scheduling schemes.
We consider hetero-geneous HD-FD networks with 3 nodes: one FD BS and two
User 2 SNR (dB) U s e r S NR ( d B ) (a) Only user 1 FD
User 2 SNR (dB) U s e r S NR ( d B ) (b) Only user 2 FD
User 2 SNR (dB) U s e r S NR ( d B ) (c) Both users FD
Figure 16:
Analytical (colored surface) and experimental (filled cir-cles) network throughput gain for 3-node networks consisting ofone FD BS and two users with varying link SNR values: (a) only user1 is FD, (b) only user 2 is FD, and (c) both users are FD. The baselineis the network throughput when both users are HD. users that can operate in either HD or FD mode (see an ex-ample experimental setup in Figs.1(c) and 14(b)). All 3 nodeshave the same 0 dBm TX power so that each user has sym-metric UL and DL SNR values of γ i ( i = , ( γ , γ ) . Analytical FD gain . We set the users to share the channel ina TDMA manner. The analytical network throughput in a 3-node network when zero, one, and two users are FD-capableis respectively given by r HD = B ( + γ ) + B ( + γ ) , (8) r HD-FDUser i FD = B log (cid:18) + γ i + γ Self (cid:19) + B (cid:0) + γ i (cid:1) , (9) r FD = B log (cid:18) + γ + γ Self (cid:19) + B log (cid:18) + γ + γ Self (cid:19) , (10)where γ Self = (cid:0) r HD-FDUser i FD / r HD (cid:1) (i.e., user i is FD and user i (cid:44) i is HD), and (cid:0) r FD / r HD (cid:1) (i.e., both users are FD). Experimental FD gain . For each pair of ( γ , γ ) , experimen-tal FD gain is measured in three cases: (i) only user 1 is FD,(ii) only user 2 is FD, and (iii) both users are FD. Fig. 16 showsthe analytical (colored surface) and experimental (filled cir-cles) FD gain for each case. We exclude the results with γ i < γ Self = SNR of User 2, (dB) F a i r ne ss = 15dB HD = 15dB FD = 20dB HD = 20dB FD = 25dB HD = 25dB FD Figure 17:
Measured Jain’s fairness index (JFI) in 3-node networkswhen both users are HD and FD with varying ( γ , γ ) . the FD gain is more significant when enabling FD capabilityfor users with higher link SNR values.Another important metric we consider is the fairness be-tween users, which is measured by the Jain’s fairness index(JFI). In the considered 3-node networks, the JFI ranges be-tween 1/2 (worst case) and 1 (best case). Fig. 17 shows themeasured JFI when both users operate in HD or FD mode. Theresults show that introducing FD capability results in an av-erage degradation in the network JFI of only 5 . / . / . γ = / /
25 dB, while the average network FD gainsare 1 . × /1 . × /1 . × , respectively. In addition, the JFI in-creases with higher and more balanced user SNR values,which is as expected. We experimentallystudy 4-node networks consisting of an FD BS and three userswith 10 dBm TX power (see an example experimental setup inFig. 14(c)). The experimental setup is similar to that describedin Section 6.5.2. 100 experiments are conducts where the 3users are placed at different locations with different userSNR values. For each experiment, the network throughputis measured in three cases where: (i) zero, (ii) one, and (iii)two users are FD-capable.Fig. 18 shows the CDF of the network throughput of thethree cases, where the measured link SNR varies between 5–45 dB. Overall, median network FD gains of 1 . × and 1 . × are achieved in cases with one and two FD users, respectively.The trend shows that in a real-world environment, the totalnetwork throughput increases as more users become FD-capable, and the improvement is more significant with higheruser SNR values. Note that we only apply a TDMA schemeand a more advanced MAC layer (e.g., [33]) has the potentialto improve the FD gain in these networks. In this section, we numerically evaluate and compare theperformance of the FDE-based RFIC [48] and PCB cancellers based on measurements and validated models . We confirmthat the PCB canceller emulates its RFIC counterpart andshow that the optimized canceller configuration scheme can
Network Throughput (Mbps) CD F All HDUser 1 FDUsers 1 & 2 FD
Med. gain1.25x Med. gain1.52x
Figure 18:
Experimental network throughput gain for 4-node net-works when zero, one, or two users are FD-capable, with
10 dBm
TXpower and varying user locations. significantly improve the performance of the RFIC canceller.We also evaluate the performance of FDE-based cancellerswith respect to the number of FDE taps, M , and desired RFSIC bandwidth, B , and discuss various design tradeoffs. We use a real, practical antenna interface response, H SI ( f k ) ,measured in the same setting as described in Section 6.1, andconsider M ∈ { , , , } and B ∈ { , , } MHz. We onlyreport the RF SIC performance with up to 4 FDE taps since,as we will show, this case can achieve sufficient RF SIC upto 80 MHz bandwidth. We use (2) to both model and evaluate the RFIC cancellerwith configuration parameters { A I i , ϕ I i , f c , i , Q i } , since it isshown that a 2 nd -order BPF can accurately model the FDE N -path filter [27, 48]. Similar to (P2) (see Section 4.3), theoptimized RFIC canceller configuration can be obtained bysolving (P3) with H I ( f k ) given by (2). (P3) min : K (cid:205) k = (cid:12)(cid:12) H Ires ( f k ) (cid:12)(cid:12) = K (cid:205) k = (cid:12)(cid:12) H SI ( f k ) − H I ( f k ) (cid:12)(cid:12) s.t.: A I i ∈ [ A Imin , A Imax ] , ϕ I i ∈ [− π , π ] , f c , i ∈ [ f c,min , f c,max ] , Q i ∈ [ Q min , Q max ] , ∀ i . Note that in [48], there is no optimization of the RFIC can-celler configuration, and the canceller is configured basedon a heuristic approach. As we will show, the optimized can-celler scheme outperforms the heuristic approach by an orderof magnitude in terms of the amount of RF SIC achieved.The implemented PCB canceller includes only M = M > M (i.e., four DoF We select typical values of 20 / /
80 MHz as the desired RF SIC bandwidth,since the circulator has a frequency range of 100 MHz. o appear in Proc. ACM MobiCom’19 13per FDE tap), we will show that M = (P2) and (P3) . Instead, they are often restricted to discretevalues given the resolution of the corresponding hardwarecomponents. To address this problem, we evaluate the can-celler models in both the ideal case and the case with practicalquantization constraints . The canceller configuration withquantization constraints are obtained by rounding the con-figuration parameters returned by solving (P2) or (P3) totheir closest quantized values.In particular, the RFIC canceller has the following con-straints: ∀ i , A I i ∈ [− , − ] dB, ϕ I i ∈ [− π , π ] , f c , i ∈[ , ] MHz, and Q i ∈ [ , ] . When adding practicalquantization constraints, we assume that the amplitude A I i has a 0 .
25 dB resolution within its range. For ϕ I i , f c , i , and Q i , an 8-bit resolution constraint is introduced, which isequivalent to 2 =
256 discrete values spaced equally in thegiven range. These constraints are practically selected andcan be easily realized in an IC implementation. The PCB can-celler model has following constraints: ∀ i , A P i ∈ [− . , ] dB, ϕ P i ∈ [− π , π ] , C F , i ∈ [ . , . ] pF, and C Q , i ∈ [ , ] pF. Whenadding the quantization constraints, we consider 0 . .
12 pF, and 0 .
39 pF resolution to A P i , C F , i , and C Q , i , respec-tively. For ϕ P i , an 8-bit resolution is introduced. These num-bers are consistent with our implementation and experi-ments (see Sections 4.1 and 6). Fig. 19 shows the TX/RX isolation achieved by the RFIC andPCB cancellers with optimized canceller configuration, withvarying M and B in the ideal case (i.e., without quantizationconstraints). It can be seen that: (i) under a given value of B ,a larger number of FDE taps results in higher average RF SIC,and (ii) for a larger value of B , more FDE taps are requiredto achieve sufficient RF SIC. For example, the ideal RFICand PCB cancellers with 2 FDE taps can achieve an average50 / /
42 dB and 50 / /
35 dB RF SIC across 20 / /
80 MHzbandwidth, respectively.Fig. 20 shows the TX/RX isolation achieved by the RFICand PCB cancellers with optimized canceller configura-tion under practical quantization constraints. Comparingto Fig. 19, the results show a performance degradation dueto limited hardware resolutions, which is more significant as M increases. This is because a larger value of M introducesa higher number of DoF with more canceller parametersthat can be flexibly controlled. As a result, the RF SIC perfor-mance is more sensitive to the coupling between individual
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Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
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Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
20 MHz
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Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
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Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
40 MHz
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Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B ) (a) RFIC Canceller
850 875 900 925 950
Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
80 MHz (b)
PCB Canceller
Figure 19:
TX/RX isolation of the antenna interface (black curve) andwith the RFIC and PCB cancellers with varying number of FDE taps, M ∈ { , , , } , and desired RF SIC bandwidth, B ∈ { , , } MHz ,in the ideal case.
850 875 900 925 950
Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
850 875 900 925 950
Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
20 MHz
850 875 900 925 950
Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
850 875 900 925 950
Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
40 MHz
850 875 900 925 950
Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B ) (a) RFIC Canceller
850 875 900 925 950
Frequency (MHz) -80-70-60-50-40-30-20-10 T X / R X I s o l a t i on ( d B )
80 MHz (b)
PCB Canceller
Figure 20:
TX/RX isolation of the antenna interface (black curve) andwith the RFIC and PCB cancellers with varying number of FDE taps, M ∈ { , , , } , and desired RF SIC bandwidth, B ∈ { , , } MHz ,under practical quantization constraints.
FDE tap responses after quantization. The results show thatunder practical constraints, the RFIC and PCB cancellerswith 4 FDE taps can still achieve an average 54 / /
45 dB ando appear in Proc. ACM MobiCom’19 14
Table 4:
Comparison between the PCB and RFIC cancellers.
PCB (this work) RFIC [48]Center Frequency
900 MHz 1 .
37 GHz
20 dB 35 dB
Canceller SIC (
20 MHz )
32 dB 20 dB
Canceller Configuration Optimization (P2)
HeuristicDigital SIC
43 dB
N/AEvaluation Node/Link/Network Node / /
39 dB RF SIC across 20 / /
80 MHz bandwidth, respec-tively. Fig. 20 also shows that the RFIC canceller under theoptimized configuration scheme achieves a 10 dB higher RFSIC compared with that achieved by the heuristic approachdescribed in [48] (labeled “Heur”).It is interesting to observe that the RF SIC profile of thePCB canceller with 2 FDE taps is very similar to our experi-mental results (see Fig. 7 in Section 6.2). It is also worth not-ing that, in practice, adding more FDE taps cannot improvethe amount of RF SIC in some scenarios (e.g., with 20 MHzbandwidth), which is limited by the quantization constraints.However, performance improvement is expected by relax-ing these constraints (e.g., through using components withhigher resolutions and/or wider tuning ranges).Table 4 shows the comparison between our implementedPCB canceller and the RFIC canceller presented in [48]. Tosummarize, we numerically show that the performance ofthe RFIC and PCB cancellers is similar. The results based onmeasurements and validated canceller models confirm thatthe PCB canceller accurately emulates its RFIC counterpart,and that the FDE-based approach is valid and suitable forachieving wideband RF SIC in small-form-factor devices.
We designed and implemented a PCB canceller using theFDE technique, which was shown to achieve wideband RFSIC in compact nodes. We presented a PCB canceller modeland a scheme for optimizing the canceller configuration. Weexperimentally evaluated the performance of the FDE-basedFD radio at the node, link, and network levels using an SDRtestbed. We also compared the RFIC and PCB implementa-tions and discussed various design tradeoffs of the FDE-basedcanceller. Future directions include: (i) better design and im-plementation of FDE-based canceller to support higher TXpower handling and RF SIC bandwidth, (ii) extension of theFDE technique to multi-antenna systems, (iii) integration inopen-access testbeds, and (iv) development and experimentalevaluation of resource allocation and scheduling algorithmstailored for FDE-based FD radios.
This work was supported in part by NSF grants ECCS-1547406, CNS-1650685, and CNS-1827923. We thank JacksonWelles for his contributions to the assembly and testing ofthe PCB cancellers.
10 APPENDIX A: THE PCB BPF MODEL
We use transmission (ABCD) matrix to derive H B i ( f ) , givenby (3). From Fig. 4 and Y F ( f k ) and Y Q ( f k ) in (4), (cid:20) V in I in (cid:21) = (cid:20) Y Q ( f k ) (cid:21) M TL (cid:20) Y F ( f k ) (cid:21) M TL (cid:20) Y Q ( f k ) (cid:21) (cid:20) V out I out (cid:21) : = (cid:20) M BPF A ( f k ) M BPF B ( f k ) M BPF C ( f k ) M BPF D ( f k ) (cid:21) (cid:20) V out I out (cid:21) , (11)where M TL is the ABCD matrix of a T-Line with wavenumber β , characteristic impedance Z , and length l , i.e., M TL = (cid:20) cos ( βl ) jZ sin ( βl ) j sin ( βl )/ Z cos ( βl ) (cid:21) . (12)With the parameters described in Section 4.1, the frequencyresponse of the implemented PCB BPF, H B i ( f k ) , is given by H B i ( f k ) = V out ( f k ) V in ( f k ) = R S · V out ( f k ) I in ( f k ) = R S · M BPF C ( f k ) . Plugging (4) and (12) into (11) yields the model H B i ( f ) . REFERENCES
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