Automated Evaluation of Concurrent Error Detection Code Protected Hardware Implementations

Abstract

Parity-based concurrent error detection (CED) techniques are often deployed as a countermeasure to fault injection attacks, owing to their low-overhead in hardware. Advanced linear and non-linear randomized encoding can be employed for constructing varying CED schemes. In this chapter, we provide an automated evaluation method to estimate the detection capability of both linear and non-linear parity-protected ciphers in the presence of fault attacks. The method takes the device characteristics into account to provide accurate results on fault coverage. Case study on PRESENT-80 CED-protected implementation is provided to show the usage and practicality of such method.