A Reconfigurable Implementation of Elliptic Curve Cryptography over GF (2n)

Abstract

In this chapter, a high-performance area-efficient reconfigurable design for the Elliptic Curve Cryptography (ECC), targeting the area-constrained high-bandwidth embedded applications, is presented. The proposed design is implemented using pipelining architecture. The applied architecture is performed using n-bit data path of the finite field GF (\\(2^{n}\\)). For the finite field operations, the implementation in the ECC uses the bit-parallel recursive Karatsuba-Ofman algorithm for multiplication and Itoh-Tsuji for inversion. An improved Montgomery ladder algorithm is utilized for the scalar multiplication of a point. Balanced-execution data paths in components of the ECC core are guaranteed by inserting pipelined registers in ideal locations. The proposed design has been implemented using Xilinx Virtex, Kintex and Artix FPGA devices. It can perform a single scalar multiplication in 226 clock cycles within 0.63 \\(\\upmu \\)s using 2780 slices and 360 Mhz working frequency on Virtex-7 over GF (\\(2^{163}\\)). In GF (\\(2^{233}\\)) and GF (\\(2^{571}\\)), a scalar multiplication can be computed in 327 and 674 clock cycles within 1.05 \\(\\upmu \\)s and 2.32 \\(\\upmu \\)s, respectively. Compared with previous works, our reconfigurable design reduces the required number of clock cycles and operates using fewer FPGA resources with competitive high working frequencies. Therefore, the proposed design is well suited in the low-powered resource-constrained real-time cryptosystems such as online banking services, wearable smart devices and network attached storages.