FPGA-Based Implementation of Digital Filters for Image Denoising

Abstract

Image processing has an important role in signal processing. The occurrence of noise in the image can degrade its quality and can cause loss of information. In this paper, design of Gaussian, mean, and median filters is considered. Gaussian and mean filters are linear filters and are designed using convolution between 3 × 3 image pixel matrix and kernel matrix. The median filter is a nonlinear filter. An SRAM-based FPGA implementation of such a filter is susceptible to memory bit flips that are caused by single-event upsets (SEUs). Hence, a protection method is needed to ensure proper working of the median filter. Here, the median filter design proposed in (Aranda et al. in J. IEEE Transactions on Nuclear Science 64:2219–2226, 2017 [7]) is used to check if the median value obtained is within a dynamic range. The performance of these three filters is evaluated by considering image quality metrics such as PSNR and correlation coefficient with four different noises. The results show choice of the filter for denoising, based on the type of noise present in the image. In recent times, FPGA technology has become a reliable method for implementing image processing algorithms due to their fast response compared to image processing in MATLAB. The noisy image to pixel conversion is done in MATLAB. The 3 × 3 sliding window approach is used for filter coding in Verilog, and the FPGA synthesis on virtex5 is done with Xilinx ISE 14.5. The images are reconstructed with filtered pixels in MATLAB.