A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS

Abstract

This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the least significant bits (LSBs) in the digital-to-analog capacitor array, which reduces the incomplete settling error and releases the requirements on the RV-buffer to achieve lower power dissipation. The SAR ADC is fabricated in 40-nm CMOS technology occupying 0.13 mm\n $$^{2}$$\n area. At 1.1 V supply voltage and 80 MHz sampling frequency, the ADC achieves 50.7 dB SNDR, 69.5 dBc SFDR with a 1 MHz input at −8 dBFS. The total power consumption of the ADC is 2.99 mW, including the reference buffer power consumption of 2 mW. The Schreier FoM is 164.1 dB.