2+2 MASH incremental ADC

Abstract

In this paper, 2+2 multi-stage noise shaping incremental ΔΣ ADC for wideband and high accuracy application is described and analyzed. The modulator introduced inter-stage gain to reduce the quantization noise without adding any hardware. Also, a gain scaling technique was used to decrease the power consumption by reducing the integrators’ output swing. A proof-of-concept prototype was fabricated with 0.18\xa0μm 2P4M CMOS process. It achieved a 94.2\xa0dB dynamic range and 74.8\xa0dB SNDR in the 1.25\xa0MHz signal band. The total power consumption is 67.1\xa0mW with dual power supplies (analog 3.3\xa0V, digital 1.8\xa0V).