A discrete-time double-quadrature low-IF receiver for multi-standard and multi-carrier applications

Abstract

In this work, we present a new RF receiver architecture capable of addressing different RF bands and communication protocols. The frequency planning and discrete-time complex signal processing choices greatly simplify the frequency synthesis circuit. Since this is one of the most power-hungry blocks in the receiver, one can expect a reduction in power consumption. Thanks to the Bandpass Sampling (BPS) technique, the receiver addresses multiple RF bands without changing the sampling frequency. The BPS downconverts the signal to a varying Intermediate Frequencies (IF), called sliding IF. From this point on, the signal processing is in the discrete-time domain. The same clock is employed to drive a time-varying gain amplifier (TVGA), which implements a mixing process by multiplying the input with a sine or cosine centered at IF. A Double-Quadrature Low-IF frequency planning and complex signal processing avoid the problem of image signal folding in both downconversions. Behavioral modeling shows how this architecture can be utilized for LTE and IEEE802.11g standards, fulfilling the noise, linearity, and image rejection specifications. With 6 bits resolution in the TVGA gains, the quantized sine and cosine lead to a Signal-to-Distortion Ratio of 48dB. The receiver achieves an image rejection of 55dB for the LTE standard and 42dB for IEEE802.11g.