CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism

Abstract

Running discrete Fourier transform (running DFT) is being used to overcome the drawbacks of ping pong buffer technique by employing fast Fourier transform (FFT) for real time spectrum analyzer, However, the major drawback of existing MAC or CORDIC (CO-ordinate Rotational DIgital Computer) based computation of running DFT is error accumulation due to finite precision machine and iterative computation which deteriorate the output in long run. Hence, two new alternative CORDIC based architectures with trade-off area and throughput for the computation of running DFT with refreshing mechanism are proposed in this paper to circumvent the problem of error accumulation. The novelty of these two proposed architectures is low hardware complexity or high throughput and provides the spectrum updates on sample-by-sample basis within tolerable error limit. The proposed designs are implemented using verilogHDL and synthesized using commercially available 0.18μ m CMOS technology to estimate its computation performances. The first order hardware complexities of these proposed architectures are compared with existing architectures. The proposed designs in this paper have potential applications for continuous monitoring of Fourier spectrum in the domain of power spectrum analysis, biomedical signal monitoring systems and communication system.