International Journal of Parallel Programming | 2021

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing

 
 
 
 
 
 

Abstract


In recent years, $$\\hbox {optical character recognition (OCR)}$$ optical character recognition (OCR) systems have been used to digitally preserve historical archives. To transcribe historical archives into a machine-readable form, first, the documents are scanned, then an $$\\hbox {OCR}$$ OCR is applied. In order to digitize documents without the need to remove them from where they are archived, it is valuable to have a portable device that combines scanning and $$\\hbox {OCR}$$ OCR capabilities. Nowadays, there exist many commercial and open-source document digitization techniques, which are optimized for contemporary documents. However, they fail to give sufficient text recognition accuracy for transcribing historical documents due to the severe quality degradation\xa0of such documents. On the contrary, the anyOCR system, which is designed to mainly digitize historical documents, provides high accuracy. However, this comes at a cost of high computational complexity resulting in long runtime and high power consumption. To tackle these challenges, we propose a low power energy-efficient accelerator with real-time capabilities called iDocChip, which is a configurable hybrid hardware-software programmable $$\\hbox {System-on-Chip (SoC)}$$ System-on-Chip (SoC) based on anyOCR\xa0for digitizing historical documents. In this paper, we focus on one of the most crucial processing steps in the anyOCR system: Text and Image Segmentation , which makes use of a multi-resolution morphology-based algorithm. Moreover, an optimized $$\\hbox {FPGA}$$ FPGA -based hybrid architecture of this anyOCR step along with its\xa0optimized software implementations are presented. We demonstrate our results on multiple embedded and general-purpose platforms with respect to runtime and power consumption. The resulting hardware accelerator outperforms the existing anyOCR by 6.2 $$\\times$$ × , while achieving 207 $$\\times$$ × higher energy-efficiency and maintaining\xa0its high accuracy.

Volume 49
Pages 253-284
DOI 10.1007/s10766-020-00690-y
Language English
Journal International Journal of Parallel Programming

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