SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement

Abstract

Silicon debugging of integrated circuits is exacerbated by the lack of golden responses, highly restricted observability and irreproducible nature of bugs. Debug engineers need to develop better methods that can assist in error localization at lower level(netlist) granularity. It is widely accepted that root-cause analysis of electrical bugs is highly difficult which further elongates the time needed to fix them. This paper revisits methodologies to debug electrical errors through satisfiability(SAT) solving under a limited visibility environment. We propose various SAT formulations and analyze their efficacy in error localization for a variety of benchmark circuits. The selection of debugging instrumentation is an important issue in post-silicon validation. We analyze different graph-based signal tracing techniques and propose a methodology that utilizes clustering of the nodes of the circuit graph. We aim at minimizing the overhead associated with signal tracing while maintaining the error localization efficacy. We address scalability concerns in SAT solving through partitioning of large error traces. We provide localization results on two different error models (bit-flip and stuck-at) and evaluate its efficiency through a set of different metrics.