A low-area design of two-factor authentication using DIES and SBI for IoT security

Abstract

Internet of things (IoTs) is an integration of heterogeneous physical devices which are interconnected and communicated over the physical Internet. The design of secure, lightweight and an effective authentication protocol is required, because the information is transmitted among the remote user and numerous sensing devices over the IoT network. Recently, two-factor authentication (TFA) scheme is developed for providing the security among the IoT devices. But, the performances of the IoT network are affected due to the less memory storage and restricted resource of the IoT. In this paper, the integration of data inverting encoding scheme (DIES) and substitution-box-based inverter is proposed for providing the security using the random values of one-time alias identity, challenge, server nonce and device nonce. Here, the linearity of produced random values is decreased for each clock cycle based on the switching characteristics of the selection line in DIES. Moreover, the linear feedback shift register is used in the adaptive physically unclonable function (APUF) for generating the random response value. The APUF–DIES-IoT architecture is analyzed in terms of lookup table, flip flops, slices, frequency and delay. This APUF–DIES-IoT architecture is analyzed for different security and authentication performances. Two existing methods are considered to evaluate the APUF–DIES-IoT architecture such as TFA-PUF-IoT and TFA-APUF-IoT. The APUF–DIES-IoT architecture uses 36 flip flops at Virtex 6; it is less when compared to the TFA-PUF-IoT and TFA-APUF-IoT.